src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * Install of build option: Memory
   6  *
   7  * Contains AMD AGESA install macros and test conditions. Output is the
   8  * defaults tables reflecting the User's build options selection.
   9  *
  10  * @xrefitem bom "File Content Label" "Release Content"
  11  * @e project:      AGESA
  12  * @e sub-project:  Options
  13  * @e \$Revision: 37402 $   @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
  14  */
  15 /*
  16  *****************************************************************************
  17  *
  18  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * ***************************************************************************
  44  *
  45  */
  46
  47 #ifndef _OPTION_MEMORY_INSTALL_H_
  48 #define _OPTION_MEMORY_INSTALL_H_
  49
  50 /*-------------------------------------------------------------------------------
  51  *  This option file is designed to be included into the platform solution install
  52  *  file. The platform solution install file will define the options status.
  53  *  Check to validate the definition
  54  */
  55
  56 /*----------------------------------------------------------------------------------
  57  * FEATURE BLOCK FUNCTIONS
  58  *
  59  *  This section defines function names that depend upon options that are selected
  60  *  in the platform solution install file.
  61  */
  62 BOOLEAN MemFDefRet (
  63   IN OUT   MEM_NB_BLOCK *NBPtr
  64   )
  65 {
  66   return FALSE;
  67 }
  68
  69 BOOLEAN MemMDefRet (
  70   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  71   )
  72 {
  73   return TRUE;
  74 }
  75
  76 BOOLEAN MemMDefRetFalse (
  77   IN   MEM_MAIN_DATA_BLOCK *MMPtr
  78   )
  79 {
  80   return FALSE;
  81 }
  82
  83 /* -----------------------------------------------------------------------------*/
  84 /**
  85  *
  86  *
  87  *   This function initializes the northbridge block for dimm identification translator
  88  *
  89  *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
  90  *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
  91  *     @param[in,out]   NodeID   - ID of current node to construct
  92  *     @return          TRUE     - This is the correct constructor for the targeted node.
  93  *     @return          FALSE    - This isn't the correct constructor for the targeted node.
  94  */
  95 BOOLEAN MemNIdentifyDimmConstructorRetDef (
  96   IN OUT   MEM_NB_BLOCK *NBPtr,
  97   IN OUT   MEM_DATA_STRUCT *MemPtr,
  98   IN       UINT8 NodeID
  99   )
 100 {
 101   return FALSE;
 102 }
 103 /*----------------------------------------------------------------------------------
 104  * TABLE FEATURE BLOCK FUNCTIONS
 105  *
 106  *  This section defines function names that depend upon options that are selected
 107  *  in the platform solution install file.
 108  */
 109 UINT8 MemFTableDefRet (
 110   IN OUT   MEM_TABLE_ALIAS **MTPtr
 111   )
 112 {
 113   return 0;
 114 }
 115 /*----------------------------------------------------------------------------------
 116  * FEATURE S3 BLOCK FUNCTIONS
 117  *
 118  *  This section defines function names that depend upon options that are selected
 119  *  in the platform solution install file.
 120  */
 121 BOOLEAN MemFS3DefConstructorRet (
 122   IN OUT   VOID *S3NBPtr,
 123   IN OUT   MEM_DATA_STRUCT *MemPtr,
 124   IN       UINT8 NodeID
 125   )
 126 {
 127   return TRUE;
 128 }
 129
 130 #if (OPTION_MEMCTLR_DR == TRUE)
 131   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 132     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 133       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
 134       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
 135     #else
 136       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 137     #endif
 138   #else
 139     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
 140   #endif
 141   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 142     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
 143     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
 144   #else
 145     #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
 146   #endif
 147 #endif
 148
 149 #if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 150   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 151     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 152       #if (OPTION_MEMCTLR_Ni == TRUE)
 153         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
 154         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
 155       #else
 156         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 157       #endif
 158       #if (OPTION_MEMCTLR_DA == TRUE)
 159         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
 160         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
 161       #else
 162         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 163       #endif
 164       #if (OPTION_MEMCTLR_PH == TRUE)
 165         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
 166         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
 167       #else
 168         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 169       #endif
 170       #if (OPTION_MEMCTLR_RB == TRUE)
 171         extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
 172         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
 173       #else
 174         #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 175       #endif
 176     #endif
 177   #else
 178     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
 179     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
 180     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
 181     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
 182   #endif
 183   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 184     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
 185     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
 186     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
 187     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
 188     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
 189     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
 190   #else
 191     #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
 192     #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
 193     #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
 194   #endif
 195 #endif
 196
 197 #if (OPTION_MEMCTLR_OR == TRUE)
 198   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 199     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 200       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
 201       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
 202     #else
 203       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 204     #endif
 205   #else
 206     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
 207   #endif
 208   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 209     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
 210     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
 211   #else
 212     #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
 213   #endif
 214 #endif
 215
 216 #if (OPTION_MEMCTLR_HY == TRUE)
 217   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 218     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 219       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
 220       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
 221     #else
 222       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 223     #endif
 224   #else
 225     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
 226   #endif
 227   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 228     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
 229     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
 230   #else
 231     #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
 232   #endif
 233 #endif
 234
 235 #if (OPTION_MEMCTLR_C32 == TRUE)
 236   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 237     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 238       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
 239       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
 240     #else
 241       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 242     #endif
 243   #else
 244     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
 245   #endif
 246   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 247     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
 248     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
 249   #else
 250     #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
 251   #endif
 252 #endif
 253
 254 #if (OPTION_MEMCTLR_LN == TRUE)
 255   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 256     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 257       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
 258       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
 259     #else
 260       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
 261     #endif
 262   #else
 263     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
 264   #endif
 265   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 266     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
 267     #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
 268   #else
 269     #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
 270   #endif
 271 #endif
 272
 273 #if (OPTION_MEMCTLR_ON == TRUE)
 274   #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
 275     #if (OPTION_S3_MEM_SUPPORT == TRUE)
 276       extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
 277       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
 278     #else
 279       #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
 280     #endif
 281   #else
 282     #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
 283   #endif
 284   #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
 285     extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
 286     #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
 287   #else
 288     #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
 289   #endif
 290 #endif
 291
 292 /*----------------------------------------------------------------------------------
 293  * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
 294  *
 295  *----------------------------------------------------------------------------------
 296 */
 297 #define MEM_NB_SUPPORT_DR
 298 #define MEM_NB_SUPPORT_RB
 299 #define MEM_NB_SUPPORT_DA
 300 #define MEM_NB_SUPPORT_Ni
 301 #define MEM_NB_SUPPORT_PH
 302 #define MEM_NB_SUPPORT_HY
 303 #define MEM_NB_SUPPORT_LN
 304 #define MEM_NB_SUPPORT_OR
 305 #define MEM_NB_SUPPORT_C32
 306 #define MEM_NB_SUPPORT_ON
 307 #define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
 308
 309 #if (AGESA_ENTRY_INIT_POST == TRUE)
 310   /*----------------------------------------------------------------------------------
 311    * FLOW CONTROL FUNCTION
 312    *
 313    *  This section selects the function that controls the memory initialization sequence
 314    *  based upon the number of processor families that the BIOS will support.
 315    */
 316
 317   extern MEM_FLOW_CFG MemMFlowDef;
 318   #if (OPTION_MEMCTLR_DR == TRUE)
 319     extern MEM_FLOW_CFG MemMFlowDr;
 320     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
 321   #else
 322     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
 323   #endif
 324   #if (OPTION_MEMCTLR_DA == TRUE)
 325     extern MEM_FLOW_CFG MemMFlowDA;
 326     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
 327   #else
 328     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
 329   #endif
 330   #if (OPTION_MEMCTLR_HY == TRUE)
 331     extern MEM_FLOW_CFG MemMFlowHy;
 332     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
 333   #else
 334     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
 335   #endif
 336   #if (OPTION_MEMCTLR_OR == TRUE)
 337     extern MEM_FLOW_CFG MemMFlowOr;
 338     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
 339   #else
 340     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
 341   #endif
 342   #if (OPTION_MEMCTLR_LN == TRUE)
 343     extern MEM_FLOW_CFG MemMFlowLN;
 344     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
 345   #else
 346     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
 347   #endif
 348   #if (OPTION_MEMCTLR_C32 == TRUE)
 349     extern MEM_FLOW_CFG MemMFlowC32;
 350     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
 351   #else
 352     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
 353   #endif
 354   #if (OPTION_MEMCTLR_ON == TRUE)
 355     extern MEM_FLOW_CFG MemMFlowON;
 356     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
 357   #else
 358     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
 359   #endif
 360   #if (OPTION_MEMCTLR_Ni == TRUE)
 361     extern MEM_FLOW_CFG MemMFlowDA;
 362     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
 363   #else
 364     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
 365   #endif
 366   #if (OPTION_MEMCTLR_RB == TRUE)
 367     extern MEM_FLOW_CFG MemMFlowRb;
 368     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
 369   #else
 370     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
 371   #endif
 372   #if (OPTION_MEMCTLR_PH == TRUE)
 373     extern MEM_FLOW_CFG MemMFlowPh;
 374     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
 375   #else
 376     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
 377   #endif
 378
 379   MEM_FLOW_CFG* memFlowControlInstalled[] = {
 380     MEM_MAIN_FLOW_CONTROL_PTR_Dr
 381     MEM_MAIN_FLOW_CONTROL_PTR_DA
 382     MEM_MAIN_FLOW_CONTROL_PTR_RB
 383     MEM_MAIN_FLOW_CONTROL_PTR_PH
 384     MEM_MAIN_FLOW_CONTROL_PTR_Hy
 385     MEM_MAIN_FLOW_CONTROL_PTR_OR
 386     MEM_MAIN_FLOW_CONTROL_PTR_LN
 387     MEM_MAIN_FLOW_CONTROL_PTR_C32
 388     MEM_MAIN_FLOW_CONTROL_PTR_ON
 389     MEM_MAIN_FLOW_CONTROL_PTR_Ni
 390     NULL
 391   };
 392
 393   #if (OPTION_ONLINE_SPARE == TRUE)
 394     extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
 395     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
 396     extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
 397     #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
 398   #else
 399     #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
 400     #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
 401   #endif
 402
 403   #if (OPTION_MEM_RESTORE == TRUE)
 404     extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
 405     extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
 406     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
 407     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
 408   #else
 409     #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
 410     #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
 411   #endif
 412
 413   #if (OPTION_BANK_INTERLEAVE == TRUE)
 414     extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
 415     #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
 416     extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
 417     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
 418   #else
 419     #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
 420     #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
 421   #endif
 422
 423   #if (OPTION_NODE_INTERLEAVE == TRUE)
 424     extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
 425     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
 426     extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
 427     extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
 428     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
 429     #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
 430   #else
 431     #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
 432     #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
 433     #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
 434   #endif
 435
 436   #if (OPTION_DCT_INTERLEAVE == TRUE)
 437     extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
 438     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
 439   #else
 440     #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
 441   #endif
 442
 443   #if (OPTION_ECC == TRUE)
 444     extern OPTION_MEM_FEATURE_MAIN MemMEcc;
 445     #define MEM_MAIN_FEATURE_ECC  MemMEcc
 446     extern OPTION_MEM_FEATURE_NB MemFCheckECC;
 447     extern OPTION_MEM_FEATURE_NB MemFInitECC;
 448     #define MEM_FEATURE_CK_ECC   MemFCheckECC
 449     #define MEM_FEATURE_ECC   MemFInitECC
 450     #define MEM_FEATURE_ECCX8  MemMDefRet
 451   #else
 452     #define MEM_MAIN_FEATURE_ECC  MemMDefRet
 453     #define MEM_FEATURE_CK_ECC   MemFDefRet
 454     #define MEM_FEATURE_ECC   MemFDefRet
 455     #define MEM_FEATURE_ECCX8  MemMDefRet
 456   #endif
 457
 458   extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
 459   #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
 460
 461   #if (OPTION_DMI == TRUE)
 462     #if (OPTION_DDR3 == TRUE)
 463       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
 464       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
 465     #else
 466       extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
 467       #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
 468     #endif
 469   #else
 470     #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
 471   #endif
 472
 473   #if (OPTION_DDR3 == TRUE)
 474     extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
 475     extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
 476     extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
 477     #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
 478     #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
 479     #define MEM_FEATURE_LVDDR3 MemFLvDdr3
 480   #else
 481     #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
 482     #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
 483     #define MEM_FEATURE_LVDDR3 MemFDefRet
 484   #endif
 485
 486   extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
 487   #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
 488
 489   extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
 490   #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
 491
 492   extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 493   #if (OPTION_PARALLEL_TRAINING == TRUE)
 494     extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
 495     #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
 496   #else
 497     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 498   #endif
 499
 500   #if (OPTION_DIMM_EXCLUDE == TRUE)
 501     extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
 502     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
 503     extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
 504     #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
 505   #else
 506     #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
 507     #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
 508   #endif
 509
 510   /*----------------------------------------------------------------------------------
 511    * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
 512    *
 513    *----------------------------------------------------------------------------------
 514   */
 515   #if OPTION_DDR2 == TRUE
 516     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
 517     #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
 518     #if (OPTION_HW_DRAM_INIT == TRUE)
 519       extern MEM_TECH_FEAT MemTDramInitHw;
 520       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 521     #else
 522       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
 523     #endif
 524     #if (OPTION_SW_DRAM_INIT == TRUE)
 525       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 526     #else
 527       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 528     #endif
 529   #else
 530     #define MEM_TECH_CONSTRUCTOR_DDR2
 531   #endif
 532   #if OPTION_DDR3 == TRUE
 533     extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
 534     #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
 535     #if (OPTION_HW_DRAM_INIT == TRUE)
 536       extern MEM_TECH_FEAT MemTDramInitHw;
 537       #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
 538     #else
 539       #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
 540     #endif
 541     #if (OPTION_SW_DRAM_INIT == TRUE)
 542 //      extern MEM_TECH_FEAT MemTDramInitSw3;
 543       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
 544     #else
 545       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
 546     #endif
 547   #else
 548     #define MEM_TECH_CONSTRUCTOR_DDR3
 549   #endif
 550
 551   /*---------------------------------------------------------------------------------------------------
 552    * FEATURE BLOCKS
 553    *
 554    *  This section instantiates a feature block structure for each memory controller installed
 555    *  by the platform solution install file.
 556    *---------------------------------------------------------------------------------------------------
 557    */
 558
 559   /*---------------------------------------------------------------------------------------------------
 560    * DEERHOUND FEATURE BLOCK
 561    *---------------------------------------------------------------------------------------------------
 562    */
 563   #if (OPTION_MEMCTLR_DR == TRUE)
 564     #if OPTION_DDR2
 565       #undef MEM_TECH_FEATURE_DRAMINIT
 566       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 567     #endif
 568     #if OPTION_DDR3
 569       #undef MEM_TECH_FEATURE_DRAMINIT
 570       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 571     #endif
 572
 573     #undef MEM_TECH_FEATURE_CPG
 574     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 575
 576     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 577       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 578       #undef MEM_TECH_FEATURE_HWRXEN
 579       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 580     #else
 581       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 582       #undef MEM_TECH_FEATURE_HWRXEN
 583       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 584     #endif
 585
 586     #undef MEM_MAIN_FEATURE_TRAINING
 587     #undef MEM_FEATURE_TRAINING
 588     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 589     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 590     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 591     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 592
 593     MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
 594       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 595       MEM_FEATURE_ONLINE_SPARE,
 596       MEM_FEATURE_BANK_INTERLEAVE,
 597       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 598       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 599       MEM_FEATURE_NODE_INTERLEAVE,
 600       MEM_FEATURE_CHANNEL_INTERLEAVE,
 601       MemFDefRet,
 602       MEM_FEATURE_CK_ECC,
 603       MEM_FEATURE_ECC,
 604       MEM_FEATURE_TRAINING,
 605       MEM_FEATURE_LVDDR3,
 606       MemFDefRet,
 607       MEM_TECH_FEATURE_DRAMINIT,
 608       MEM_FEATURE_DIMM_EXCLUDE,
 609       MemFDefRet,
 610       MEM_TECH_FEATURE_CPG,
 611       MEM_TECH_FEATURE_HWRXEN
 612     };
 613
 614     #undef MEM_NB_SUPPORT_DR
 615     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
 616     extern MEM_INITIALIZER MemNInitDefaultsDR;
 617
 618
 619     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
 620   #endif // OPTION_MEMCTRL_DR
 621
 622   /*---------------------------------------------------------------------------------------------------
 623    * DASHOUND FEATURE BLOCK
 624    *---------------------------------------------------------------------------------------------------
 625    */
 626   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
 627     #if OPTION_DDR2
 628       #undef MEM_TECH_FEATURE_DRAMINIT
 629       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 630     #endif
 631     #if OPTION_DDR3
 632       #undef MEM_TECH_FEATURE_DRAMINIT
 633       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 634     #endif
 635
 636     #undef MEM_TECH_FEATURE_CPG
 637     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 638
 639     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 640       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 641       #undef MEM_TECH_FEATURE_HWRXEN
 642       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 643     #else
 644       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 645       #undef MEM_TECH_FEATURE_HWRXEN
 646       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 647     #endif
 648
 649     #undef MEM_MAIN_FEATURE_TRAINING
 650     #undef MEM_FEATURE_TRAINING
 651     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 652     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 653     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 654     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 655
 656     #if (OPTION_MEMCTLR_Ni == TRUE)
 657       MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
 658         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 659         MemFDefRet,
 660         MEM_FEATURE_BANK_INTERLEAVE,
 661         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 662         MemFDefRet,
 663         MemFDefRet,
 664         MEM_FEATURE_CHANNEL_INTERLEAVE,
 665         MEM_FEATURE_REGION_INTERLEAVE,
 666         MEM_FEATURE_CK_ECC,
 667         MEM_FEATURE_ECC,
 668         MEM_FEATURE_TRAINING,
 669         MEM_FEATURE_LVDDR3,
 670         MemFDefRet,
 671         MEM_TECH_FEATURE_DRAMINIT,
 672         MEM_FEATURE_DIMM_EXCLUDE,
 673         MemFDefRet,
 674         MEM_TECH_FEATURE_CPG,
 675         MEM_TECH_FEATURE_HWRXEN
 676       };
 677
 678       #undef MEM_NB_SUPPORT_Ni
 679       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
 680       extern MEM_INITIALIZER MemNInitDefaultsNi;
 681
 682       #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
 683     #endif
 684
 685     #if (OPTION_MEMCTLR_PH == TRUE)
 686       MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
 687         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 688         MemFDefRet,
 689         MEM_FEATURE_BANK_INTERLEAVE,
 690         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 691         MemFDefRet,
 692         MemFDefRet,
 693         MEM_FEATURE_CHANNEL_INTERLEAVE,
 694         MEM_FEATURE_REGION_INTERLEAVE,
 695         MEM_FEATURE_CK_ECC,
 696         MEM_FEATURE_ECC,
 697         MEM_FEATURE_TRAINING,
 698         MEM_FEATURE_LVDDR3,
 699         MemFDefRet,
 700         MEM_TECH_FEATURE_DRAMINIT,
 701         MEM_FEATURE_DIMM_EXCLUDE,
 702         MemFDefRet,
 703         MEM_TECH_FEATURE_CPG,
 704         MEM_TECH_FEATURE_HWRXEN
 705       };
 706
 707       #undef MEM_NB_SUPPORT_PH
 708       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
 709       extern MEM_INITIALIZER MemNInitDefaultsPh;
 710
 711       #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
 712     #endif
 713
 714     #if (OPTION_MEMCTLR_RB == TRUE)
 715       MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
 716         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 717         MemFDefRet,
 718         MEM_FEATURE_BANK_INTERLEAVE,
 719         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 720         MemFDefRet,
 721         MemFDefRet,
 722         MEM_FEATURE_CHANNEL_INTERLEAVE,
 723         MEM_FEATURE_REGION_INTERLEAVE,
 724         MEM_FEATURE_CK_ECC,
 725         MEM_FEATURE_ECC,
 726         MEM_FEATURE_TRAINING,
 727         MEM_FEATURE_LVDDR3,
 728         MemFDefRet,
 729         MEM_TECH_FEATURE_DRAMINIT,
 730         MEM_FEATURE_DIMM_EXCLUDE,
 731         MemFDefRet,
 732         MEM_TECH_FEATURE_CPG,
 733         MEM_TECH_FEATURE_HWRXEN
 734       };
 735
 736       #undef MEM_NB_SUPPORT_RB
 737       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
 738       extern MEM_INITIALIZER MemNInitDefaultsRb;
 739
 740       #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
 741     #endif
 742
 743     #if (OPTION_MEMCTLR_DA == TRUE)
 744       MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
 745         MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 746         MemFDefRet,
 747         MEM_FEATURE_BANK_INTERLEAVE,
 748         MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 749         MemFDefRet,
 750         MemFDefRet,
 751         MEM_FEATURE_CHANNEL_INTERLEAVE,
 752         MEM_FEATURE_REGION_INTERLEAVE,
 753         MEM_FEATURE_CK_ECC,
 754         MEM_FEATURE_ECC,
 755         MEM_FEATURE_TRAINING,
 756         MEM_FEATURE_LVDDR3,
 757         MemFDefRet,
 758         MEM_TECH_FEATURE_DRAMINIT,
 759         MEM_FEATURE_DIMM_EXCLUDE,
 760         MemFDefRet,
 761         MEM_TECH_FEATURE_CPG,
 762         MEM_TECH_FEATURE_HWRXEN
 763       };
 764
 765       #undef MEM_NB_SUPPORT_DA
 766       extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
 767       extern MEM_INITIALIZER MemNInitDefaultsDA;
 768
 769       #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
 770     #endif
 771   #endif // OPTION_MEMCTRL_DA
 772
 773   /*---------------------------------------------------------------------------------------------------
 774    * HYDRA FEATURE BLOCK
 775    *---------------------------------------------------------------------------------------------------
 776    */
 777   #if (OPTION_MEMCTLR_HY == TRUE)
 778     #if OPTION_DDR2
 779       #undef MEM_TECH_FEATURE_DRAMINIT
 780       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 781     #endif
 782     #if OPTION_DDR3
 783       #undef MEM_TECH_FEATURE_DRAMINIT
 784       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 785     #endif
 786
 787     #undef MEM_TECH_FEATURE_CPG
 788     #define MEM_TECH_FEATURE_CPG    MemFDefRet
 789
 790     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 791       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 792       #undef MEM_TECH_FEATURE_HWRXEN
 793       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 794     #else
 795       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 796       #undef MEM_TECH_FEATURE_HWRXEN
 797       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 798     #endif
 799
 800
 801     #undef MEM_MAIN_FEATURE_TRAINING
 802     #undef MEM_FEATURE_TRAINING
 803     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 804     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 805     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 806     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 807
 808     MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
 809       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 810       MEM_FEATURE_ONLINE_SPARE,
 811       MEM_FEATURE_BANK_INTERLEAVE,
 812       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 813       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
 814       MEM_FEATURE_NODE_INTERLEAVE,
 815       MEM_FEATURE_CHANNEL_INTERLEAVE,
 816       MemFDefRet,
 817       MEM_FEATURE_CK_ECC,
 818       MEM_FEATURE_ECC,
 819       MEM_FEATURE_TRAINING,
 820       MEM_FEATURE_LVDDR3,
 821       MEM_FEATURE_ONDIMMTHERMAL,
 822       MEM_TECH_FEATURE_DRAMINIT,
 823       MEM_FEATURE_DIMM_EXCLUDE,
 824       MemFDefRet,
 825       MEM_TECH_FEATURE_CPG,
 826       MEM_TECH_FEATURE_HWRXEN
 827     };
 828
 829     #undef MEM_NB_SUPPORT_HY
 830     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
 831     extern MEM_INITIALIZER MemNInitDefaultsHY;
 832     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
 833   #endif // OPTION_MEMCTRL_HY
 834   /*---------------------------------------------------------------------------------------------------
 835    * LLANO FEATURE BLOCK
 836    *---------------------------------------------------------------------------------------------------
 837    */
 838   #if (OPTION_MEMCTLR_LN == TRUE)
 839     #if OPTION_DDR2
 840       #undef MEM_TECH_FEATURE_DRAMINIT
 841       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 842     #endif
 843     #if OPTION_DDR3
 844       #undef MEM_TECH_FEATURE_DRAMINIT
 845       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 846     #endif
 847
 848     #if (OPTION_EARLY_SAMPLES == TRUE)
 849       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN;
 850       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportLN
 851     #else
 852       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
 853     #endif
 854
 855     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
 856       extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
 857       #undef MEM_TECH_FEATURE_CPG
 858       #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
 859     #else
 860       #undef MEM_TECH_FEATURE_CPG
 861       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 862     #endif
 863
 864     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 865       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 866       #undef MEM_TECH_FEATURE_HWRXEN
 867       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 868     #else
 869       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 870       #undef MEM_TECH_FEATURE_HWRXEN
 871       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 872     #endif
 873
 874     #undef MEM_MAIN_FEATURE_TRAINING
 875     #undef MEM_FEATURE_TRAINING
 876     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
 877     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 878     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 879     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 880
 881     MEM_FEAT_BLOCK_NB  MemFeatBlockLn = {
 882       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 883       MemFDefRet,
 884       MEM_FEATURE_BANK_INTERLEAVE,
 885       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 886       MemFDefRet,
 887       MemFDefRet,
 888       MEM_FEATURE_CHANNEL_INTERLEAVE,
 889       MEM_FEATURE_REGION_INTERLEAVE,
 890       MEM_FEATURE_CK_ECC,
 891       MemFDefRet,
 892       MEM_FEATURE_TRAINING,
 893       MEM_FEATURE_LVDDR3,
 894       MEM_FEATURE_ONDIMMTHERMAL,
 895       MEM_TECH_FEATURE_DRAMINIT,
 896       MEM_FEATURE_DIMM_EXCLUDE,
 897       MEM_EARLY_SAMPLE_SUPPORT,
 898       MEM_TECH_FEATURE_CPG,
 899       MEM_TECH_FEATURE_HWRXEN
 900     };
 901     #undef MEM_NB_SUPPORT_LN
 902     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
 903     extern MEM_INITIALIZER MemNInitDefaultsLN;
 904     #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
 905
 906   #endif // OPTION_MEMCTRL_LN
 907
 908   /*---------------------------------------------------------------------------------------------------
 909    * ONTARIO FEATURE BLOCK
 910    *---------------------------------------------------------------------------------------------------
 911    */
 912   #if (OPTION_MEMCTLR_ON == TRUE)
 913     #if OPTION_DDR2
 914       #undef MEM_TECH_FEATURE_DRAMINIT
 915       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 916     #endif
 917     #if OPTION_DDR3
 918       #undef MEM_TECH_FEATURE_DRAMINIT
 919       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 920     #endif
 921
 922     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
 923       extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
 924       #undef MEM_TECH_FEATURE_CPG
 925       #define MEM_TECH_FEATURE_CPG    MemNInitCPGClientNb
 926     #else
 927       #undef MEM_TECH_FEATURE_CPG
 928       #define MEM_TECH_FEATURE_CPG    MemFDefRet
 929     #endif
 930
 931     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
 932       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
 933       #undef MEM_TECH_FEATURE_HWRXEN
 934       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
 935     #else
 936       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
 937       #undef MEM_TECH_FEATURE_HWRXEN
 938       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
 939     #endif
 940
 941     #undef MEM_MAIN_FEATURE_TRAINING
 942     #undef MEM_FEATURE_TRAINING
 943     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
 944     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
 945     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 946
 947     #if (OPTION_EARLY_SAMPLES == TRUE)
 948       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
 949       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportON
 950     #else
 951       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
 952     #endif
 953
 954     MEM_FEAT_BLOCK_NB  MemFeatBlockOn = {
 955       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
 956       MemFDefRet,
 957       MEM_FEATURE_BANK_INTERLEAVE,
 958       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
 959       MemFDefRet,
 960       MemFDefRet,
 961       MemFDefRet,
 962       MemFDefRet,
 963       MemFDefRet,
 964       MemFDefRet,
 965       MEM_FEATURE_TRAINING,
 966       MEM_FEATURE_LVDDR3,
 967       MEM_FEATURE_ONDIMMTHERMAL,
 968       MEM_TECH_FEATURE_DRAMINIT,
 969       MEM_FEATURE_DIMM_EXCLUDE,
 970       MEM_EARLY_SAMPLE_SUPPORT,
 971       MEM_TECH_FEATURE_CPG,
 972       MEM_TECH_FEATURE_HWRXEN
 973     };
 974
 975     #undef MEM_NB_SUPPORT_ON
 976     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
 977     extern MEM_INITIALIZER MemNInitDefaultsON;
 978     #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
 979
 980   #endif // OPTION_MEMCTRL_ON
 981
 982   /*---------------------------------------------------------------------------------------------------
 983    * OROCHI FEATURE BLOCK
 984    *---------------------------------------------------------------------------------------------------
 985    */
 986   #if (OPTION_MEMCTLR_OR == TRUE)
 987     #if OPTION_DDR2
 988       #undef MEM_TECH_FEATURE_DRAMINIT
 989       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
 990     #endif
 991     #if OPTION_DDR3
 992       #undef MEM_MAIN_FEATURE_LVDDR3
 993       extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
 994       #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
 995       #undef MEM_TECH_FEATURE_DRAMINIT
 996       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
 997     #endif
 998
 999     #if (OPTION_EARLY_SAMPLES == TRUE)
1000       extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
1001       #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
1002     #else
1003       #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
1004     #endif
1005
1006     #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
1007       extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
1008       #undef MEM_TECH_FEATURE_CPG
1009       #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
1010     #else
1011       #undef MEM_TECH_FEATURE_CPG
1012       #define MEM_TECH_FEATURE_CPG    MemFDefRet
1013     #endif
1014
1015     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1016       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
1017       #undef MEM_TECH_FEATURE_HWRXEN
1018       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
1019     #else
1020       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
1021       #undef MEM_TECH_FEATURE_HWRXEN
1022       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
1023     #endif
1024
1025
1026     #undef MEM_MAIN_FEATURE_TRAINING
1027     #undef MEM_FEATURE_TRAINING
1028     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
1029     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
1030     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
1031     #define MEM_FEATURE_TRAINING  MemFStandardTraining
1032
1033     MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
1034       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
1035       MEM_FEATURE_ONLINE_SPARE,
1036       MEM_FEATURE_BANK_INTERLEAVE,
1037       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
1038       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
1039       MEM_FEATURE_NODE_INTERLEAVE,
1040       MEM_FEATURE_CHANNEL_INTERLEAVE,
1041       MemFDefRet,
1042       MEM_FEATURE_CK_ECC,
1043       MEM_FEATURE_ECC,
1044       MEM_FEATURE_TRAINING,
1045       MEM_FEATURE_LVDDR3,
1046       MEM_FEATURE_ONDIMMTHERMAL,
1047       MEM_TECH_FEATURE_DRAMINIT,
1048       MEM_FEATURE_DIMM_EXCLUDE,
1049       MEM_EARLY_SAMPLE_SUPPORT,
1050       MEM_TECH_FEATURE_CPG,
1051       MEM_TECH_FEATURE_HWRXEN
1052     };
1053
1054     #undef MEM_NB_SUPPORT_OR
1055     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
1056     extern MEM_INITIALIZER MemNInitDefaultsOR;
1057     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
1058   #endif // OPTION_MEMCTRL_OR
1059
1060   /*---------------------------------------------------------------------------------------------------
1061    * C32 FEATURE BLOCK
1062    *---------------------------------------------------------------------------------------------------
1063    */
1064   #if (OPTION_MEMCTLR_C32 == TRUE)
1065     #if OPTION_DDR2
1066       #undef MEM_TECH_FEATURE_DRAMINIT
1067       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
1068     #endif
1069     #if OPTION_DDR3
1070       #undef MEM_TECH_FEATURE_DRAMINIT
1071       #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
1072     #endif
1073
1074     #undef MEM_TECH_FEATURE_CPG
1075     #define MEM_TECH_FEATURE_CPG    MemFDefRet
1076
1077     #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1078       extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
1079       #undef MEM_TECH_FEATURE_HWRXEN
1080       #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
1081     #else
1082       extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
1083       #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
1084     #endif
1085
1086     #undef MEM_MAIN_FEATURE_TRAINING
1087     #undef MEM_FEATURE_TRAINING
1088     extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
1089     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
1090     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
1091     #define MEM_FEATURE_TRAINING  MemFStandardTraining
1092
1093     MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
1094       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
1095       MEM_FEATURE_ONLINE_SPARE,
1096       MEM_FEATURE_BANK_INTERLEAVE,
1097       MEM_FEATURE_UNDO_BANK_INTERLEAVE,
1098       MEM_FEATURE_NODE_INTERLEAVE_CHECK,
1099       MEM_FEATURE_NODE_INTERLEAVE,
1100       MEM_FEATURE_CHANNEL_INTERLEAVE,
1101       MemFDefRet,
1102       MEM_FEATURE_CK_ECC,
1103       MEM_FEATURE_ECC,
1104       MEM_FEATURE_TRAINING,
1105       MEM_FEATURE_LVDDR3,
1106       MEM_FEATURE_ONDIMMTHERMAL,
1107       MEM_TECH_FEATURE_DRAMINIT,
1108       MEM_FEATURE_DIMM_EXCLUDE,
1109       MemFDefRet,
1110       MEM_TECH_FEATURE_CPG,
1111       MEM_TECH_FEATURE_HWRXEN
1112     };
1113
1114     #undef MEM_NB_SUPPORT_C32
1115     extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
1116     extern MEM_INITIALIZER MemNInitDefaultsC32;
1117     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
1118   #endif // OPTION_MEMCTRL_C32
1119
1120   /*---------------------------------------------------------------------------------------------------
1121    * MAIN FEATURE BLOCK
1122    *---------------------------------------------------------------------------------------------------
1123    */
1124   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
1125     MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
1126     MEM_MAIN_FEATURE_TRAINING,
1127     MEM_MAIN_FEATURE_DIMM_EXCLUDE,
1128     MEM_MAIN_FEATURE_ONLINE_SPARE,
1129     MEM_MAIN_FEATURE_NODE_INTERLEAVE,
1130     MEM_MAIN_FEATURE_ECC,
1131     MEM_MAIN_FEATURE_MEM_CLEAR,
1132     MEM_MAIN_FEATURE_MEM_DMI,
1133     MEM_MAIN_FEATURE_LVDDR3,
1134     MEM_MAIN_FEATURE_UMAALLOC,
1135     MEM_MAIN_FEATURE_MEM_SAVE,
1136     MEM_MAIN_FEATURE_MEM_RESTORE
1137   };
1138
1139
1140   /*---------------------------------------------------------------------------------------------------
1141    * Technology Training SPECIFIC CONFIGURATION
1142    *
1143    *
1144    *---------------------------------------------------------------------------------------------------
1145    */
1146   #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
1147   #if OPTION_MEMCTLR_DR
1148     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
1149     #if OPTION_DDR2
1150       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1151       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1152       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1153       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1154       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1155       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1156         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1157         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1158       #else
1159         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1160         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1161       #endif
1162       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1163         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1164       #else
1165         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1166       #endif
1167       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1168         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1169       #else
1170         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1171       #endif
1172       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1173         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1174       #else
1175         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1176       #endif
1177       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1178         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1179       #else
1180         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1181       #endif
1182       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1183         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1184       #else
1185         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1186       #endif
1187       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
1188         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1189         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1190         TECH_TRAIN_SW_WL_DDR2,
1191         TECH_TRAIN_HW_WL_P1_DDR2,
1192         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1193         TECH_TRAIN_HW_WL_P2_DDR2,
1194         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1195         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1196         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1197         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1198         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1199         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1200         TECH_TRAIN_MAX_RD_LAT_DDR2
1201       };
1202       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1203       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1204       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1205       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
1206     #else
1207       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1208       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1209       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1210       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1211       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1212       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1213       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1214       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1215       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1216       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1217       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1218       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1219       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1220       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1221     #endif
1222     #if OPTION_DDR3
1223       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1224       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1225       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1226       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1227       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1228         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1229         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1230       #else
1231         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1232         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1233       #endif
1234       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1235         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1236       #else
1237         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1238       #endif
1239       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1240         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1241         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1242       #else
1243         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1244         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1245       #endif
1246       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1247         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1248       #else
1249         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1250       #endif
1251       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1252         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1253       #else
1254         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1255       #endif
1256       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1257         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1258       #else
1259         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1260       #endif
1261       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1262         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1263       #else
1264         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1265       #endif
1266       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1267         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1268       #else
1269         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1270       #endif
1271       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1272       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1273       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1274       extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
1275       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
1276         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1277         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1278         TECH_TRAIN_SW_WL_DDR3,
1279         TECH_TRAIN_HW_WL_P1_DDR3,
1280         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1281         TECH_TRAIN_HW_WL_P2_DDR3,
1282         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1283         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1284         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1285         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1286         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1287         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1288         TECH_TRAIN_MAX_RD_LAT_DDR3
1289       };
1290       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
1291     #else
1292       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1293       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1294       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1295       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1296       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1297       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1298       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1299       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1300       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1301       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1302       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1303       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1304       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1305       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1306       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1307       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1308     #endif
1309   #else
1310     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1311     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1312   #endif
1313
1314   #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
1315     #if OPTION_DDR2
1316       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1317       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1318       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1319       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1320       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1321       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1322         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1323         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1324       #else
1325         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1326         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1327       #endif
1328       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1329         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1330       #else
1331         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1332       #endif
1333       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1334         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1335       #else
1336         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1337       #endif
1338       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1339         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1340       #else
1341         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1342       #endif
1343       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1344         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1345       #else
1346         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1347       #endif
1348       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1349         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1350       #else
1351         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1352       #endif
1353       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
1354         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1355         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1356         TECH_TRAIN_SW_WL_DDR2,
1357         TECH_TRAIN_HW_WL_P1_DDR2,
1358         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1359         TECH_TRAIN_HW_WL_P2_DDR2,
1360         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1361         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1362         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1363         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1364         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1365         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1366         TECH_TRAIN_MAX_RD_LAT_DDR2
1367       };
1368       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
1369         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1370         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1371         TECH_TRAIN_SW_WL_DDR2,
1372         TECH_TRAIN_HW_WL_P1_DDR2,
1373         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1374         TECH_TRAIN_HW_WL_P2_DDR2,
1375         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1376         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1377         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1378         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1379         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1380         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1381         TECH_TRAIN_MAX_RD_LAT_DDR2
1382       };
1383       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
1384         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1385         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1386         TECH_TRAIN_SW_WL_DDR2,
1387         TECH_TRAIN_HW_WL_P1_DDR2,
1388         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1389         TECH_TRAIN_HW_WL_P2_DDR2,
1390         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1391         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1392         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1393         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1394         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1395         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1396         TECH_TRAIN_MAX_RD_LAT_DDR2
1397       };
1398       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
1399         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1400         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1401         TECH_TRAIN_SW_WL_DDR2,
1402         TECH_TRAIN_HW_WL_P1_DDR2,
1403         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1404         TECH_TRAIN_HW_WL_P2_DDR2,
1405         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1406         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1407         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1408         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1409         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1410         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1411         TECH_TRAIN_MAX_RD_LAT_DDR2
1412       };
1413       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1414       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1415       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1416       #if (OPTION_MEMCTLR_DA)
1417         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
1418         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
1419       #else
1420         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1421       #endif
1422       #if (OPTION_MEMCTLR_PH)
1423         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
1424         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
1425       #else
1426         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1427       #endif
1428       #if (OPTION_MEMCTLR_RB)
1429         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
1430         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
1431       #else
1432         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1433       #endif
1434
1435       #if (OPTION_MEMCTLR_Ni)
1436         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
1437         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
1438       #else
1439         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1440       #endif
1441     #else
1442       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1443       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1444       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1445       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1446       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1447       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1448       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1449       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1450       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1451       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1452       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1453       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1454       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1455       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1456       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1457       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1458       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1459     #endif
1460     #if OPTION_DDR3
1461       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1462       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1463       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1464       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1465       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1466         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1467         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1468       #else
1469         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1470         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1471       #endif
1472       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1473         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1474       #else
1475         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1476       #endif
1477       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1478         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1479         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1480       #else
1481         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1482         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1483       #endif
1484       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1485         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1486       #else
1487         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1488       #endif
1489       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1490         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1491       #else
1492         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1493       #endif
1494       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1495         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1496       #else
1497         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1498       #endif
1499       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1500         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1501       #else
1502         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1503       #endif
1504       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1505         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1506       #else
1507         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1508       #endif
1509       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
1510         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1511         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1512         TECH_TRAIN_SW_WL_DDR3,
1513         TECH_TRAIN_HW_WL_P1_DDR3,
1514         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1515         TECH_TRAIN_HW_WL_P2_DDR3,
1516         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1517         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1518         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1519         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1520         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1521         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1522         TECH_TRAIN_MAX_RD_LAT_DDR3
1523       };
1524       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
1525         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1526         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1527         TECH_TRAIN_SW_WL_DDR3,
1528         TECH_TRAIN_HW_WL_P1_DDR3,
1529         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1530         TECH_TRAIN_HW_WL_P2_DDR3,
1531         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1532         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1533         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1534         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1535         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1536         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1537         TECH_TRAIN_MAX_RD_LAT_DDR3
1538       };
1539       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
1540         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1541         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1542         TECH_TRAIN_SW_WL_DDR3,
1543         TECH_TRAIN_HW_WL_P1_DDR3,
1544         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1545         TECH_TRAIN_HW_WL_P2_DDR3,
1546         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1547         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1548         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1549         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1550         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1551         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1552         TECH_TRAIN_MAX_RD_LAT_DDR3
1553       };
1554       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
1555         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1556         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1557         TECH_TRAIN_SW_WL_DDR3,
1558         TECH_TRAIN_HW_WL_P1_DDR3,
1559         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1560         TECH_TRAIN_HW_WL_P2_DDR3,
1561         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1562         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1563         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1564         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1565         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1566         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1567         TECH_TRAIN_MAX_RD_LAT_DDR3
1568       };
1569       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1570       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1571       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1572       #if (OPTION_MEMCTLR_DA)
1573         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
1574         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
1575       #else
1576         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1577       #endif
1578       #if (OPTION_MEMCTLR_PH)
1579         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
1580         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
1581       #else
1582         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1583       #endif
1584       #if (OPTION_MEMCTLR_RB)
1585         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
1586         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
1587       #else
1588         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1589       #endif
1590       #if (OPTION_MEMCTLR_Ni)
1591         extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
1592         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
1593       #else
1594         #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1595       #endif
1596     #else
1597       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1598       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1599       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1600       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1601       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1602       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1603       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1604       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1605       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1606       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1607       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1608       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1609       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1610       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1611       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1612       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1613       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1614       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1615       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1616     #endif
1617   #else
1618     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1619     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1620     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1621     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1622     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1623     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1624     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1625     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1626   #endif
1627
1628   #if OPTION_MEMCTLR_HY
1629     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
1630     #if OPTION_DDR2
1631       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1632       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1633       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1634       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1635       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1636       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1637         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1638         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1639       #else
1640         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1641         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1642       #endif
1643       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1644         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1645       #else
1646         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1647       #endif
1648       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1649         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1650       #else
1651         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1652       #endif
1653       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1654         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1655       #else
1656         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1657       #endif
1658       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1659         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1660       #else
1661         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1662       #endif
1663       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1664         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1665       #else
1666         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1667       #endif
1668       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
1669         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1670         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1671         TECH_TRAIN_SW_WL_DDR2,
1672         TECH_TRAIN_HW_WL_P1_DDR2,
1673         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1674         TECH_TRAIN_HW_WL_P2_DDR2,
1675         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1676         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1677         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1678         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1679         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1680         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1681         TECH_TRAIN_MAX_RD_LAT_DDR2
1682       };
1683       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1684       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1685       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1686       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
1687     #else
1688       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1689       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1690       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1691       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1692       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1693       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1694       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1695       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1696       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1697       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1698       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1699       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1700       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1701       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1702     #endif
1703     #if OPTION_DDR3
1704       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1705       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1706       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1707       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1708       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1709         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1710         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1711       #else
1712         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1713         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1714       #endif
1715       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1716         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1717       #else
1718         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1719       #endif
1720       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1721         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1722           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1723         #endif
1724         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
1725         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1726           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1727         #endif
1728         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
1729       #else
1730         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1731         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1732       #endif
1733       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1734         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1735       #else
1736         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1737       #endif
1738       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1739         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1740       #else
1741         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1742       #endif
1743       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1744         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1745       #else
1746         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1747       #endif
1748       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1749         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1750       #else
1751         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1752       #endif
1753       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1754         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1755       #else
1756         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1757       #endif
1758       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
1759         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1760         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1761         TECH_TRAIN_SW_WL_DDR3,
1762         TECH_TRAIN_HW_WL_P1_DDR3,
1763         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1764         TECH_TRAIN_HW_WL_P2_DDR3,
1765         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1766         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1767         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1768         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1769         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1770         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1771         TECH_TRAIN_MAX_RD_LAT_DDR3
1772       };
1773       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1774       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1775       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1776       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
1777     #else
1778       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1779       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1780       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1781       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1782       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1783       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1784       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1785       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1786       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1787       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1788       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1789       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1790       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1791       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1792       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1793       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1794     #endif
1795   #else
1796     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1797     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1798   #endif
1799
1800   #if OPTION_MEMCTLR_C32
1801     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
1802     #if OPTION_DDR2
1803       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1804       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1805       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1806       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1807       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1808       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1809         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
1810         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
1811       #else
1812         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1813         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1814       #endif
1815       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1816         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
1817       #else
1818         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1819       #endif
1820       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1821         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
1822       #else
1823         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1824       #endif
1825       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1826         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
1827       #else
1828         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1829       #endif
1830       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1831         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
1832       #else
1833         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1834       #endif
1835       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1836         #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
1837       #else
1838         #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1839       #endif
1840       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
1841         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1842         TECH_TRAIN_ENTER_HW_TRN_DDR2,
1843         TECH_TRAIN_SW_WL_DDR2,
1844         TECH_TRAIN_HW_WL_P1_DDR2,
1845         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
1846         TECH_TRAIN_HW_WL_P2_DDR2,
1847         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
1848         TECH_TRAIN_EXIT_HW_TRN_DDR2,
1849         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
1850         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
1851         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
1852         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
1853         TECH_TRAIN_MAX_RD_LAT_DDR2
1854       };
1855       extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
1856       #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
1857       extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
1858       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
1859     #else
1860       #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1861       #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1862       #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1863       #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1864       #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1865       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1866       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1867       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1868       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1869       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1870       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1871       #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1872       #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1873       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1874     #endif
1875     #if OPTION_DDR3
1876       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1877       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
1878       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1879       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
1880       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1881         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1882         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1883       #else
1884         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1885         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1886       #endif
1887       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
1888         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
1889       #else
1890         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1891       #endif
1892       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
1893         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1894           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
1895         #endif
1896         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
1897         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1898           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
1899         #endif
1900         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
1901       #else
1902         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1903         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1904       #endif
1905       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1906         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
1907       #else
1908         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1909       #endif
1910       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
1911         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
1912       #else
1913         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1914       #endif
1915       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1916         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1917       #else
1918         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1919       #endif
1920       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
1921         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
1922       #else
1923         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1924       #endif
1925       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
1926         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
1927       #else
1928         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1929       #endif
1930       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
1931         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
1932         TECH_TRAIN_ENTER_HW_TRN_DDR3,
1933         TECH_TRAIN_SW_WL_DDR3,
1934         TECH_TRAIN_HW_WL_P1_DDR3,
1935         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
1936         TECH_TRAIN_HW_WL_P2_DDR3,
1937         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
1938         TECH_TRAIN_EXIT_HW_TRN_DDR3,
1939         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
1940         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
1941         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
1942         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
1943         TECH_TRAIN_MAX_RD_LAT_DDR3
1944       };
1945       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
1946       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
1947       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
1948       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
1949     #else
1950       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1951       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
1952       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1953       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
1954       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1955       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
1956       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
1957       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1958       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
1959       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1960       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
1961       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1962       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
1963       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
1964       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1965       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1966     #endif
1967   #else
1968     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1969     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1970   #endif
1971
1972
1973   #if OPTION_MEMCTLR_LN
1974     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
1975     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
1976     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
1977     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
1978     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
1979     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1980     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
1981     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1982     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
1983     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1984     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
1985     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
1986     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
1987     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
1988     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN;
1989     #if OPTION_DDR3
1990       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
1991       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
1992       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
1993       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
1994       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
1995         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
1996         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
1997       #else
1998         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
1999         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2000       #endif
2001       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2002       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2003         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2004         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2005       #else
2006         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2007         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2008       #endif
2009       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2010         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
2011       #else
2012         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2013       #endif
2014       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2015         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
2016       #else
2017         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2018       #endif
2019       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2020         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2021       #else
2022         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2023       #endif
2024       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2025         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2026       #else
2027         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2028       #endif
2029       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2030         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2031       #else
2032         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2033       #endif
2034       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3LN = {
2035         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2036         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2037         TECH_TRAIN_SW_WL_DDR3,
2038         TECH_TRAIN_HW_WL_P1_DDR3,
2039         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2040         TECH_TRAIN_HW_WL_P2_DDR3,
2041         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2042         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2043         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2044         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2045         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2046         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2047         TECH_TRAIN_MAX_RD_LAT_DDR3
2048       };
2049       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2050       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2051       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2052       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN },
2053     #else
2054       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2055       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2056       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2057       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2058       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2059       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2060       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2061       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2062       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2063       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2064       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2065       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2066       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2067       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2068       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2069       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2070     #endif
2071   #else
2072     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2073     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2074   #endif
2075
2076
2077   #if OPTION_MEMCTLR_OR
2078     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
2079     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
2080     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
2081     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
2082     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
2083     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
2084     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2085     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
2086     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2087     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2088     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2089     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2090     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
2091     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2092     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2093     #if OPTION_DDR3
2094       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2095       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
2096       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2097       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
2098       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
2099         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
2100         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
2101       #else
2102         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2103         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2104       #endif
2105       #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
2106         #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
2107       #else
2108         #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2109       #endif
2110       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2111         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2112           #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
2113         #endif
2114         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2115         #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2116           #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
2117         #endif
2118         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2119       #else
2120         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2121         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2122       #endif
2123       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2124         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
2125       #else
2126         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2127       #endif
2128       #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
2129       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2130         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
2131       #else
2132         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2133       #endif
2134       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2135         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2136       #else
2137         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2138       #endif
2139       #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
2140       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2141         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2142       #else
2143         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2144       #endif
2145       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2146         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2147       #else
2148         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2149       #endif
2150       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
2151         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2152         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2153         TECH_TRAIN_SW_WL_DDR3,
2154         TECH_TRAIN_HW_WL_P1_DDR3,
2155         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2156         TECH_TRAIN_HW_WL_P2_DDR3,
2157         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2158         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2159         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2160         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2161         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2162         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2163         TECH_TRAIN_MAX_RD_LAT_DDR3
2164       };
2165       extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2166       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2167       extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2168       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
2169     #else
2170       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2171       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2172       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2173       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2174       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2175       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2176       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2177       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2178       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2179       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2180       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2181       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2182       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2183       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2184       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2185       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2186     #endif
2187   #else
2188     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2189     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2190   #endif
2191
2192
2193   #if OPTION_MEMCTLR_ON
2194     extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
2195     #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
2196     #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
2197     #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
2198     #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
2199     #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
2200     #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2201     #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
2202     #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2203     #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
2204     #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2205     #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
2206     #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
2207     #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2208     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2209     #if OPTION_DDR3
2210       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2211       #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTFeatDef
2212       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2213       #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTrainingClient3
2214       #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
2215         #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
2216         #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
2217       #else
2218         #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2219         #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2220       #endif
2221       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2222       #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
2223         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
2224         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
2225       #else
2226         #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2227         #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2228       #endif
2229       #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2230         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
2231       #else
2232         #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2233       #endif
2234       #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
2235       #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
2236         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
2237       #else
2238         #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2239       #endif
2240       #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2241         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2242       #else
2243         #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2244       #endif
2245       #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
2246         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
2247       #else
2248         #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2249       #endif
2250       #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
2251         #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
2252       #else
2253         #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2254       #endif
2255       MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3ON = {
2256         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
2257         TECH_TRAIN_ENTER_HW_TRN_DDR3,
2258         TECH_TRAIN_SW_WL_DDR3,
2259         TECH_TRAIN_HW_WL_P1_DDR3,
2260         TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
2261         TECH_TRAIN_HW_WL_P2_DDR3,
2262         TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
2263         TECH_TRAIN_EXIT_HW_TRN_DDR3,
2264         TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
2265         TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
2266         TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
2267         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
2268         TECH_TRAIN_MAX_RD_LAT_DDR3
2269       };
2270 //      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
2271       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
2272 //      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
2273       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
2274     #else
2275       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
2276       #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
2277       #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
2278       #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
2279       #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
2280       #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
2281       #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
2282       #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2283       #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
2284       #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2285       #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
2286       #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2287       #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
2288       #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
2289       #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
2290       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2291     #endif
2292   #else
2293     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2294     #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
2295   #endif
2296
2297   #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
2298   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
2299     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
2300     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
2301     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
2302     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN
2303     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
2304     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
2305     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
2306     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
2307     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
2308     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
2309     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2310   };
2311
2312   MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
2313     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
2314     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
2315     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
2316     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN
2317     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
2318     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
2319     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
2320     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
2321     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
2322     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
2323     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
2324   };
2325   /*---------------------------------------------------------------------------------------------------
2326    * NB TRAINING FLOW CONTROL
2327    *
2328    *
2329    *---------------------------------------------------------------------------------------------------
2330    */
2331   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
2332     NB_TRAIN_FLOW_DDR2,
2333     NB_TRAIN_FLOW_DDR3,
2334   };
2335   /*---------------------------------------------------------------------------------------------------
2336    * TECHNOLOGY BLOCK
2337    *
2338    *
2339    *---------------------------------------------------------------------------------------------------
2340    */
2341   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
2342     MEM_TECH_CONSTRUCTOR_DDR2
2343     MEM_TECH_CONSTRUCTOR_DDR3
2344     NULL
2345   };
2346    /*---------------------------------------------------------------------------------------------------
2347    * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
2348    *
2349    *
2350    *---------------------------------------------------------------------------------------------------
2351    */
2352   #if  OPTION_MEMCTLR_HY
2353     #if OPTION_UDIMMS
2354       #if OPTION_DDR2
2355         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2356       #else
2357         #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2358       #endif
2359       #if OPTION_DDR3
2360         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
2361       #else
2362         #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2363       #endif
2364     #else
2365       #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2366       #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2367     #endif
2368     #if OPTION_RDIMMS
2369       #if OPTION_DDR2
2370         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2371       #else
2372         #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2373       #endif
2374       #if OPTION_DDR3
2375         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
2376       #else
2377         #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2378       #endif
2379     #else
2380       #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2381       #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2382     #endif
2383     #if OPTION_SODIMMS
2384       #if OPTION_DDR2
2385         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2386       #else
2387         #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2388       #endif
2389       #if OPTION_DDR3
2390         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
2391       #else
2392         #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2393       #endif
2394     #else
2395       #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2396       #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2397     #endif
2398   #else
2399     #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
2400     #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
2401     #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
2402     #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
2403     #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
2404     #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
2405   #endif
2406   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
2407     PLAT_SP_HY_FF_UDIMM2
2408     PLAT_SP_HY_FF_RDIMM2
2409     PLAT_SP_HY_FF_SDIMM2
2410     PLAT_SP_HY_FF_UDIMM3
2411     PLAT_SP_HY_FF_RDIMM3
2412     PLAT_SP_HY_FF_SDIMM3
2413   };
2414
2415   #if OPTION_MEMCTLR_DR
2416     #if OPTION_UDIMMS
2417       #if OPTION_DDR2
2418         extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
2419         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
2420       #else
2421         #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2422       #endif
2423       #if OPTION_DDR3
2424         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
2425       #else
2426         #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2427       #endif
2428     #else
2429       #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2430       #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2431     #endif
2432     #if OPTION_RDIMMS
2433       #if OPTION_DDR2
2434         extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
2435         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
2436       #else
2437         #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2438       #endif
2439       #if OPTION_DDR3
2440         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
2441       #else
2442         #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2443       #endif
2444     #else
2445       #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2446       #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2447     #endif
2448     #if OPTION_SODIMMS
2449       #if OPTION_DDR2
2450         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2451       #else
2452         #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2453       #endif
2454       #if OPTION_DDR3
2455         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
2456       #else
2457         #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2458       #endif
2459     #else
2460       #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2461       #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2462     #endif
2463   #else
2464     #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
2465     #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
2466     #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
2467     #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
2468     #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
2469     #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
2470   #endif
2471   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
2472     PLAT_SP_DR_FF_UDIMM2
2473     PLAT_SP_DR_FF_RDIMM2
2474     PLAT_SP_DR_FF_SDIMM2
2475     PLAT_SP_DR_FF_UDIMM3
2476     PLAT_SP_DR_FF_RDIMM3
2477     PLAT_SP_DR_FF_SDIMM3
2478   };
2479
2480   #if (OPTION_MEMCTLR_DA == TRUE)
2481     #if OPTION_UDIMMS
2482       #if OPTION_DDR2
2483         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2484       #else
2485         #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2486       #endif
2487       #if OPTION_DDR3
2488         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
2489       #else
2490         #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2491       #endif
2492     #else
2493       #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2494       #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2495     #endif
2496     #if OPTION_RDIMMS
2497       #if OPTION_DDR2
2498         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2499       #else
2500         #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2501       #endif
2502       #if OPTION_DDR3
2503         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2504       #else
2505         #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2506       #endif
2507     #else
2508       #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2509       #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2510     #endif
2511     #if OPTION_SODIMMS
2512       #if OPTION_DDR2
2513         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
2514       #else
2515         #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2516       #endif
2517       #if OPTION_DDR3
2518         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
2519       #else
2520         #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2521       #endif
2522     #else
2523       #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2524       #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2525     #endif
2526   #else
2527     #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
2528     #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
2529     #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
2530     #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
2531     #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
2532     #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
2533   #endif
2534   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
2535     PLAT_SP_DA_FF_UDIMM2
2536     PLAT_SP_DA_FF_RDIMM2
2537     PLAT_SP_DA_FF_SDIMM2
2538     PLAT_SP_DA_FF_UDIMM3
2539     PLAT_SP_DA_FF_RDIMM3
2540     PLAT_SP_DA_FF_SDIMM3
2541   };
2542
2543   #if (OPTION_MEMCTLR_Ni == TRUE)
2544     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2545     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2546     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2547     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsSNi3,
2548     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2549     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUNi3,
2550   #else
2551     #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
2552     #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
2553     #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
2554     #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsUDef,
2555     #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
2556     #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUDef,
2557   #endif
2558   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
2559     PLAT_SP_NI_FF_UDIMM2
2560     PLAT_SP_NI_FF_RDIMM2
2561     PLAT_SP_NI_FF_SDIMM2
2562     PLAT_SP_NI_FF_UDIMM3
2563     PLAT_SP_NI_FF_RDIMM3
2564     PLAT_SP_NI_FF_SDIMM3
2565   };
2566
2567   #if (OPTION_MEMCTLR_PH == TRUE)
2568     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2569     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2570     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2571     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsSPh3,
2572     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2573     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUPh3,
2574   #else
2575     #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
2576     #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
2577     #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
2578     #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsUDef,
2579     #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
2580     #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUDef,
2581   #endif
2582   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
2583     PLAT_SP_PH_FF_UDIMM2
2584     PLAT_SP_PH_FF_RDIMM2
2585     PLAT_SP_PH_FF_SDIMM2
2586     PLAT_SP_PH_FF_UDIMM3
2587     PLAT_SP_PH_FF_RDIMM3
2588     PLAT_SP_PH_FF_SDIMM3
2589   };
2590
2591   #if (OPTION_MEMCTLR_RB == TRUE)
2592     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2593     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2594     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2595     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsSRb3,
2596     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2597     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsURb3,
2598   #else
2599     #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
2600     #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
2601     #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
2602     #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsUDef,
2603     #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
2604     #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsUDef,
2605   #endif
2606   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
2607     PLAT_SP_RB_FF_UDIMM2
2608     PLAT_SP_RB_FF_RDIMM2
2609     PLAT_SP_RB_FF_SDIMM2
2610     PLAT_SP_RB_FF_UDIMM3
2611     PLAT_SP_RB_FF_RDIMM3
2612     PLAT_SP_RB_FF_SDIMM3
2613   };
2614
2615   #if OPTION_MEMCTLR_LN
2616     #if OPTION_UDIMMS
2617       #if OPTION_DDR3
2618         #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsULN3,
2619       #else
2620         #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2621       #endif
2622     #else
2623       #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2624     #endif
2625     #if OPTION_SODIMMS
2626       #if OPTION_DDR3
2627         #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsSLN3,
2628       #else
2629         #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2630       #endif
2631     #else
2632       #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2633     #endif
2634   #else
2635     #define PLAT_SP_LN_FF_SDIMM3    MemPConstructPsUDef,
2636     #define PLAT_SP_LN_FF_UDIMM3    MemPConstructPsUDef,
2637   #endif
2638   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
2639     PLAT_SP_LN_FF_SDIMM3
2640     PLAT_SP_LN_FF_UDIMM3
2641     NULL
2642   };
2643
2644   #if  OPTION_MEMCTLR_C32
2645     #if OPTION_UDIMMS
2646       #if OPTION_DDR2
2647         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2648       #else
2649         #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2650       #endif
2651       #if OPTION_DDR3
2652         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
2653       #else
2654         #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2655       #endif
2656     #else
2657       #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2658       #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2659     #endif
2660     #if OPTION_RDIMMS
2661       #if OPTION_DDR2
2662         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2663       #else
2664         #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2665       #endif
2666       #if OPTION_DDR3
2667         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
2668       #else
2669         #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2670       #endif
2671     #else
2672       #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2673       #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2674     #endif
2675     #if OPTION_SODIMMS
2676       #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2677       #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2678     #endif
2679   #else
2680     #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
2681     #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
2682     #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
2683     #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
2684     #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
2685     #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
2686   #endif
2687   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
2688     PLAT_SP_C32_FF_UDIMM2
2689     PLAT_SP_C32_FF_RDIMM2
2690     PLAT_SP_C32_FF_SDIMM2
2691     PLAT_SP_C32_FF_UDIMM3
2692     PLAT_SP_C32_FF_RDIMM3
2693     PLAT_SP_C32_FF_SDIMM3
2694   };
2695
2696   #if OPTION_MEMCTLR_ON
2697     #if OPTION_UDIMMS
2698       #if OPTION_DDR3
2699         #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUON3,
2700       #else
2701         #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2702       #endif
2703     #else
2704       #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2705     #endif
2706     #if OPTION_SODIMMS
2707       #if OPTION_DDR3
2708         #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsSON3,
2709       #else
2710         #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2711       #endif
2712     #else
2713       #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2714     #endif
2715   #else
2716     #define PLAT_SP_ON_FF_SDIMM3    MemPConstructPsUDef,
2717     #define PLAT_SP_ON_FF_UDIMM3    MemPConstructPsUDef,
2718   #endif
2719   MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = {
2720     PLAT_SP_ON_FF_SDIMM3
2721     PLAT_SP_ON_FF_UDIMM3
2722     NULL
2723   };
2724
2725   /*---------------------------------------------------------------------------------------------------
2726    * PLATFORM-SPECIFIC CONFIGURATION
2727    *
2728    *
2729    *---------------------------------------------------------------------------------------------------
2730    */
2731
2732   #if OPTION_MEMCTLR_DR
2733     #if OPTION_UDIMMS
2734       #if OPTION_DDR2
2735         #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
2736       #else
2737         #define PSC_DR_UDIMM_DDR2
2738       #endif
2739       #if OPTION_DDR3
2740         #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
2741       #else
2742         #define PSC_DR_UDIMM_DDR3
2743       #endif
2744     #endif
2745     #if OPTION_RDIMMS
2746       #if OPTION_DDR2
2747         #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
2748       #else
2749         #define PSC_DR_RDIMM_DDR2
2750       #endif
2751       #if OPTION_DDR3
2752         #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
2753       #else
2754         #define PSC_DR_RDIMM_DDR3
2755       #endif
2756     #endif
2757     #if OPTION_SODIMMS
2758       #if OPTION_DDR2
2759         #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
2760       #else
2761         #define PSC_DR_SODIMM_DDR2
2762       #endif
2763       #if OPTION_DDR3
2764         #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
2765       #else
2766         #define PSC_DR_SODIMM_DDR3
2767       #endif
2768     #endif
2769   #endif
2770
2771   #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
2772     #if OPTION_MEMCTLR_Ni
2773       #define PSC_NI_UDIMM_DDR2
2774       #define PSC_NI_UDIMM_DDR3     MemAGetPsCfgUNi3,
2775       #define PSC_NI_RDIMM_DDR2
2776       #define PSC_NI_RDIMM_DDR3
2777       #define PSC_NI_SODIMM_DDR2
2778       #define PSC_NI_SODIMM_DDR3    MemAGetPsCfgSNi3,
2779     #endif
2780     #if OPTION_MEMCTLR_PH
2781       #define PSC_PH_UDIMM_DDR2
2782       #define PSC_PH_UDIMM_DDR3     MemAGetPsCfgUPh3,
2783       #define PSC_PH_RDIMM_DDR2
2784       #define PSC_PH_RDIMM_DDR3
2785       #define PSC_PH_SODIMM_DDR2
2786       #define PSC_PH_SODIMM_DDR3    MemAGetPsCfgSPh3,
2787     #endif
2788     #if OPTION_MEMCTLR_RB
2789       #define PSC_RB_UDIMM_DDR2
2790       #define PSC_RB_UDIMM_DDR3     MemAGetPsCfgURb3,
2791       #define PSC_RB_RDIMM_DDR2
2792       #define PSC_RB_RDIMM_DDR3
2793       #define PSC_RB_SODIMM_DDR2
2794       #define PSC_RB_SODIMM_DDR3    MemAGetPsCfgSRb3,
2795     #endif
2796     #if OPTION_MEMCTLR_DA
2797       #if OPTION_UDIMMS
2798         #if OPTION_DDR2
2799           #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
2800         #else
2801           #define PSC_DA_UDIMM_DDR2
2802         #endif
2803         #if OPTION_DDR3
2804           #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
2805         #else
2806           #define PSC_DA_UDIMM_DDR3
2807         #endif
2808       #endif
2809       #if OPTION_RDIMMS
2810         #if OPTION_DDR2
2811           #define PSC_DA_RDIMM_DDR2
2812         #else
2813           #define PSC_DA_RDIMM_DDR2
2814         #endif
2815         #if OPTION_DDR3
2816           #define PSC_DA_RDIMM_DDR3
2817         #else
2818           #define PSC_DA_RDIMM_DDR3
2819         #endif
2820       #endif
2821       #if OPTION_SODIMMS
2822         #if OPTION_DDR2
2823           #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
2824         #else
2825           #define PSC_DA_SODIMM_DDR2
2826         #endif
2827         #if OPTION_DDR3
2828           #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
2829         #else
2830           #define PSC_DA_SODIMM_DDR3
2831         #endif
2832       #endif
2833     #endif
2834   #endif
2835
2836   #if OPTION_MEMCTLR_HY
2837     #if OPTION_UDIMMS
2838       #if OPTION_DDR2
2839         #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
2840       #else
2841         #define PSC_HY_UDIMM_DDR2
2842       #endif
2843       #if OPTION_DDR3
2844         #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
2845       #else
2846         #define PSC_HY_UDIMM_DDR3
2847       #endif
2848     #endif
2849     #if OPTION_RDIMMS
2850       #if OPTION_DDR2
2851         #define PSC_HY_RDIMM_DDR2
2852       #else
2853         #define PSC_HY_RDIMM_DDR2
2854       #endif
2855       #if OPTION_DDR3
2856         #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
2857       #else
2858         #define PSC_HY_RDIMM_DDR3
2859       #endif
2860     #endif
2861     #if OPTION_SODIMMS
2862       #if OPTION_DDR2
2863         #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
2864       #else
2865         #define PSC_HY_SODIMM_DDR2
2866       #endif
2867       #if OPTION_DDR3
2868         #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
2869       #else
2870         #define PSC_HY_SODIMM_DDR3
2871       #endif
2872     #endif
2873   #endif
2874
2875   #if OPTION_MEMCTLR_C32
2876     #if OPTION_UDIMMS
2877       #if OPTION_DDR2
2878         #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
2879       #else
2880         #define PSC_C32_UDIMM_DDR2
2881       #endif
2882       #if OPTION_DDR3
2883         #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
2884       #else
2885         #define PSC_C32_UDIMM_DDR3
2886       #endif
2887     #endif
2888     #if OPTION_RDIMMS
2889       #if OPTION_DDR2
2890         #define PSC_C32_RDIMM_DDR2
2891       #else
2892         #define PSC_C32_RDIMM_DDR2
2893       #endif
2894       #if OPTION_DDR3
2895         #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
2896       #else
2897         #define PSC_C32_RDIMM_DDR3
2898       #endif
2899     #endif
2900     #if OPTION_SODIMMS
2901       #if OPTION_DDR2
2902         #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
2903       #else
2904         #define PSC_C32_SODIMM_DDR2
2905       #endif
2906       #if OPTION_DDR3
2907         #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
2908       #else
2909         #define PSC_C32_SODIMM_DDR3
2910       #endif
2911     #endif
2912   #endif
2913
2914   #if OPTION_MEMCTLR_LN
2915     #if OPTION_UDIMMS
2916       #if OPTION_DDR2
2917         #define PSC_LN_UDIMM_DDR2     //MemAGetPsCfgULN2,
2918       #else
2919         #define PSC_LN_UDIMM_DDR2
2920       #endif
2921       #if OPTION_DDR3
2922         #define PSC_LN_UDIMM_DDR3    MemAGetPsCfgULN3,
2923       #else
2924         #define PSC_LN_UDIMM_DDR3
2925       #endif
2926     #endif
2927     #if OPTION_RDIMMS
2928       #if OPTION_DDR2
2929         #define PSC_LN_RDIMM_DDR2
2930       #else
2931         #define PSC_LN_RDIMM_DDR2
2932       #endif
2933       #if OPTION_DDR3
2934         #define PSC_LN_RDIMM_DDR3    //MemAGetPsCfgRLN3,
2935       #else
2936         #define PSC_LN_RDIMM_DDR3
2937       #endif
2938     #endif
2939     #if OPTION_SODIMMS
2940       #if OPTION_DDR2
2941         #define PSC_LN_SODIMM_DDR2    //MemAGetPsCfgSLN2,
2942       #else
2943         #define PSC_LN_SODIMM_DDR2
2944       #endif
2945       #if OPTION_DDR3
2946         #define PSC_LN_SODIMM_DDR3   MemAGetPsCfgSLN3,
2947       #else
2948         #define PSC_LN_SODIMM_DDR3
2949       #endif
2950     #endif
2951   #endif
2952
2953   #if OPTION_MEMCTLR_OR
2954     #if OPTION_UDIMMS
2955       #if OPTION_DDR2
2956         #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
2957       #else
2958         #define PSC_OR_UDIMM_DDR2
2959       #endif
2960       #if OPTION_DDR3
2961         #define PSC_OR_UDIMM_DDR3     //MemAGetPsCfgUOr3,
2962       #else
2963         #define PSC_OR_UDIMM_DDR3
2964       #endif
2965     #endif
2966     #if OPTION_RDIMMS
2967       #if OPTION_DDR2
2968         #define PSC_OR_RDIMM_DDR2
2969       #else
2970         #define PSC_OR_RDIMM_DDR2
2971       #endif
2972       #if OPTION_DDR3
2973         #define PSC_OR_RDIMM_DDR3     //MemAGetPsCfgROr3,
2974       #else
2975         #define PSC_OR_RDIMM_DDR3
2976       #endif
2977     #endif
2978     #if OPTION_SODIMMS
2979       #if OPTION_DDR2
2980         #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
2981       #else
2982         #define PSC_OR_SODIMM_DDR2
2983       #endif
2984       #if OPTION_DDR3
2985         #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
2986       #else
2987         #define PSC_OR_SODIMM_DDR3
2988       #endif
2989     #endif
2990   #endif
2991
2992   #if OPTION_MEMCTLR_ON
2993     #if OPTION_UDIMMS
2994       #if OPTION_DDR2
2995         #define PSC_ON_UDIMM_DDR2     //MemAGetPsCfgUON2,
2996       #else
2997         #define PSC_ON_UDIMM_DDR2
2998       #endif
2999       #if OPTION_DDR3
3000         #define PSC_ON_UDIMM_DDR3    MemAGetPsCfgUON3,
3001       #else
3002         #define PSC_ON_UDIMM_DDR3
3003       #endif
3004     #endif
3005     #if OPTION_RDIMMS
3006       #if OPTION_DDR2
3007         #define PSC_ON_RDIMM_DDR2
3008       #else
3009         #define PSC_ON_RDIMM_DDR2
3010       #endif
3011       #if OPTION_DDR3
3012         #define PSC_ON_RDIMM_DDR3    //MemAGetPsCfgRON3,
3013       #else
3014         #define PSC_ON_RDIMM_DDR3
3015       #endif
3016     #endif
3017     #if OPTION_SODIMMS
3018       #if OPTION_DDR2
3019         #define PSC_ON_SODIMM_DDR2    //MemAGetPsCfgSON2,
3020       #else
3021         #define PSC_ON_SODIMM_DDR2
3022       #endif
3023       #if OPTION_DDR3
3024         #define PSC_ON_SODIMM_DDR3   MemAGetPsCfgSON3,
3025       #else
3026         #define PSC_ON_SODIMM_DDR3
3027       #endif
3028     #endif
3029   #endif
3030
3031   /*----------------------------------------------------------------------
3032    * DEFAULT PSCFG DEFINITIONS
3033    *
3034    *----------------------------------------------------------------------
3035    */
3036
3037   #ifndef PSC_DR_UDIMM_DDR2
3038     #define PSC_DR_UDIMM_DDR2
3039   #endif
3040   #ifndef PSC_DR_RDIMM_DDR2
3041     #define PSC_DR_RDIMM_DDR2
3042   #endif
3043   #ifndef PSC_DR_SODIMM_DDR2
3044     #define PSC_DR_SODIMM_DDR2
3045   #endif
3046   #ifndef PSC_DR_UDIMM_DDR3
3047     #define PSC_DR_UDIMM_DDR3
3048   #endif
3049   #ifndef PSC_DR_RDIMM_DDR3
3050     #define PSC_DR_RDIMM_DDR3
3051   #endif
3052   #ifndef PSC_DR_SODIMM_DDR3
3053     #define PSC_DR_SODIMM_DDR3
3054   #endif
3055   #ifndef PSC_RB_UDIMM_DDR2
3056     #define PSC_RB_UDIMM_DDR2
3057   #endif
3058   #ifndef PSC_RB_RDIMM_DDR2
3059     #define PSC_RB_RDIMM_DDR2
3060   #endif
3061   #ifndef PSC_RB_SODIMM_DDR2
3062     #define PSC_RB_SODIMM_DDR2
3063   #endif
3064   #ifndef PSC_RB_UDIMM_DDR3
3065     #define PSC_RB_UDIMM_DDR3
3066   #endif
3067   #ifndef PSC_RB_RDIMM_DDR3
3068     #define PSC_RB_RDIMM_DDR3
3069   #endif
3070   #ifndef PSC_RB_SODIMM_DDR3
3071     #define PSC_RB_SODIMM_DDR3
3072   #endif
3073   #ifndef PSC_DA_UDIMM_DDR2
3074     #define PSC_DA_UDIMM_DDR2
3075   #endif
3076   #ifndef PSC_DA_RDIMM_DDR2
3077     #define PSC_DA_RDIMM_DDR2
3078   #endif
3079   #ifndef PSC_DA_SODIMM_DDR2
3080     #define PSC_DA_SODIMM_DDR2
3081   #endif
3082   #ifndef PSC_DA_UDIMM_DDR3
3083     #define PSC_DA_UDIMM_DDR3
3084   #endif
3085   #ifndef PSC_DA_RDIMM_DDR3
3086     #define PSC_DA_RDIMM_DDR3
3087   #endif
3088   #ifndef PSC_DA_SODIMM_DDR3
3089     #define PSC_DA_SODIMM_DDR3
3090   #endif
3091   #ifndef PSC_NI_UDIMM_DDR2
3092     #define PSC_NI_UDIMM_DDR2
3093   #endif
3094   #ifndef PSC_NI_RDIMM_DDR2
3095     #define PSC_NI_RDIMM_DDR2
3096   #endif
3097   #ifndef PSC_NI_SODIMM_DDR2
3098     #define PSC_NI_SODIMM_DDR2
3099   #endif
3100   #ifndef PSC_NI_UDIMM_DDR3
3101     #define PSC_NI_UDIMM_DDR3
3102   #endif
3103   #ifndef PSC_NI_RDIMM_DDR3
3104     #define PSC_NI_RDIMM_DDR3
3105   #endif
3106   #ifndef PSC_NI_SODIMM_DDR3
3107     #define PSC_NI_SODIMM_DDR3
3108   #endif
3109   #ifndef PSC_PH_UDIMM_DDR2
3110     #define PSC_PH_UDIMM_DDR2
3111   #endif
3112   #ifndef PSC_PH_RDIMM_DDR2
3113     #define PSC_PH_RDIMM_DDR2
3114   #endif
3115   #ifndef PSC_PH_SODIMM_DDR2
3116     #define PSC_PH_SODIMM_DDR2
3117   #endif
3118   #ifndef PSC_PH_UDIMM_DDR3
3119     #define PSC_PH_UDIMM_DDR3
3120   #endif
3121   #ifndef PSC_PH_RDIMM_DDR3
3122     #define PSC_PH_RDIMM_DDR3
3123   #endif
3124   #ifndef PSC_PH_SODIMM_DDR3
3125     #define PSC_PH_SODIMM_DDR3
3126   #endif
3127   #ifndef PSC_HY_UDIMM_DDR2
3128     #define PSC_HY_UDIMM_DDR2
3129   #endif
3130   #ifndef PSC_HY_RDIMM_DDR2
3131     #define PSC_HY_RDIMM_DDR2
3132   #endif
3133   #ifndef PSC_HY_SODIMM_DDR2
3134     #define PSC_HY_SODIMM_DDR2
3135   #endif
3136   #ifndef PSC_HY_UDIMM_DDR3
3137     #define PSC_HY_UDIMM_DDR3
3138   #endif
3139   #ifndef PSC_HY_RDIMM_DDR3
3140     #define PSC_HY_RDIMM_DDR3
3141   #endif
3142   #ifndef PSC_HY_SODIMM_DDR3
3143     #define PSC_HY_SODIMM_DDR3
3144   #endif
3145   #ifndef PSC_LN_UDIMM_DDR2
3146     #define PSC_LN_UDIMM_DDR2
3147   #endif
3148   #ifndef PSC_LN_RDIMM_DDR2
3149     #define PSC_LN_RDIMM_DDR2
3150   #endif
3151   #ifndef PSC_LN_SODIMM_DDR2
3152     #define PSC_LN_SODIMM_DDR2
3153   #endif
3154   #ifndef PSC_LN_UDIMM_DDR3
3155     #define PSC_LN_UDIMM_DDR3
3156   #endif
3157   #ifndef PSC_LN_RDIMM_DDR3
3158     #define PSC_LN_RDIMM_DDR3
3159   #endif
3160   #ifndef PSC_LN_SODIMM_DDR3
3161     #define PSC_LN_SODIMM_DDR3
3162   #endif
3163   #ifndef PSC_OR_UDIMM_DDR2
3164     #define PSC_OR_UDIMM_DDR2
3165   #endif
3166   #ifndef PSC_OR_RDIMM_DDR2
3167     #define PSC_OR_RDIMM_DDR2
3168   #endif
3169   #ifndef PSC_OR_SODIMM_DDR2
3170     #define PSC_OR_SODIMM_DDR2
3171   #endif
3172   #ifndef PSC_OR_UDIMM_DDR3
3173     #define PSC_OR_UDIMM_DDR3
3174   #endif
3175   #ifndef PSC_OR_RDIMM_DDR3
3176     #define PSC_OR_RDIMM_DDR3
3177   #endif
3178   #ifndef PSC_OR_SODIMM_DDR3
3179     #define PSC_OR_SODIMM_DDR3
3180   #endif
3181   #ifndef PSC_C32_UDIMM_DDR3
3182     #define PSC_C32_UDIMM_DDR3
3183   #endif
3184   #ifndef PSC_C32_RDIMM_DDR3
3185     #define PSC_C32_RDIMM_DDR3
3186   #endif
3187   #ifndef PSC_ON_UDIMM_DDR2
3188     #define PSC_ON_UDIMM_DDR2
3189   #endif
3190   #ifndef PSC_ON_RDIMM_DDR2
3191     #define PSC_ON_RDIMM_DDR2
3192   #endif
3193   #ifndef PSC_ON_SODIMM_DDR2
3194     #define PSC_ON_SODIMM_DDR2
3195   #endif
3196   #ifndef PSC_ON_UDIMM_DDR3
3197     #define PSC_ON_UDIMM_DDR3
3198   #endif
3199   #ifndef PSC_ON_RDIMM_DDR3
3200     #define PSC_ON_RDIMM_DDR3
3201   #endif
3202   #ifndef PSC_ON_SODIMM_DDR3
3203     #define PSC_ON_SODIMM_DDR3
3204   #endif
3205
3206   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
3207     PSC_DR_UDIMM_DDR2
3208     PSC_DR_RDIMM_DDR2
3209     PSC_DR_SODIMM_DDR2
3210     PSC_DR_UDIMM_DDR3
3211     PSC_DR_RDIMM_DDR3
3212     PSC_DR_SODIMM_DDR3
3213     PSC_RB_UDIMM_DDR3
3214     PSC_RB_SODIMM_DDR3
3215     PSC_DA_SODIMM_DDR2
3216     PSC_DA_UDIMM_DDR3
3217     PSC_DA_SODIMM_DDR3
3218     PSC_NI_UDIMM_DDR3
3219     PSC_NI_SODIMM_DDR3
3220     PSC_PH_UDIMM_DDR3
3221     PSC_PH_SODIMM_DDR3
3222     PSC_HY_UDIMM_DDR3
3223     PSC_HY_RDIMM_DDR3
3224     PSC_HY_SODIMM_DDR3
3225     PSC_LN_UDIMM_DDR3
3226     PSC_LN_RDIMM_DDR3
3227     PSC_LN_SODIMM_DDR3
3228     PSC_OR_UDIMM_DDR3
3229     PSC_OR_RDIMM_DDR3
3230     PSC_OR_SODIMM_DDR3
3231     PSC_C32_UDIMM_DDR3
3232     PSC_C32_RDIMM_DDR3
3233     PSC_ON_UDIMM_DDR3
3234     PSC_ON_RDIMM_DDR3
3235     PSC_ON_SODIMM_DDR3
3236     NULL
3237   };
3238   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
3239 //  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
3240 //    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
3241 //  #endif
3242
3243   /*---------------------------------------------------------------------------------------------------
3244    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
3245    *
3246    *
3247    *---------------------------------------------------------------------------------------------------
3248    */
3249   #define MEM_PSC_FLOW_BLOCK_END NULL
3250   #define PSC_TBL_END NULL
3251   #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
3252
3253   #if OPTION_MEMCTLR_OR
3254     #if OPTION_UDIMMS
3255       #if OPTION_AM3_SOCKET_SUPPORT
3256         extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
3257         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3  &MaxFreqTblEntUAM3,
3258         extern PSC_TBL_ENTRY DramTermTblEntUAM3;
3259         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &DramTermTblEntUAM3,
3260         extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
3261         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &OdtPat1DTblEntUAM3,
3262         extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
3263         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3  &OdtPat2DTblEntUAM3,
3264         extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
3265         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &OdtPat3DTblEntUAM3,
3266         extern PSC_TBL_ENTRY SAOTblEntUAM3;
3267         #define PSC_TBL_OR_UDIMM3_SAO_AM3  &SAOTblEntUAM3,
3268         extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
3269         #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
3270       #endif
3271       #if OPTION_C32_SOCKET_SUPPORT
3272         extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
3273         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32  &MaxFreqTblEntUC32,
3274         extern PSC_TBL_ENTRY DramTermTblEntUC32;
3275         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32  &DramTermTblEntUC32,
3276         extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
3277         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntUC32,
3278         extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
3279         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntUC32,
3280         extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
3281         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntUC32,
3282         extern PSC_TBL_ENTRY SAOTblEntUC32;
3283         #define PSC_TBL_OR_UDIMM3_SAO_C32  &SAOTblEntUC32,
3284         extern PSC_TBL_ENTRY ClkDisMapEntUC32;
3285         #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
3286         extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
3287         #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
3288       #endif
3289       #if OPTION_G34_SOCKET_SUPPORT
3290         extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
3291         #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34  &MaxFreqTblEntUG34,
3292         extern PSC_TBL_ENTRY DramTermTblEntUG34;
3293         #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34  &DramTermTblEntUG34,
3294         extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
3295         #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntUG34,
3296         extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
3297         #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntUG34,
3298         extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
3299         #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntUG34,
3300         extern PSC_TBL_ENTRY SAOTblEntUG34;
3301         #define PSC_TBL_OR_UDIMM3_SAO_G34  &SAOTblEntUG34,
3302         extern PSC_TBL_ENTRY ClkDisMapEntUG34;
3303         #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
3304       #endif
3305     #endif
3306     #if OPTION_RDIMMS
3307       #if OPTION_C32_SOCKET_SUPPORT
3308         extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
3309         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32  &MaxFreqTblEntRC32,
3310         extern PSC_TBL_ENTRY DramTermTblEntRC32;
3311         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32  &DramTermTblEntRC32,
3312         extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
3313         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntRC32,
3314         extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
3315         #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntRC32,
3316         extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
3317         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntRC32,
3318         extern PSC_TBL_ENTRY SAOTblEntRC32;
3319         #define PSC_TBL_OR_RDIMM3_SAO_C32  &SAOTblEntRC32,
3320         extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
3321         #define PSC_TBL_OR_RDIMM3_RC2IBT_C32  &RC2IBTTblEntRC32,
3322         extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
3323         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32  &RC10OpSpdTblEntRC32,
3324         extern PSC_TBL_ENTRY ClkDisMapEntRC32;
3325         #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
3326       #endif
3327       #if OPTION_G34_SOCKET_SUPPORT
3328         extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
3329         #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34  &MaxFreqTblEntRG34,
3330         extern PSC_TBL_ENTRY DramTermTblEntRG34;
3331         #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34  &DramTermTblEntRG34,
3332         extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
3333         #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntRG34,
3334         extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
3335         #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntRG34,
3336         extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
3337         #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntRG34,
3338         extern PSC_TBL_ENTRY SAOTblEntRG34;
3339         #define PSC_TBL_OR_RDIMM3_SAO_G34  &SAOTblEntRG34,
3340         extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
3341         #define PSC_TBL_OR_RDIMM3_RC2IBT_G34  &RC2IBTTblEntRG34,
3342         extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
3343         #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34  &RC10OpSpdTblEntRG34,
3344         extern PSC_TBL_ENTRY ClkDisMapEntRG34;
3345         #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
3346       #endif
3347     #endif
3348     //#if OPTION_SODIMMS
3349     //#endif
3350     //#if OPTION_LRDIMMS
3351     //  #if OPTION_C32_SOCKET_SUPPORT
3352     //    extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
3353     //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32  &MaxFreqTblEntLRC32,
3354     //    extern PSC_TBL_ENTRY DramTermTblEntLRC32;
3355     //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32  &DramTermTblEntLRC32,
3356     //    extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
3357     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntLRC32,
3358     //    extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
3359     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32  &OdtPat2DTblEntLRC32,
3360     //    extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
3361     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntLRC32,
3362     //    extern PSC_TBL_ENTRY SAOTblEntRC32;
3363     //    #define PSC_TBL_OR_LRDIMM3_SAO_C32  &SAOTblEntLRC32,
3364     //    extern PSC_TBL_ENTRY IBTTblEntLRC32;
3365     //    #define PSC_TBL_OR_LRDIMM3_IBT_C32  &IBTTblEntLRC32,
3366     //    extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
3367     //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
3368     //  #endif
3369     //  #if OPTION_G34_SOCKET_SUPPORT
3370     //    extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
3371     //    #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34  &MaxFreqTblEntLRG34,
3372     //    extern PSC_TBL_ENTRY DramTermTblEntLRG34;
3373     //    #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34  &DramTermTblEntLRG34,
3374     //    extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
3375     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntLRG34,
3376     //    extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
3377     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34  &OdtPat2DTblEntLRG34,
3378     //    extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
3379     //    #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntLRG34,
3380     //    extern PSC_TBL_ENTRY SAOTblEntRG34;
3381     //    #define PSC_TBL_OR_LRDIMM3_SAO_G34  &SAOTblEntLRG34,
3382     //    extern PSC_TBL_ENTRY IBTTblEntLRG34;
3383     //    #define PSC_TBL_OR_LRDIMM3_IBT_G34  &IBTTblEntLRG34,
3384     //    extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
3385     //    #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
3386     //  #endif
3387     //#endif
3388     extern PSC_TBL_ENTRY MR0WrTblEntry;
3389     #define PSC_TBL_OR_MR0_WR  &MR0WrTblEntry,
3390     extern PSC_TBL_ENTRY MR0CLTblEntry;
3391     #define PSC_TBL_OR_MR0_CL  &MR0CLTblEntry,
3392     extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
3393     #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
3394     extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
3395     #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
3396     extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
3397     #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
3398     extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
3399     #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
3400     extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
3401     #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
3402     extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
3403     #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
3404     extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
3405     #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
3406
3407     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3408       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3409     #endif
3410     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3411       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3412     #endif
3413     #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3414       #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3415     #endif
3416     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3417       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3418     #endif
3419     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3420       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3421     #endif
3422     #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3423       #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3424     #endif
3425     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3426       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3427     #endif
3428     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3429       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3430     #endif
3431     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3432       #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3433     #endif
3434     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3435       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3436     #endif
3437     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3438       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3439     #endif
3440     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3441       #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3442     #endif
3443     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3444       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3445     #endif
3446     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3447       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3448     #endif
3449     #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3450       #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3451     #endif
3452     #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
3453       #define PSC_TBL_OR_UDIMM3_SAO_AM3
3454     #endif
3455     #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
3456       #define PSC_TBL_OR_UDIMM3_SAO_C32
3457     #endif
3458     #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
3459       #define PSC_TBL_OR_UDIMM3_SAO_G34
3460     #endif
3461     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3462       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3463     #endif
3464     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3465       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3466     #endif
3467     #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3468       #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3469     #endif
3470     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3471       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3472     #endif
3473     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3474       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3475     #endif
3476     #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3477       #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3478     #endif
3479     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3480       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3481     #endif
3482     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3483       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3484     #endif
3485     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3486       #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3487     #endif
3488     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3489       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3490     #endif
3491     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3492       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3493     #endif
3494     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3495       #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3496     #endif
3497     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3498       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3499     #endif
3500     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3501       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3502     #endif
3503     #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3504       #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3505     #endif
3506     #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
3507       #define PSC_TBL_OR_RDIMM3_SAO_AM3
3508     #endif
3509     #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
3510       #define PSC_TBL_OR_RDIMM3_SAO_C32
3511     #endif
3512     #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
3513       #define PSC_TBL_OR_RDIMM3_SAO_G34
3514     #endif
3515     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3516       #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3517     #endif
3518     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
3519       #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
3520     #endif
3521     #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
3522       #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
3523     #endif
3524     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3525       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3526     #endif
3527     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3528       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3529     #endif
3530     #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3531       #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3532     #endif
3533     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3534       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3535     #endif
3536     #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3537       #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3538     #endif
3539     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3540       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3541     #endif
3542     #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3543       #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3544     #endif
3545     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3546       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3547     #endif
3548     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3549       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3550     #endif
3551     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3552       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3553     #endif
3554     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3555       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3556     #endif
3557     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3558       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3559     #endif
3560     #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3561       #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3562     #endif
3563     #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
3564       #define PSC_TBL_OR_LRDIMM3_SAO_C32
3565     #endif
3566     #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
3567       #define PSC_TBL_OR_LRDIMM3_SAO_G34
3568     #endif
3569     #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
3570       #define PSC_TBL_OR_LRDIMM3_IBT_C32
3571     #endif
3572     #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
3573       #define PSC_TBL_OR_LRDIMM3_IBT_G34
3574     #endif
3575     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3576       #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3577     #endif
3578     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3579       #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3580     #endif
3581     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3582       #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3583     #endif
3584     #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3585       #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3586     #endif
3587     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3588       #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3589     #endif
3590     #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3591       #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3592     #endif
3593     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3594       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3595     #endif
3596     #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3597       #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3598     #endif
3599
3600     PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
3601       PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
3602       PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
3603       PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
3604       PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
3605       PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
3606       PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
3607       PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
3608       PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
3609       PSC_TBL_END
3610     };
3611
3612     PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
3613       PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
3614       PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
3615       PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
3616       PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
3617       PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
3618       PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
3619       PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
3620       PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
3621       PSC_TBL_END
3622     };
3623
3624     PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
3625       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
3626       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
3627       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
3628       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
3629       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
3630       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
3631       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
3632       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
3633       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
3634       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
3635       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
3636       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
3637       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
3638       PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
3639       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
3640       PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
3641       PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
3642       PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
3643       PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
3644       PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
3645       PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
3646       PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
3647       PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
3648       PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
3649       PSC_TBL_END
3650     };
3651
3652     PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
3653       PSC_TBL_OR_UDIMM3_SAO_AM3
3654       PSC_TBL_OR_UDIMM3_SAO_C32
3655       PSC_TBL_OR_UDIMM3_SAO_G34
3656       PSC_TBL_OR_RDIMM3_SAO_AM3
3657       PSC_TBL_OR_RDIMM3_SAO_C32
3658       PSC_TBL_OR_RDIMM3_SAO_G34
3659       PSC_TBL_OR_LRDIMM3_SAO_C32
3660       PSC_TBL_OR_LRDIMM3_SAO_G34
3661       PSC_TBL_END
3662     };
3663
3664     PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
3665       PSC_TBL_OR_MR0_WR
3666       PSC_TBL_END
3667     };
3668
3669     PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
3670       PSC_TBL_OR_MR0_CL
3671       PSC_TBL_END
3672     };
3673
3674     PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
3675       PSC_TBL_OR_RDIMM3_RC2IBT_AM3
3676       PSC_TBL_OR_RDIMM3_RC2IBT_C32
3677       PSC_TBL_OR_RDIMM3_RC2IBT_G34
3678       PSC_TBL_END
3679     };
3680
3681     PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
3682       PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
3683       PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
3684       PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
3685       PSC_TBL_END
3686     };
3687
3688     PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
3689       PSC_TBL_OR_LRDIMM3_IBT_C32
3690       PSC_TBL_OR_LRDIMM3_IBT_G34
3691       PSC_TBL_END
3692     };
3693
3694     PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
3695       PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
3696       PSC_TBL_OR_UDIMM3_CLK_DIS_C32
3697       PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
3698       PSC_TBL_OR_UDIMM3_CLK_DIS_G34
3699       PSC_TBL_OR_RDIMM3_CLK_DIS_C32
3700       PSC_TBL_OR_RDIMM3_CLK_DIS_G34
3701       PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
3702       PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
3703       PSC_TBL_OR_CKE_TRI
3704       PSC_TBL_OR_ODT_TRI_3D
3705       PSC_TBL_OR_ODT_TRI
3706       PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
3707       PSC_TBL_OR_LRDIMM3_ODT_TRI
3708       PSC_TBL_OR_UDIMM3_CS_TRI
3709       PSC_TBL_OR_CS_TRI
3710       PSC_TBL_END
3711     };
3712
3713     MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
3714       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
3715       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
3716       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
3717       (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
3718       (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
3719       (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
3720       (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
3721       (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
3722       (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
3723       NULL,
3724       NULL,
3725       (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR
3726     };
3727
3728     extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
3729     #define PSC_FLOW_OR_MAX_FREQ   MemPGetMaxFreqSupported
3730     extern MEM_PSC_FLOW MemPGetRttNomWr;
3731     #define PSC_FLOW_OR_DRAM_TERM   MemPGetRttNomWr
3732     extern MEM_PSC_FLOW MemPGetODTPattern;
3733     #define PSC_FLOW_OR_ODT_PATTERN   MemPGetODTPattern
3734     extern MEM_PSC_FLOW MemPGetSAO;
3735     #define PSC_FLOW_OR_SAO   MemPGetSAO
3736     extern MEM_PSC_FLOW MemPGetMR0WrCL;
3737     #define PSC_FLOW_OR_MR0_WRCL   MemPGetMR0WrCL
3738     #if OPTION_RDIMMS
3739       extern MEM_PSC_FLOW MemPGetRC2IBT;
3740       #define PSC_FLOW_OR_RC2_IBT    MemPGetRC2IBT
3741       extern MEM_PSC_FLOW MemPGetRC10OpSpd;
3742       #define PSC_FLOW_OR_RC10_OPSPD   MemPGetRC10OpSpd
3743     #endif
3744     //#if OPTION_LRDIMMS
3745     //extern MEM_PSC_FLOW MemPGetLRIBT;
3746     //#define PSC_FLOW_OR_LR_IBT   MemPGetLRIBT
3747     //extern MEM_PSC_FLOW MemPGetLRNPR;
3748     //#define PSC_FLOW_OR_LR_NPR   MemPGetLRNPR
3749     //extern MEM_PSC_FLOW MemPGetLRNLR;
3750     //#define PSC_FLOW_OR_LR_NLR  MemPGetLRNLR
3751     //#endif
3752     #ifndef PSC_FLOW_OR_MAX_FREQ
3753       #define PSC_FLOW_OR_MAX_FREQ   MEM_PSC_FLOW_DEFTRUE
3754     #endif
3755     #ifndef PSC_FLOW_OR_DRAM_TERM
3756       #define PSC_FLOW_OR_DRAM_TERM   MEM_PSC_FLOW_DEFTRUE
3757     #endif
3758     #ifndef PSC_FLOW_OR_ODT_PATTERN
3759       #define PSC_FLOW_OR_ODT_PATTERN   MEM_PSC_FLOW_DEFTRUE
3760     #endif
3761     #ifndef PSC_FLOW_OR_SAO
3762       #define PSC_FLOW_OR_SAO   MEM_PSC_FLOW_DEFTRUE
3763     #endif
3764     #ifndef PSC_FLOW_OR_MR0_WRCL
3765       #define PSC_FLOW_OR_MR0_WRCL   MEM_PSC_FLOW_DEFTRUE
3766     #endif
3767     #ifndef PSC_FLOW_OR_RC2_IBT
3768       #define PSC_FLOW_OR_RC2_IBT   MEM_PSC_FLOW_DEFTRUE
3769     #endif
3770     #ifndef PSC_FLOW_OR_RC10_OPSPD
3771       #define PSC_FLOW_OR_RC10_OPSPD   MEM_PSC_FLOW_DEFTRUE
3772     #endif
3773     #ifndef PSC_FLOW_OR_LR_IBT
3774       #define PSC_FLOW_OR_LR_IBT   MEM_PSC_FLOW_DEFTRUE
3775     #endif
3776     #ifndef PSC_FLOW_OR_LR_NPR
3777       #define PSC_FLOW_OR_LR_NPR   MEM_PSC_FLOW_DEFTRUE
3778     #endif
3779     #ifndef PSC_FLOW_OR_LR_NLR
3780       #define PSC_FLOW_OR_LR_NLR   MEM_PSC_FLOW_DEFTRUE
3781     #endif
3782     MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
3783       &memPSCTblBlockOr,
3784       PSC_FLOW_OR_MAX_FREQ,
3785       PSC_FLOW_OR_DRAM_TERM,
3786       PSC_FLOW_OR_ODT_PATTERN,
3787       PSC_FLOW_OR_SAO,
3788       PSC_FLOW_OR_MR0_WRCL,
3789       PSC_FLOW_OR_RC2_IBT,
3790       PSC_FLOW_OR_RC10_OPSPD,
3791       PSC_FLOW_OR_LR_IBT,
3792       PSC_FLOW_OR_LR_NPR,
3793       PSC_FLOW_OR_LR_NLR
3794     };
3795     #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
3796   #else
3797     #define MEM_PSC_FLOW_BLOCK_OR
3798   #endif
3799
3800
3801   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
3802     MEM_PSC_FLOW_BLOCK_OR
3803     MEM_PSC_FLOW_BLOCK_END
3804   };
3805
3806   /*---------------------------------------------------------------------------------------------------
3807   *
3808   *  LRDIMM CONTROL
3809   *
3810   *---------------------------------------------------------------------------------------------------
3811   */
3812   #if (OPTION_LRDIMMS == TRUE)
3813     #if (OPTION_MEMCTLR_OR == TRUE)
3814       extern MEM_TECH_FEAT MemTLrdimmConstructor3;
3815       #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
3816     #else //#if (OPTION_MEMCTLR_OR == FALSE)
3817       #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3818     #endif
3819   #else //#if (OPTION_LRDIMMS == FALSE)
3820     #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
3821   #endif
3822   MEM_TECH_LRDIMM memLrdimmSupported = {
3823     MEM_TECH_LRDIMM_STRUCT_VERSION,
3824     MEM_TECH_FEATURE_LRDIMM_INIT
3825   };
3826 #else
3827   /*---------------------------------------------------------------------------------------------------
3828    * MAIN FLOW CONTROL
3829    *
3830    *
3831    *---------------------------------------------------------------------------------------------------
3832    */
3833   MEM_FLOW_CFG* memFlowControlInstalled[] = {
3834     NULL
3835   };
3836   /*---------------------------------------------------------------------------------------------------
3837    * NB TRAINING FLOW CONTROL
3838    *
3839    *
3840    *---------------------------------------------------------------------------------------------------
3841    */
3842   OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
3843     NULL
3844   };
3845   /*---------------------------------------------------------------------------------------------------
3846    * DEFAULT TECHNOLOGY BLOCK
3847    *
3848    *
3849    *---------------------------------------------------------------------------------------------------
3850    */
3851   MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
3852     NULL
3853   };
3854
3855   /*---------------------------------------------------------------------------------------------------
3856    * DEFAULT TECHNOLOGY MAP
3857    *
3858    *
3859    *---------------------------------------------------------------------------------------------------
3860    */
3861   UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
3862
3863   /*---------------------------------------------------------------------------------------------------
3864    * DEFAULT MAIN FEATURE BLOCK
3865    *---------------------------------------------------------------------------------------------------
3866    */
3867   MEM_FEAT_BLOCK_MAIN MemFeatMain = {
3868     NULL
3869   };
3870
3871   /*---------------------------------------------------------------------------------------------------
3872    * DEFAULT NORTHBRIDGE SUPPORT LIST
3873    *
3874    *
3875    *---------------------------------------------------------------------------------------------------
3876    */
3877   #if (OPTION_MEMCTLR_DR == TRUE)
3878     #undef MEM_NB_SUPPORT_DR
3879     #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
3880   #endif
3881   #if (OPTION_MEMCTLR_RB == TRUE)
3882     #undef MEM_NB_SUPPORT_RB
3883     #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
3884   #endif
3885   #if (OPTION_MEMCTLR_DA == TRUE)
3886     #undef MEM_NB_SUPPORT_DA
3887     #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
3888   #endif
3889   #if (OPTION_MEMCTLR_PH == TRUE)
3890     #undef MEM_NB_SUPPORT_PH
3891     #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
3892   #endif
3893   #if (OPTION_MEMCTLR_HY == TRUE)
3894     #undef MEM_NB_SUPPORT_HY
3895     #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
3896   #endif
3897   #if (OPTION_MEMCTLR_C32 == TRUE)
3898     #undef MEM_NB_SUPPORT_C32
3899     #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
3900   #endif
3901   #if (OPTION_MEMCTLR_LN == TRUE)
3902     #undef MEM_NB_SUPPORT_LN
3903     #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
3904   #endif
3905   #if (OPTION_MEMCTLR_ON == TRUE)
3906     #undef MEM_NB_SUPPORT_ON
3907     #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
3908   #endif
3909   #if (OPTION_MEMCTLR_OR == TRUE)
3910     #undef MEM_NB_SUPPORT_OR
3911     #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
3912   #endif
3913   /*---------------------------------------------------------------------------------------------------
3914    * DEFAULT Technology Training
3915    *
3916    *
3917    *---------------------------------------------------------------------------------------------------
3918    */
3919   #if OPTION_DDR2
3920     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
3921       NULL
3922     };
3923     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
3924       NULL
3925     };
3926   #endif
3927   #if OPTION_DDR3
3928     MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
3929       NULL
3930     };
3931     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
3932       NULL
3933     };
3934   #endif
3935     /*---------------------------------------------------------------------------------------------------
3936      * DEFAULT Platform Specific list
3937      *
3938      *
3939      *---------------------------------------------------------------------------------------------------
3940      */
3941   #if (OPTION_MEMCTLR_DR == TRUE)
3942     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
3943       NULL
3944     };
3945   #endif
3946   #if (OPTION_MEMCTLR_RB == TRUE)
3947     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
3948       NULL
3949     };
3950   #endif
3951   #if (OPTION_MEMCTLR_DA == TRUE)
3952     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
3953       NULL
3954     };
3955   #endif
3956   #if (OPTION_MEMCTLR_Ni == TRUE)
3957     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
3958       NULL
3959     };
3960   #endif
3961   #if (OPTION_MEMCTLR_PH == TRUE)
3962     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
3963       NULL
3964     };
3965   #endif
3966   #if (OPTION_MEMCTLR_LN == TRUE)
3967     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
3968       NULL
3969     };
3970   #endif
3971   #if (OPTION_MEMCTLR_HY == TRUE)
3972     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
3973       NULL
3974     };
3975   #endif
3976   #if (OPTION_MEMCTLR_OR == TRUE)
3977     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
3978       NULL
3979     };
3980   #endif
3981   #if (OPTION_MEMCTLR_C32 == TRUE)
3982     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
3983       NULL
3984     };
3985   #endif
3986   #if (OPTION_MEMCTLR_ON == TRUE)
3987     MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
3988       NULL
3989     };
3990   #endif
3991   /*----------------------------------------------------------------------
3992    * DEFAULT PSCFG DEFINITIONS
3993    *
3994    *----------------------------------------------------------------------
3995    */
3996   MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
3997     NULL
3998   };
3999
4000   /*----------------------------------------------------------------------
4001    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
4002    *
4003    *----------------------------------------------------------------------
4004    */
4005   MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
4006     NULL
4007   };
4008
4009   MEM_TECH_LRDIMM memLrdimmSupported = {
4010     MEM_TECH_LRDIMM_STRUCT_VERSION,
4011     NULL
4012   };
4013 #endif
4014
4015 /*---------------------------------------------------------------------------------------------------
4016  * NORTHBRIDGE SUPPORT LIST
4017  *
4018  *
4019  *---------------------------------------------------------------------------------------------------
4020  */
4021 MEM_NB_SUPPORT memNBInstalled[] = {
4022   MEM_NB_SUPPORT_RB
4023   MEM_NB_SUPPORT_DA
4024   MEM_NB_SUPPORT_Ni
4025   MEM_NB_SUPPORT_PH
4026   MEM_NB_SUPPORT_HY
4027   MEM_NB_SUPPORT_LN
4028   MEM_NB_SUPPORT_OR
4029   MEM_NB_SUPPORT_C32
4030   MEM_NB_SUPPORT_ON
4031   MEM_NB_SUPPORT_END
4032 };
4033
4034 #endif  // _OPTION_MEMORY_INSTALL_H_