util/superiotool/superiotool.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SUPERIOTOOL_H
   4 #define SUPERIOTOOL_H
   5
   6 #include <stdio.h>
   7 #include <stdlib.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <getopt.h>
  11 #if defined(__GLIBC__)
  12 #include <sys/io.h>
  13 #endif
  14 #if (defined(__MACH__) && defined(__APPLE__))
  15 /* DirectHW is available here: https://www.coreboot.org/DirectHW */
  16 #include <DirectHW/DirectHW.h>
  17 #endif
  18
  19 #ifdef PCI_SUPPORT
  20 # ifdef __NetBSD__
  21 #include <pciutils/pci.h>
  22 # else
  23 #include <pci/pci.h>
  24 # endif
  25 #endif
  26
  27 #if defined(__FreeBSD__)
  28 #include <sys/types.h>
  29 #include <machine/cpufunc.h>
  30 #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
  31 #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
  32 #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
  33 #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
  34 #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
  35 #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
  36 #else
  37 #define OUTB outb
  38 #define OUTW outw
  39 #define OUTL outl
  40 #define INB  inb
  41 #define INW  inw
  42 #define INL  inl
  43 #endif
  44
  45 #if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__))
  46 #include <sys/types.h>
  47 #include <machine/sysarch.h>
  48 #if defined(__i386__)
  49 #define iopl i386_iopl
  50 #elif defined(__x86_64__)
  51 #define iopl x86_64_iopl
  52 #endif
  53
  54 static __inline__ void
  55 outb(uint8_t value, uint16_t port)
  56 {
  57         __asm__ __volatile__ ("outb %b0,%w1": :"a" (value), "Nd" (port));
  58 }
  59
  60 static __inline__ void
  61 outw(uint16_t value, uint16_t port)
  62 {
  63         __asm__ __volatile__ ("outw %w0,%w1": :"a" (value), "Nd" (port));
  64 }
  65
  66 static __inline__ void
  67 outl(uint32_t value, uint16_t port)
  68 {
  69         __asm__ __volatile__ ("outl %0,%w1": :"a" (value), "Nd" (port));
  70 }
  71
  72 static __inline__ uint8_t inb(uint16_t port)
  73 {
  74         uint8_t value;
  75         __asm__ __volatile__ ("inb %w1,%0":"=a" (value):"Nd" (port));
  76         return value;
  77 }
  78
  79 static __inline__ uint16_t inw(uint16_t port)
  80 {
  81         uint16_t value;
  82         __asm__ __volatile__ ("inw %w1,%0":"=a" (value):"Nd" (port));
  83         return value;
  84 }
  85
  86 static __inline__ uint32_t inl(uint16_t port)
  87 {
  88         uint32_t value;
  89         __asm__ __volatile__ ("inl %1,%0":"=a" (value):"Nd" (port));
  90         return value;
  91 }
  92 #endif
  93
  94 #define USAGE "Usage: superiotool [-d] [-e] [-a] [-l] [-V] [-v] [-h]\n\n\
  95   -d | --dump            Dump Super I/O register contents\n\
  96   -e | --extra-dump      Dump secondary registers too (e.g. EC registers)\n\
  97   -a | --alternate-dump  Use alternative dump format, more suitable for diff\n\
  98   -l | --list-supported  Show the list of supported Super I/O chips\n\
  99   -V | --verbose         Verbose mode\n\
 100   -v | --version         Show the superiotool version\n\
 101   -h | --help            Show a short help text\n\n"
 102
 103 #define USAGE_INFO "\
 104 Per default (no options) superiotool will just probe for a Super I/O\n\
 105 and print its vendor, name, ID, revision, and config port.\n"
 106
 107 #define NOTFOUND "  Failed. Returned data: "
 108
 109 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 110
 111 #define EOT             -1              /* End Of Table */
 112 #define NOLDN           -2              /* NO LDN needed */
 113 #define NANA            -3              /* Not Available:
 114                                            Used for registers having externally controlled
 115                                            values that can change during runtime like
 116                                            GPIO input value registers. */
 117 #define RSVD            -4              /* Reserved */
 118 #define MISC            -5              /* Needs special comment in output:
 119                                            Used for registers depending on external pin straps
 120                                            configuring static, but board-specific settings like
 121                                            SIO base address or AMD/Intel power seqencing type. */
 122 #define MAXLDN          0x14            /* Biggest LDN */
 123 #define LDNSIZE         (MAXLDN + 3)    /* Biggest LDN + 0 + NOLDN + EOT */
 124 #define MAXNUMIDX       170             /* Maximum number of indices */
 125 #define IDXSIZE         (MAXNUMIDX + 1)
 126 #define MAXNUMPORTS     (6 + 1)         /* Maximum number of Super I/O ports */
 127
 128 /* Select registers for various components. */
 129 #define LDN_SEL         0x07            /* LDN select register */
 130 #define WINBOND_HWM_SEL 0x4e            /* Hardware monitor bank select */
 131
 132 /* Command line parameters. */
 133 extern int dump, verbose, extra_dump;
 134
 135 extern int chip_found;
 136
 137 struct superio_registers {
 138         int32_t superio_id;             /* Signed, as we need EOT. */
 139         const char *name;               /* Super I/O name */
 140         struct {
 141                 int8_t ldn;
 142                 const char *name;       /* LDN name */
 143                 int16_t idx[IDXSIZE];
 144                 int16_t def[IDXSIZE];
 145         } ldn[LDNSIZE];
 146 };
 147
 148 /* pci.c */
 149 #ifdef PCI_SUPPORT
 150 extern struct pci_access *pacc;
 151 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
 152 #endif
 153
 154 /* superiotool.c */
 155 uint8_t regval(uint16_t port, uint8_t reg);
 156 void regwrite(uint16_t port, uint8_t reg, uint8_t val);
 157 void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port);
 158 void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port);
 159 void enter_conf_mode_fintek_7777(uint16_t port);
 160 void exit_conf_mode_fintek_7777(uint16_t port);
 161 int superio_unknown(const struct superio_registers reg_table[], uint16_t id);
 162 const char *get_superio_name(const struct superio_registers reg_table[],
 163                              uint16_t id);
 164 void dump_superio(const char *name, const struct superio_registers reg_table[],
 165                   uint16_t port, uint16_t id, uint8_t ldn_sel);
 166 void dump_io(uint16_t iobase, uint16_t length);
 167 void dump_data(uint16_t iobase, int bank);
 168 void probing_for(const char *vendor, const char *info, uint16_t port);
 169 void print_vendor_chips(const char *vendor,
 170                         const struct superio_registers reg_table[]);
 171
 172 /* ali.c */
 173 void probe_idregs_ali(uint16_t port);
 174 void print_ali_chips(void);
 175
 176 /* aspeed.c */
 177 void probe_idregs_aspeed(uint16_t port);
 178 void print_aspeed_chips(void);
 179
 180 /* amd.c */
 181 void probe_idregs_amd(uint16_t port);
 182 void print_amd_chips(void);
 183
 184 /* serverengines.c */
 185 void probe_idregs_serverengines(uint16_t port);
 186 void print_serverengines_chips(void);
 187
 188 /* exar.c */
 189 void probe_idregs_exar(uint16_t port);
 190 void print_exar_chips(void);
 191
 192 /* fintek.c */
 193 void probe_idregs_fintek(uint16_t port);
 194 void probe_idregs_fintek_alternative(uint16_t port);
 195 void print_fintek_chips(void);
 196
 197 /* infineon.c */
 198 void probe_idregs_infineon(uint16_t port);
 199 void print_infineon_chips(void);
 200
 201 /* ite.c */
 202 void probe_idregs_ite(uint16_t port);
 203 void print_ite_chips(void);
 204
 205 /* nsc.c */
 206 void probe_idregs_nsc(uint16_t port);
 207 void print_nsc_chips(void);
 208
 209 /* nuvoton.c */
 210 void probe_idregs_nuvoton(uint16_t port);
 211 void print_nuvoton_chips(void);
 212
 213 /* smsc.c */
 214 void probe_idregs_smsc(uint16_t port);
 215 void print_smsc_chips(void);
 216
 217 /* winbond.c */
 218 void probe_idregs_winbond(uint16_t port);
 219 void print_winbond_chips(void);
 220
 221 /* via.c */
 222 #ifdef PCI_SUPPORT
 223 void probe_idregs_via(uint16_t port);
 224 void print_via_chips(void);
 225 #endif
 226
 227 /** Table of which config ports to probe for each Super I/O family. */
 228 static const struct {
 229         void (*probe_idregs) (uint16_t port);
 230         int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */
 231 } superio_ports_table[] = {
 232         {probe_idregs_ali,      {0x3f0, 0x370, EOT}},
 233         {probe_idregs_aspeed,   {0x2e, 0x4e, EOT}},
 234         {probe_idregs_exar,     {0x2e, 0x4e, EOT}},
 235         {probe_idregs_fintek,   {0x2e, 0x4e, EOT}},
 236         {probe_idregs_fintek_alternative,       {0x2e, 0x4e, EOT}},
 237         /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
 238         {probe_idregs_ite,      {0x20e, 0x25e, 0x2e, 0x4e, 0x370, 0x6e, EOT}},
 239         {probe_idregs_nsc,      {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
 240         /* I/O pairs on Nuvoton EC chips can be configured by firmware in
 241          * addition to the following hardware strapping options. */
 242         {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
 243         {probe_idregs_smsc,     {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
 244         {probe_idregs_winbond,  {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
 245 #ifdef PCI_SUPPORT
 246         {probe_idregs_via,      {0x2e, 0x4e, 0x3f0, EOT}},
 247         /* in fact read the BASE from HW */
 248         {probe_idregs_amd,      {0xaa, EOT}},
 249 #endif
 250         {probe_idregs_serverengines,    {0x2e, EOT}},
 251         {probe_idregs_infineon, {0x2e, 0x4e, EOT}},
 252 };
 253
 254 /** Table of functions to print out supported Super I/O chips. */
 255 static const struct {
 256         void (*print_list) (void);
 257 } vendor_print_functions[] = {
 258         {print_ali_chips},
 259         {print_exar_chips},
 260         {print_fintek_chips},
 261         {print_ite_chips},
 262         {print_nsc_chips},
 263         {print_nuvoton_chips},
 264         {print_smsc_chips},
 265         {print_winbond_chips},
 266 #ifdef PCI_SUPPORT
 267         {print_via_chips},
 268         {print_amd_chips},
 269         {print_aspeed_chips},
 270 #endif
 271         {print_serverengines_chips},
 272         {print_infineon_chips},
 273 };
 274
 275 #endif