src/soc/intel/common/block/include/intelblocks/cse.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SOC_INTEL_COMMON_CSE_H
   4 #define SOC_INTEL_COMMON_CSE_H
   5
   6 #include <types.h>
   7 #include <vb2_api.h>
   8
   9 /* MKHI Command groups */
  10 #define MKHI_GROUP_ID_CBM       0x0
  11 #define MKHI_GROUP_ID_HMRFPO    0x5
  12 #define MKHI_GROUP_ID_GEN       0xff
  13 #define MKHI_GROUP_ID_BUP_COMMON        0xf0
  14 #define MKHI_GROUP_ID_FWCAPS    0x3
  15
  16 /* Global Reset Command ID */
  17 #define MKHI_CBM_GLOBAL_RESET_REQ       0xb
  18
  19 /* Set State Command ID */
  20 #define MKHI_SET_ME_DISABLE     0x3
  21 #define MKHI_SET_ME_ENABLE      0x3
  22
  23 /* Origin of Global Reset command */
  24 #define GR_ORIGIN_BIOS_POST     0x2
  25
  26 /* HMRFPO Command Ids */
  27 #define MKHI_HMRFPO_ENABLE      0x1
  28 #define MKHI_HMRFPO_GET_STATUS  0x3
  29
  30 /* Get Firmware Version Command Id */
  31 #define MKHI_GEN_GET_FW_VERSION 0x2
  32
  33 /* MEI bus disable command. Must be sent to MEI client endpoint, not MKHI */
  34 #define MEI_BUS_DISABLE_COMMAND 0xc
  35
  36 /* Set End-of-POST in CSE */
  37 #define MKHI_END_OF_POST        0xc
  38
  39 /* Boot partition info and set boot partition info command ids */
  40 #define MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO 0x1c
  41 #define MKHI_BUP_COMMON_SET_BOOT_PARTITION_INFO 0x1d
  42 #define MKHI_BUP_COMMON_DATA_CLEAR              0x20
  43
  44 /* Get boot performance command id */
  45 #define MKHI_BUP_COMMON_GET_BOOT_PERF_DATA      0x8
  46
  47 /* ME Current Working States */
  48 #define ME_HFS1_CWS_NORMAL      0x5
  49
  50 /* ME Current Operation Modes */
  51 #define ME_HFS1_COM_NORMAL      0x0
  52 #define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
  53 #define ME_HFS1_COM_SECOVER_MEI_MSG     0x5
  54
  55 /* ME Disable Rule */
  56 #define ME_DISABLE_RULE_ID      6
  57 #define ME_DISABLE_RULE_LENGTH  4
  58 #define ME_DISABLE_COMMAND      0
  59 #define ME_DISABLE_ATTEMPTS     3
  60
  61 /* ME Firmware SKU Types */
  62 #define ME_HFS3_FW_SKU_CONSUMER 0x2
  63 #define ME_HFS3_FW_SKU_CORPORATE        0x3
  64 #define ME_HFS3_FW_SKU_LITE     0x5
  65
  66 /* Number of cse boot performance data */
  67 #define NUM_CSE_BOOT_PERF_DATA  64
  68
  69 /* HFSTS register offsets in PCI config space */
  70 enum {
  71         PCI_ME_HFSTS1 = 0x40,
  72         PCI_ME_HFSTS2 = 0x48,
  73         PCI_ME_HFSTS3 = 0x60,
  74         PCI_ME_HFSTS4 = 0x64,
  75         PCI_ME_HFSTS5 = 0x68,
  76         PCI_ME_HFSTS6 = 0x6C,
  77 };
  78
  79 /* MKHI Message Header */
  80 struct mkhi_hdr {
  81         uint8_t group_id;
  82         uint8_t command:7;
  83         uint8_t is_resp:1;
  84         uint8_t rsvd;
  85         uint8_t result;
  86 } __packed;
  87
  88 /* CSE FW Version */
  89 struct fw_version {
  90         uint16_t major;
  91         uint16_t minor;
  92         uint16_t hotfix;
  93         uint16_t build;
  94 } __packed;
  95
  96 /* ME FW Version */
  97 struct me_version {
  98         uint16_t minor;
  99         uint16_t major;
 100         uint16_t build;
 101         uint16_t hotfix;
 102 } __packed;
 103
 104 /* ME FW Version response */
 105 struct me_fw_ver_resp {
 106         struct mkhi_hdr hdr;
 107         struct me_version code;
 108         struct me_version rec;
 109         struct me_version fitc;
 110 } __packed;
 111
 112 /* CSE recovery sub-error codes */
 113 enum csme_failure_reason {
 114         /* No error */
 115         CSE_NO_ERROR = 0,
 116
 117         /* Unspecified error */
 118         CSE_ERROR_UNSPECIFIED = 1,
 119
 120         /* CSE fails to boot from RW */
 121         CSE_LITE_SKU_RW_JUMP_ERROR = 2,
 122
 123         /* CSE RW boot partition access error */
 124         CSE_LITE_SKU_RW_ACCESS_ERROR = 3,
 125
 126         /* Fails to set next boot partition as RW */
 127         CSE_LITE_SKU_RW_SWITCH_ERROR = 4,
 128
 129         /* CSE firmware update failure */
 130         CSE_LITE_SKU_FW_UPDATE_ERROR = 5,
 131
 132         /* Fails to communicate with CSE */
 133         CSE_COMMUNICATION_ERROR = 6,
 134
 135         /* Fails to wipe CSE runtime data */
 136         CSE_LITE_SKU_DATA_WIPE_ERROR = 7,
 137
 138         /* CSE RW is not found */
 139         CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8,
 140
 141         /* CSE CBFS RW SHA-256 mismatch with the provided SHA */
 142         CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9,
 143
 144         /* CSE CBFS RW metadata is not found */
 145         CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10,
 146
 147         /* CSE CBFS RW blob layout is not correct */
 148         CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11,
 149
 150         /* Error sending EOP to CSE */
 151         CSE_EOP_FAIL = 12,
 152
 153         /* CSE Sub-partition update fail */
 154         CSE_LITE_SKU_SUB_PART_UPDATE_FAIL = 13,
 155
 156         /* CSE sub-partition access failure */
 157         CSE_LITE_SKU_SUB_PART_ACCESS_ERR = 14,
 158
 159         /* CSE CBFS sub-partition access error */
 160         CSE_LITE_SKU_SUB_PART_BLOB_ACCESS_ERR = 15,
 161
 162         /* CSE Lite sub-partition update is not required */
 163         CSE_LITE_SKU_SUB_PART_UPDATE_NOT_REQ = 16,
 164
 165         /* CSE Lite sub-partition layout mismatch error */
 166         CSE_LITE_SKU_SUB_PART_LAYOUT_MISMATCH_ERROR = 17,
 167
 168         /* CSE Lite sub-partition update success */
 169         CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18,
 170 };
 171
 172 /* Boot performance data */
 173 enum cse_boot_perf_data {
 174         /* CSME ROM start execution  */
 175         PERF_DATA_CSME_ROM_START = 0,
 176
 177         /* EC Boot Load Done (CSME ROM starts main execution) */
 178         PERF_DATA_EC_BOOT_LOAD_DONE = 1,
 179
 180         /* CSME ROM completed execution / CSME RBE started */
 181         PERF_DATA_CSME_ROM_COMPLETED = 2,
 182
 183         /* CSME got ESE Init Done indication from ESE */
 184         PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3,
 185
 186         /* CSME RBE start PMC patch/es loading */
 187         PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4,
 188
 189         /* CSME RBE completed PMC patch/es loading */
 190         PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5,
 191
 192         /* CSME RBE set "Boot Stall Done" indication to PMC */
 193         PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6,
 194
 195         /* CSME start poll for PMC PPS register */
 196         PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7,
 197
 198         /* PMC set PPS */
 199         PERF_DATA_PMC_SET_PPS = 8,
 200
 201         /* CSME BUP start running  */
 202         PERF_DATA_CSME_BUP_START = 9,
 203
 204         /* CSME set "Host Boot Prep Done" indication to PMC  */
 205         PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10,
 206
 207         /* CSME starts PHYs loading */
 208         PERF_DATA_CSME_PHY_LOADING_START = 11,
 209
 210         /* CSME completed PHYs loading */
 211         PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12,
 212
 213         /* PMC indicated CSME that xxPWRGOOD was asserted */
 214         PERF_DATA_PMC_PWRGOOD_ASSERTED = 13,
 215
 216         /* PMC indicated CSME that SYS_PWROK was asserted */
 217         PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14,
 218
 219         /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */
 220         PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15,
 221
 222         /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */
 223         PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW = 16,
 224
 225         /* PMC indicated CSME that xxPLTRST was de-asserted */
 226         PERF_DATA_PMC_PLTRST_DEASSERTED = 17,
 227
 228         /* PMC indicated CSME that TCO_S0 was asserted */
 229         PERF_DATA_PMC_TC0_S0_ASSERTED = 18,
 230
 231         /* PMC sent "Core Reset Done Ack - Sent" message to CSME */
 232         PERF_DATA_PMC_SENT_CRDA = 19,
 233
 234         /* ACM Active indication - ACM started its execution */
 235         PERF_DATA_ACM_START = 20,
 236
 237         /* ACM Done indication - ACM completed execution */
 238         PERF_DATA_ACM_DONE = 21,
 239
 240         /* BIOS sent DRAM Init Done message */
 241         PERF_DATA_BIOS_DRAM_INIT_DONE = 22,
 242
 243         /* CSME sent DRAM Init Done message back to BIOS */
 244         PERF_DATA_CSME_DRAM_INIT_DONE = 23,
 245
 246         /* CSME completed loading TCSS */
 247         PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24,
 248
 249         /* CSME started loading ISH Bringup module */
 250         PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25,
 251
 252         /* CSME completed loading ISH Bringup module */
 253         PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26,
 254
 255         /* CSME started loading ISH Main module */
 256         PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27,
 257
 258         /* CSME completed loading Main module */
 259         PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28,
 260
 261         /* BIOS sent "End Of Post" message to CSME */
 262         PERF_DATA_BIOS_END_OF_POST = 29,
 263
 264         /* CSME sent "End Of Post" ack message back to BIOS */
 265         PERF_DATA_CSME_END_OF_POST = 30,
 266
 267         /* BIOS sent "Core BIOS Done" message to CSME */
 268         PERF_DATA_BIOS_BIOS_CORE_DONE = 31,
 269
 270         /* CSME sent "Core BIOS Done" ack message back to BIOS */
 271         PERF_DATA_CSME_BIOS_CORE_DONE = 32,
 272
 273         /* CSME reached Firmware Init Done */
 274         PERF_DATA_CSME_GW_INIT_DONE = 33,
 275
 276         /* 34 - 62 Reserved */
 277
 278         /* Timestamp when CSME responded to BupGetBootData message itself */
 279         PERF_DATA_CSME_GET_PERF_RESPONSE = 63,
 280 };
 281
 282 /* CSE boot performance data */
 283 struct cse_boot_perf_rsp {
 284         struct mkhi_hdr hdr;
 285
 286         /* Data version */
 287         uint32_t version;
 288
 289         /* Data length in DWORDs, represents number of valid elements in timestamp array */
 290         uint32_t num_valid_timestamps;
 291
 292         /* Boot performance data */
 293         uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA];
 294 } __packed;
 295
 296 /* set up device for use in early boot enviroument with temp bar */
 297 void heci_init(uintptr_t bar);
 298
 299 /*
 300  * Send message from BIOS_HOST_ADDR to cse_addr.
 301  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
 302  * rcv_msg of size rcv_sz
 303  * Returns 0 on failure and 1 on success.
 304  */
 305 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz,
 306                                                                         uint8_t cse_addr);
 307
 308 /*
 309  * Attempt device reset. This is useful and perhaps only thing left to do when
 310  * CPU and CSE are out of sync or CSE fails to respond.
 311  * Returns 0 on failure and 1 on success.
 312  */
 313 int heci_reset(void);
 314 /* Disable HECI1 using Sideband interface communication */
 315 void heci1_disable(void);
 316
 317 /* Reads config value from a specified offset in the CSE PCI Config space. */
 318 uint32_t me_read_config32(int offset);
 319
 320 /*
 321  * Check if the CSE device as per function argument `devfn` is enabled in device tree
 322  * and also visible on the PCI bus.
 323  */
 324 bool is_cse_devfn_visible(unsigned int devfn);
 325
 326 /*
 327  * Check if the CSE device is enabled in device tree. Also check if the device
 328  * is visible on the PCI bus by reading config space.
 329  * Return true if device present and config space enabled, else return false.
 330  */
 331 bool is_cse_enabled(void);
 332
 333 /* Makes the host ready to communicate with CSE */
 334 void cse_set_host_ready(void);
 335
 336 /*
 337  * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
 338  * Returns 0 on failure and 1 on success.
 339  */
 340 uint8_t cse_wait_sec_override_mode(void);
 341
 342 enum rst_req_type {
 343         GLOBAL_RESET = 1,
 344         CSE_RESET_ONLY = 3,
 345 };
 346
 347 /*
 348  * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET.
 349  * Returns 0 on failure and 1 on success.
 350  */
 351 int cse_request_global_reset(void);
 352 /*
 353  * Sends HMRFPO_ENABLE command.
 354  * HMRFPO - Host ME Region Flash Protection Override.
 355  * For CSE Lite SKU, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode:
 356  *      1. Ensure CSE boots from RO(BP1).
 357  *              - Set CSE's next boot partition to RO
 358  *              - Issue GLOBAL_RESET command to reset the system
 359  *      2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.
 360  *
 361  * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks
 362  * the CSE region to perform updates to it.
 363  * This command is only valid before EOP.
 364  *
 365  * Returns 0 on failure to send HECI command and to enable HMRFPO mode, and 1 on success.
 366  *
 367  */
 368 int cse_hmrfpo_enable(void);
 369
 370 /*
 371  * Send HMRFPO_GET_STATUS command.
 372  * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED)
 373  * on success.
 374  */
 375 int cse_hmrfpo_get_status(void);
 376
 377 /* Fixed Address MEI Header's Host Address field value */
 378 #define BIOS_HOST_ADDR  0x00
 379
 380 /* Fixed Address MEI Header's ME Address field value */
 381 #define HECI_MKHI_ADDR  0x07
 382
 383 /* Fixed Address MEI Header's ME Address for MEI bus messages */
 384 #define HECI_MEI_ADDR   0x00
 385
 386 /* HMRFPO Status types */
 387 /* Host can't access ME region */
 388 #define MKHI_HMRFPO_DISABLED    0
 389
 390 /*
 391  * ME Firmware locked down HMRFPO Feature.
 392  * Host can't access ME region.
 393  */
 394 #define MKHI_HMRFPO_LOCKED      1
 395
 396 /* Host can access ME region */
 397 #define MKHI_HMRFPO_ENABLED     2
 398
 399 /*
 400  * Queries and logs ME firmware version
 401  */
 402 void print_me_fw_version(void *unused);
 403
 404 /*
 405  * Queries and gets ME firmware version
 406  */
 407 enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp);
 408
 409 /*
 410  * Checks current working operation state is normal or not.
 411  * Returns true if CSE's current working state is normal, otherwise false.
 412  */
 413 bool cse_is_hfs1_cws_normal(void);
 414
 415 /*
 416  * Checks CSE's current operation mode is normal or not.
 417  * Returns true if CSE's current operation mode is normal, otherwise false.
 418  */
 419 bool cse_is_hfs1_com_normal(void);
 420
 421 /*
 422  * Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
 423  * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
 424  */
 425 bool cse_is_hfs1_com_secover_mei_msg(void);
 426
 427 /*
 428  * Checks CSE's current operation mode is Soft Disable Mode or not.
 429  * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
 430  */
 431 bool cse_is_hfs1_com_soft_temp_disable(void);
 432
 433 /*
 434  * Checks CSE's spi protection mode is protected or unprotected.
 435  * Returns true if CSE's spi protection mode is protected, otherwise false.
 436  */
 437 bool cse_is_hfs1_spi_protected(void);
 438
 439 /*
 440  * Checks CSE's Firmware SKU is Lite or not.
 441  * Returns true if CSE's Firmware SKU is Lite, otherwise false
 442  */
 443 bool cse_is_hfs3_fw_sku_lite(void);
 444
 445 /*
 446  * Polls for CSE's current operation mode 'Soft Temp Disable'.
 447  * Returns 0 on failure and 1 on success.
 448  */
 449 uint8_t cse_wait_com_soft_temp_disable(void);
 450
 451 /*
 452  * The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
 453  * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
 454  * boot from RW and triggers recovery mode if CSE fails to jump to RW.
 455  * In software triggered recovery mode, the function allows CSE to boot from whatever is
 456  * currently selected partition.
 457  */
 458 void cse_fw_sync(void);
 459
 460 /* Perform a board-specific reset sequence for CSE RO<->RW jump */
 461 void cse_board_reset(void);
 462
 463 /* Trigger vboot recovery mode on a CSE error */
 464 void cse_trigger_vboot_recovery(enum csme_failure_reason reason);
 465
 466 enum cse_device_state {
 467         DEV_IDLE,
 468         DEV_ACTIVE,
 469 };
 470
 471 /* Function to get the current CSE device state as per `cse_device_state` */
 472 enum cse_device_state get_cse_device_state(unsigned int devfn);
 473
 474 /* Function that put the CSE into desired state based on `requested_state` */
 475 bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state);
 476
 477 /*
 478  * Check if cse sub-parition update is required or not.
 479  * Returns true if cse sub-parition update is required otherwise false.
 480  */
 481 bool skip_cse_sub_part_update(void);
 482
 483 /*
 484  * This command retrieves a set of boot performance timestamps CSME collected during
 485  * the last platform boot flow.
 486  */
 487 bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf);
 488
 489 /* Function to make cse disable using PMC IPC */
 490 bool cse_disable_mei_devices(void);
 491
 492 /* Set CSE device state to D0I3 */
 493 void cse_set_to_d0i3(void);
 494
 495 /* Function sets D0I3 for all HECI devices */
 496 void heci_set_to_d0i3(void);
 497
 498 /* Function performs the global reset lock */
 499 void cse_control_global_reset_lock(void);
 500
 501 /*
 502  * SoC override API to make heci1 disable using PCR.
 503  *
 504  * Allow SoC to implement heci1 disable override due to PSF registers being
 505  * different across SoC generation.
 506  */
 507 void soc_disable_heci1_using_pcr(void);
 508
 509 #endif // SOC_INTEL_COMMON_CSE_H