src/soc/rockchip/rk3288/vop.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc.
  18  */
  19
  20 #include <arch/io.h>
  21 #include <console/console.h>
  22 #include <delay.h>
  23 #include <stdlib.h>
  24 #include <string.h>
  25 #include <stddef.h>
  26 #include <soc/addressmap.h>
  27 #include <soc/clock.h>
  28 #include <soc/edp.h>
  29 #include <soc/vop.h>
  30
  31 #include "chip.h"
  32
  33 static struct rk3288_vop_regs * const vop_regs[] = {
  34         (struct rk3288_vop_regs *)VOP_BIG_BASE,
  35         (struct rk3288_vop_regs *)VOP_LIT_BASE
  36 };
  37
  38 void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
  39 {
  40         u32 lb_mode;
  41         u32 rgb_mode;
  42         u32 hactive = edid->mode.ha;
  43         u32 vactive = edid->mode.va;
  44         u32 hsync_len = edid->mode.hspw;
  45         u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
  46         u32 vsync_len = edid->mode.vspw;
  47         u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
  48         u32 xpos = 0, ypos = 0;
  49         struct rk3288_vop_regs *preg = vop_regs[vop_id];
  50
  51         write32(&preg->win0_act_info,
  52                 V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
  53
  54         write32(&preg->win0_dsp_st, V_DSP_XST(xpos + hsync_len + hback_porch) |
  55                                     V_DSP_YST(ypos + vsync_len + vback_porch));
  56
  57         write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) |
  58                                       V_DSP_HEIGHT(vactive - 1));
  59
  60         clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
  61                                                 V_WIN0_KEY_EN(0) |
  62                                                 V_WIN0_KEY_COLOR(0));
  63
  64         switch (edid->framebuffer_bits_per_pixel) {
  65         case 16:
  66                 rgb_mode = RGB565;
  67                 write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive));
  68                 break;
  69         case 24:
  70                 rgb_mode = RGB888;
  71                 write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive));
  72                 break;
  73         case 32:
  74         default:
  75                 rgb_mode = ARGB8888;
  76                 write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive));
  77                 break;
  78         }
  79
  80         if (hactive > 2560)
  81                 lb_mode = LB_RGB_3840X2;
  82         else if (hactive > 1920)
  83                 lb_mode = LB_RGB_2560X4;
  84         else if (hactive > 1280)
  85                 lb_mode = LB_RGB_1920X5;
  86         else
  87                 lb_mode = LB_RGB_1280X8;
  88
  89         clrsetbits_le32(&preg->win0_ctrl0,
  90                         M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
  91                         V_WIN0_LB_MODE(lb_mode) |
  92                         V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
  93
  94         write32(&preg->win0_yrgb_mst, fbbase);
  95
  96         write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
  97 }
  98
  99 void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
 100 {
 101         u32 hactive = edid->mode.ha;
 102         u32 vactive = edid->mode.va;
 103         u32 hfront_porch = edid->mode.hso;
 104         u32 hsync_len = edid->mode.hspw;
 105         u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
 106         u32 vfront_porch = edid->mode.vso;
 107         u32 vsync_len = edid->mode.vspw;
 108         u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
 109         struct rk3288_vop_regs *preg = vop_regs[vop_id];
 110
 111         switch (mode) {
 112
 113         case VOP_MODE_HDMI:
 114                 clrsetbits_le32(&preg->sys_ctrl,
 115                                 M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
 116                 break;
 117
 118         case VOP_MODE_EDP:
 119         default:
 120                 clrsetbits_le32(&preg->sys_ctrl,
 121                                 M_ALL_OUT_EN, V_EDP_OUT_EN(1));
 122                 break;
 123         }
 124
 125         clrsetbits_le32(&preg->dsp_ctrl0,
 126                         M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
 127                         V_DSP_OUT_MODE(15) |
 128                         V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
 129                         V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
 130
 131         write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
 132                 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
 133
 134         write32(&preg->dsp_hact_st_end,
 135                 V_HEAP(hsync_len + hback_porch + hactive) |
 136                 V_HASP(hsync_len + hback_porch));
 137
 138         write32(&preg->dsp_vtotal_vs_end, V_VSYNC(vsync_len) |
 139                 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch));
 140
 141         write32(&preg->dsp_vact_st_end,
 142                 V_VAEP(vsync_len + vback_porch + vactive) |
 143                 V_VASP(vsync_len + vback_porch));
 144
 145         write32(&preg->post_dsp_hact_info,
 146                 V_HEAP(hsync_len + hback_porch + hactive) |
 147                 V_HASP(hsync_len + hback_porch));
 148
 149         write32(&preg->post_dsp_vact_info,
 150                 V_VAEP(vsync_len + vback_porch + vactive) |
 151                 V_VASP(vsync_len + vback_porch));
 152
 153         write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
 154 }