2 * drivers/video/tegra/dc/dp.c
4 * Copyright (c) 2011-2015, NVIDIA Corporation.
5 * Copyright 2014 Google Inc.
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <console/console.h>
19 #include <device/device.h>
20 #include <device/i2c.h>
25 #include <soc/addressmap.h>
26 #include <soc/clock.h>
27 #include <soc/display.h>
28 #include <soc/nvidia/tegra/i2c.h>
29 #include <soc/nvidia/tegra/dc.h>
30 #include <soc/nvidia/tegra/types.h>
31 #include <soc/nvidia/tegra/pwm.h>
32 #include <soc/nvidia/tegra/displayport.h>
36 #define DO_FAST_LINK_TRAINING 0
38 struct tegra_dc dc_data
;
45 struct tegra_dc_dp_data dp_data
;
47 static inline u32
tegra_dpaux_readl(struct tegra_dc_dp_data
*dp
, u32 reg
)
49 void *addr
= dp
->aux_base
+ (u32
) (reg
<< 2);
50 u32 reg_val
= READL(addr
);
54 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data
*dp
,
57 void *addr
= dp
->aux_base
+ (u32
) (reg
<< 2);
61 static inline u32
tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data
*dp
,
62 u32 reg
, u32 mask
, u32 exp_val
,
67 u32 temp
= timeout_us
;
70 udelay(poll_interval_us
);
71 reg_val
= tegra_dpaux_readl(dp
, reg
);
72 if (timeout_us
> poll_interval_us
)
73 timeout_us
-= poll_interval_us
;
76 } while ((reg_val
& mask
) != exp_val
);
78 if ((reg_val
& mask
) == exp_val
)
79 return 0; /* success */
81 "dpaux_poll_register 0x%x: timeout: "
82 "(reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
83 reg
, reg_val
, mask
, exp_val
);
87 static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data
*dp
)
89 /* According to DP spec, each aux transaction needs to finish
91 if (tegra_dc_dpaux_poll_register(dp
, DPAUX_DP_AUXCTL
,
92 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK
,
93 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE
,
94 100, DP_AUX_TIMEOUT_MS
* 1000) != 0) {
95 printk(BIOS_INFO
, "dp: DPAUX transaction timeout\n");
101 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data
*dp
, u32 cmd
,
102 u32 addr
, u8
*data
, u32
*size
,
107 u32 timeout_retries
= DP_AUX_TIMEOUT_MAX_TRIES
;
108 u32 defer_retries
= DP_AUX_DEFER_MAX_TRIES
;
111 if (*size
> DP_AUX_MAX_BYTES
)
112 return -1; /* only write one chunk of data */
114 /* Make sure the command is write command */
116 case DPAUX_DP_AUXCTL_CMD_I2CWR
:
117 case DPAUX_DP_AUXCTL_CMD_MOTWR
:
118 case DPAUX_DP_AUXCTL_CMD_AUXWR
:
121 printk(BIOS_ERR
, "dp: aux write cmd 0x%x is invalid\n", cmd
);
125 tegra_dpaux_writel(dp
, DPAUX_DP_AUXADDR
, addr
);
126 for (i
= 0; i
< DP_AUX_MAX_BYTES
/ 4; ++i
) {
127 memcpy(&temp_data
, data
, 4);
128 tegra_dpaux_writel(dp
, DPAUX_DP_AUXDATA_WRITE_W(i
), temp_data
);
132 reg_val
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXCTL
);
133 reg_val
&= ~DPAUX_DP_AUXCTL_CMD_MASK
;
135 reg_val
&= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD
;
136 reg_val
|= ((*size
- 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT
);
138 while ((timeout_retries
> 0) && (defer_retries
> 0)) {
139 if ((timeout_retries
!= DP_AUX_TIMEOUT_MAX_TRIES
) ||
140 (defer_retries
!= DP_AUX_DEFER_MAX_TRIES
))
143 reg_val
|= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING
;
144 tegra_dpaux_writel(dp
, DPAUX_DP_AUXCTL
, reg_val
);
146 if (tegra_dpaux_wait_transaction(dp
))
147 printk(BIOS_ERR
, "dp: aux write transaction timeout\n");
149 *aux_stat
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXSTAT
);
151 if ((*aux_stat
& DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING
) ||
152 (*aux_stat
& DPAUX_DP_AUXSTAT_RX_ERROR_PENDING
) ||
153 (*aux_stat
& DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING
) ||
154 (*aux_stat
& DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING
)) {
155 if (timeout_retries
-- > 0) {
156 printk(BIOS_INFO
, "dp: aux write retry (0x%x)"
158 *aux_stat
, timeout_retries
);
159 /* clear the error bits */
160 tegra_dpaux_writel(dp
, DPAUX_DP_AUXSTAT
,
164 printk(BIOS_ERR
, "dp: aux write got error"
165 " (0x%x)\n", *aux_stat
);
170 if ((*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER
) ||
171 (*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER
)) {
172 if (defer_retries
-- > 0) {
173 printk(BIOS_INFO
, "dp: aux write defer (0x%x)"
174 " -- %d\n", *aux_stat
, defer_retries
);
175 /* clear the error bits */
176 tegra_dpaux_writel(dp
, DPAUX_DP_AUXSTAT
,
180 printk(BIOS_ERR
, "dp: aux write defer exceeds"
181 " max retries (0x%x)\n", *aux_stat
);
186 if ((*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_MASK
) ==
187 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK
) {
188 *size
= ((*aux_stat
) & DPAUX_DP_AUXSTAT_REPLY_M_MASK
);
191 printk(BIOS_ERR
, "dp: aux write failed (0x%x)\n",
196 /* Should never come to here */
200 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data
*dp
, u32 cmd
,
201 u32 addr
, u8
*data
, u32
*size
,
205 u32 timeout_retries
= DP_AUX_TIMEOUT_MAX_TRIES
;
206 u32 defer_retries
= DP_AUX_DEFER_MAX_TRIES
;
208 if (*size
> DP_AUX_MAX_BYTES
)
209 return -1; /* only read one chunk */
211 /* Check to make sure the command is read command */
213 case DPAUX_DP_AUXCTL_CMD_I2CRD
:
214 case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT
:
215 case DPAUX_DP_AUXCTL_CMD_MOTRD
:
216 case DPAUX_DP_AUXCTL_CMD_AUXRD
:
219 printk(BIOS_ERR
, "dp: aux read cmd 0x%x is invalid\n", cmd
);
223 *aux_stat
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXSTAT
);
224 if (!(*aux_stat
& DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED
)) {
225 printk(BIOS_SPEW
, "dp: HPD is not detected\n");
229 tegra_dpaux_writel(dp
, DPAUX_DP_AUXADDR
, addr
);
231 reg_val
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXCTL
);
232 reg_val
&= ~DPAUX_DP_AUXCTL_CMD_MASK
;
234 reg_val
&= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD
;
235 reg_val
|= ((*size
- 1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT
);
236 while ((timeout_retries
> 0) && (defer_retries
> 0)) {
237 if ((timeout_retries
!= DP_AUX_TIMEOUT_MAX_TRIES
) ||
238 (defer_retries
!= DP_AUX_DEFER_MAX_TRIES
))
239 udelay(DP_DPCP_RETRY_SLEEP_NS
* 2);
241 reg_val
|= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING
;
242 tegra_dpaux_writel(dp
, DPAUX_DP_AUXCTL
, reg_val
);
244 if (tegra_dpaux_wait_transaction(dp
))
245 printk(BIOS_INFO
, "dp: aux read transaction timeout\n");
247 *aux_stat
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXSTAT
);
249 if ((*aux_stat
& DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING
) ||
250 (*aux_stat
& DPAUX_DP_AUXSTAT_RX_ERROR_PENDING
) ||
251 (*aux_stat
& DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING
) ||
252 (*aux_stat
& DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING
)) {
253 if (timeout_retries
-- > 0) {
254 printk(BIOS_INFO
, "dp: aux read retry (0x%x)"
255 " -- %d\n", *aux_stat
,
257 /* clear the error bits */
258 tegra_dpaux_writel(dp
, DPAUX_DP_AUXSTAT
,
260 continue; /* retry */
262 printk(BIOS_ERR
, "dp: aux read got error"
263 " (0x%x)\n", *aux_stat
);
268 if ((*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER
) ||
269 (*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER
)) {
270 if (defer_retries
-- > 0) {
271 printk(BIOS_INFO
, "dp: aux read defer (0x%x)"
272 " -- %d\n", *aux_stat
, defer_retries
);
273 /* clear the error bits */
274 tegra_dpaux_writel(dp
, DPAUX_DP_AUXSTAT
,
278 printk(BIOS_INFO
, "dp: aux read defer exceeds"
279 " max retries (0x%x)\n", *aux_stat
);
284 if ((*aux_stat
& DPAUX_DP_AUXSTAT_REPLYTYPE_MASK
) ==
285 DPAUX_DP_AUXSTAT_REPLYTYPE_ACK
) {
289 for (i
= 0; i
< DP_AUX_MAX_BYTES
/ 4; ++i
)
290 temp_data
[i
] = tegra_dpaux_readl(dp
,
291 DPAUX_DP_AUXDATA_READ_W(i
));
293 *size
= ((*aux_stat
) & DPAUX_DP_AUXSTAT_REPLY_M_MASK
);
294 memcpy(data
, temp_data
, *size
);
298 printk(BIOS_ERR
, "dp: aux read failed (0x%x\n",
303 /* Should never come to here */
304 printk(BIOS_ERR
, "%s: can't\n", __func__
);
308 #if DO_FAST_LINK_TRAINING
309 static int tegra_dc_dpaux_read(struct tegra_dc_dp_data
*dp
, u32 cmd
, u32 addr
,
310 u8
*data
, u32
*size
, u32
*aux_stat
)
317 cur_size
= *size
- finished
;
318 if (cur_size
> DP_AUX_MAX_BYTES
)
319 cur_size
= DP_AUX_MAX_BYTES
;
321 ret
= tegra_dc_dpaux_read_chunk(dp
, cmd
, addr
,
322 data
, &cur_size
, aux_stat
);
326 /* cur_size should be the real size returned */
329 finished
+= cur_size
;
331 } while (*size
> finished
);
336 #endif /* DO_FAST_LINK_TRAINING */
338 static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data
*dp
, u32 cmd
,
345 ret
= tegra_dc_dpaux_read_chunk(dp
, DPAUX_DP_AUXCTL_CMD_AUXRD
,
346 cmd
, data_ptr
, &size
, &status
);
349 "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
355 static int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data
*dp
, u32 cmd
,
362 ret
= tegra_dc_dpaux_write_chunk(dp
, DPAUX_DP_AUXCTL_CMD_AUXWR
,
363 cmd
, &data
, &size
, &status
);
366 "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
371 static int tegra_dc_i2c_aux_read(struct tegra_dc_dp_data
*dp
, u32 i2c_addr
,
372 u8 addr
, u8
*data
, u32
*size
, u32
*aux_stat
)
378 u32 cur_size
= MIN(DP_AUX_MAX_BYTES
, *size
- finished
);
381 ret
= tegra_dc_dpaux_write_chunk(
382 dp
, DPAUX_DP_AUXCTL_CMD_MOTWR
, i2c_addr
,
383 &addr
, &len
, aux_stat
);
385 printk(BIOS_ERR
, "%s: error sending address to read.\n",
390 ret
= tegra_dc_dpaux_read_chunk(
391 dp
, DPAUX_DP_AUXCTL_CMD_I2CRD
, i2c_addr
,
392 data
, &cur_size
, aux_stat
);
394 printk(BIOS_ERR
, "%s: error reading data.\n", __func__
);
398 /* cur_size should be the real size returned */
401 finished
+= cur_size
;
402 } while (*size
> finished
);
408 static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data
*dp
)
410 /* clear interrupt */
411 tegra_dpaux_writel(dp
, DPAUX_INTR_AUX
, 0xffffffff);
412 /* do not enable interrupt for now. Enable them when Isr in place */
413 tegra_dpaux_writel(dp
, DPAUX_INTR_EN_AUX
, 0x0);
415 tegra_dpaux_writel(dp
, DPAUX_HYBRID_PADCTL
,
416 DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50
|
417 DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70
|
418 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT
|
419 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE
);
421 tegra_dpaux_writel(dp
, DPAUX_HYBRID_SPARE
,
422 DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP
);
425 static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data
*dp
,
426 const struct tegra_dc_dp_link_config
*link_cfg
)
428 printk(BIOS_INFO
, "DP config: cfg_name "
430 printk(BIOS_INFO
, " Lane Count %d\n",
431 link_cfg
->max_lane_count
);
432 printk(BIOS_INFO
, " SupportEnhancedFraming %s\n",
433 link_cfg
->support_enhanced_framing
? "Y" : "N");
434 printk(BIOS_INFO
, " Bandwidth %d\n",
435 link_cfg
->max_link_bw
);
436 printk(BIOS_INFO
, " bpp %d\n",
437 link_cfg
->bits_per_pixel
);
438 printk(BIOS_INFO
, " EnhancedFraming %s\n",
439 link_cfg
->enhanced_framing
? "Y" : "N");
440 printk(BIOS_INFO
, " Scramble_enabled %s\n",
441 link_cfg
->scramble_ena
? "Y" : "N");
442 printk(BIOS_INFO
, " LinkBW %d\n",
444 printk(BIOS_INFO
, " lane_count %d\n",
445 link_cfg
->lane_count
);
446 printk(BIOS_INFO
, " activespolarity %d\n",
447 link_cfg
->activepolarity
);
448 printk(BIOS_INFO
, " active_count %d\n",
449 link_cfg
->active_count
);
450 printk(BIOS_INFO
, " tu_size %d\n",
452 printk(BIOS_INFO
, " active_frac %d\n",
453 link_cfg
->active_frac
);
454 printk(BIOS_INFO
, " watermark %d\n",
455 link_cfg
->watermark
);
456 printk(BIOS_INFO
, " hblank_sym %d\n",
457 link_cfg
->hblank_sym
);
458 printk(BIOS_INFO
, " vblank_sym %d\n",
459 link_cfg
->vblank_sym
);
462 static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data
*dp
,
463 struct tegra_dc_dp_link_config
*link_cfg
)
466 switch (link_cfg
->link_bw
) {
467 case SOR_LINK_SPEED_G1_62
:
468 if (link_cfg
->max_link_bw
> SOR_LINK_SPEED_G1_62
)
469 link_cfg
->link_bw
= SOR_LINK_SPEED_G2_7
;
470 link_cfg
->lane_count
/= 2;
472 case SOR_LINK_SPEED_G2_7
:
473 link_cfg
->link_bw
= SOR_LINK_SPEED_G1_62
;
475 case SOR_LINK_SPEED_G5_4
:
476 if (link_cfg
->lane_count
== 1) {
477 link_cfg
->link_bw
= SOR_LINK_SPEED_G2_7
;
478 link_cfg
->lane_count
= link_cfg
->max_lane_count
;
480 link_cfg
->lane_count
/= 2;
483 printk(BIOS_ERR
, "dp: Error link rate %d\n", link_cfg
->link_bw
);
487 return (link_cfg
->lane_count
> 0) ? DP_LT_SUCCESS
: DP_LT_FAILED
;
490 /* Calcuate if given cfg can meet the mode request. */
491 /* Return true if mode is possible, false otherwise. */
492 static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data
*dp
,
493 const struct soc_nvidia_tegra210_config
*config
,
494 struct tegra_dc_dp_link_config
*link_cfg
)
496 const u32 link_rate
= 27 * link_cfg
->link_bw
* 1000 * 1000;
497 const u64 f
= 100000; /* precision factor */
499 u32 num_linkclk_line
; /* Number of link clocks per line */
500 u64 ratio_f
; /* Ratio of incoming to outgoing data rate */
503 u64 activesym_f
; /* Activesym per TU */
509 u64 accumulated_error_f
= 0;
510 u32 lowest_neg_activecount
= 0;
511 u32 lowest_neg_activepolarity
= 0;
512 u32 lowest_neg_tusize
= 64;
513 u32 num_symbols_per_line
;
514 u64 lowest_neg_activefrac
= 0;
515 u64 lowest_neg_error_f
= 64 * f
;
521 printk(BIOS_INFO
, "dp: %s\n", __func__
);
523 if (!link_rate
|| !link_cfg
->lane_count
|| !config
->pixel_clock
||
524 !link_cfg
->bits_per_pixel
)
527 if ((u64
)config
->pixel_clock
* link_cfg
->bits_per_pixel
>=
528 (u64
)link_rate
* 8 * link_cfg
->lane_count
)
531 num_linkclk_line
= (u32
)((u64
)link_rate
* (u64
)config
->xres
/
532 config
->pixel_clock
);
534 ratio_f
= (u64
)config
->pixel_clock
* link_cfg
->bits_per_pixel
* f
;
536 ratio_f
= (u64
)(ratio_f
/ (link_rate
* link_cfg
->lane_count
));
538 for (i
= 64; i
>= 32; --i
) {
539 activesym_f
= ratio_f
* i
;
540 activecount_f
= (u64
)(activesym_f
/ (u32
)f
) * f
;
541 frac_f
= activesym_f
- activecount_f
;
542 activecount
= (u32
)((u64
)(activecount_f
/ (u32
)f
));
544 if (frac_f
< (f
/ 2)) /* fraction < 0.5 */
552 frac_f
= (u64
)((f
* f
) / frac_f
); /* 1/fraction */
553 if (frac_f
> (15 * f
))
554 activefrac
= activepolarity
? 1 : 15;
556 activefrac
= activepolarity
?
557 (u32
)((u64
)(frac_f
/ (u32
)f
)) + 1 :
558 (u32
)((u64
)(frac_f
/ (u32
)f
));
564 if (activepolarity
== 1)
565 approx_value_f
= activefrac
? (u64
)(
566 (activecount_f
+ (activefrac
* f
- f
) * f
) /
570 approx_value_f
= activefrac
?
571 activecount_f
+ (u64
)(f
/ activefrac
) :
574 if (activesym_f
< approx_value_f
) {
575 accumulated_error_f
= num_linkclk_line
*
576 (u64
)((approx_value_f
- activesym_f
) / i
);
579 accumulated_error_f
= num_linkclk_line
*
580 (u64
)((activesym_f
- approx_value_f
) / i
);
584 if ((neg
&& (lowest_neg_error_f
> accumulated_error_f
)) ||
585 (accumulated_error_f
== 0)) {
586 lowest_neg_error_f
= accumulated_error_f
;
587 lowest_neg_tusize
= i
;
588 lowest_neg_activecount
= activecount
;
589 lowest_neg_activepolarity
= activepolarity
;
590 lowest_neg_activefrac
= activefrac
;
592 if (accumulated_error_f
== 0)
597 if (lowest_neg_activefrac
== 0) {
598 link_cfg
->activepolarity
= 0;
599 link_cfg
->active_count
= lowest_neg_activepolarity
?
600 lowest_neg_activecount
: lowest_neg_activecount
- 1;
601 link_cfg
->tu_size
= lowest_neg_tusize
;
602 link_cfg
->active_frac
= 1;
604 link_cfg
->activepolarity
= lowest_neg_activepolarity
;
605 link_cfg
->active_count
= (u32
)lowest_neg_activecount
;
606 link_cfg
->tu_size
= lowest_neg_tusize
;
607 link_cfg
->active_frac
= (u32
)lowest_neg_activefrac
;
610 watermark_f
= (u64
)((ratio_f
* link_cfg
->tu_size
* (f
- ratio_f
)) / f
);
611 link_cfg
->watermark
= (u32
)((u64
)((watermark_f
+ lowest_neg_error_f
) /
612 f
)) + link_cfg
->bits_per_pixel
/ 4 - 1;
613 num_symbols_per_line
= (config
->xres
* link_cfg
->bits_per_pixel
) /
614 (8 * link_cfg
->lane_count
);
616 if (link_cfg
->watermark
> 30) {
618 "dp: sor setting: unable to get a good tusize, "
619 "force watermark to 30.\n");
620 link_cfg
->watermark
= 30;
622 } else if (link_cfg
->watermark
> num_symbols_per_line
) {
624 "dp: sor setting: force watermark to the number "
625 "of symbols in the line.\n");
626 link_cfg
->watermark
= num_symbols_per_line
;
630 /* Refer to dev_disp.ref for more information. */
631 /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
632 /* SetRasterBlankStart.X - 7) * link_clk / pclk) */
633 /* - 3 * enhanced_framing - Y */
634 /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
635 link_cfg
->hblank_sym
= (int)((u64
)(((u64
)(config
->hback_porch
+
636 config
->hfront_porch
+ config
->hsync_width
- 7) *
637 link_rate
) / config
->pixel_clock
)) -
638 3 * link_cfg
->enhanced_framing
-
639 (12 / link_cfg
->lane_count
);
641 if (link_cfg
->hblank_sym
< 0)
642 link_cfg
->hblank_sym
= 0;
645 /* Refer to dev_disp.ref for more information. */
646 /* # symbols/vblank = ((SetRasterBlankStart.X - */
647 /* SetRasterBlankEen.X - 25) * link_clk / pclk) */
649 /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
650 link_cfg
->vblank_sym
= (int)((u64
)((u64
)(config
->xres
- 25)
651 * link_rate
/ config
->pixel_clock
)) - (36 /
652 link_cfg
->lane_count
) - 4;
654 if (link_cfg
->vblank_sym
< 0)
655 link_cfg
->vblank_sym
= 0;
657 link_cfg
->is_valid
= 1;
658 tegra_dc_dp_dump_link_cfg(dp
, link_cfg
);
663 static int tegra_dc_dp_init_max_link_cfg(
664 struct soc_nvidia_tegra210_config
*config
,
665 struct tegra_dc_dp_data
*dp
,
666 struct tegra_dc_dp_link_config
*link_cfg
)
671 printk(BIOS_INFO
, "dp: %s\n", __func__
);
673 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, NV_DPCD_MAX_LANE_COUNT
,
675 link_cfg
->max_lane_count
= dpcd_data
& NV_DPCD_MAX_LANE_COUNT_MASK
;
676 link_cfg
->tps3_supported
= (dpcd_data
&
677 NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES
) ? 1 : 0;
679 link_cfg
->support_enhanced_framing
=
680 (dpcd_data
& NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES
) ?
683 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, NV_DPCD_MAX_DOWNSPREAD
,
685 link_cfg
->downspread
= (dpcd_data
& NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT
)
688 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, NV_DPCD_TRAINING_AUX_RD_INTERVAL
,
689 &link_cfg
->aux_rd_interval
));
691 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, NV_DPCD_MAX_LINK_BANDWIDTH
,
692 &link_cfg
->max_link_bw
));
694 link_cfg
->bits_per_pixel
= config
->panel_bits_per_pixel
;
697 * Set to a high value for link training and attach.
698 * Will be re-programmed when dp is enabled.
700 link_cfg
->drive_current
= config
->dp
.drive_current
;
701 link_cfg
->preemphasis
= config
->dp
.preemphasis
;
702 link_cfg
->postcursor
= config
->dp
.postcursor
;
704 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, NV_DPCD_EDP_CONFIG_CAP
,
706 link_cfg
->alt_scramber_reset_cap
=
707 (dpcd_data
& NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES
) ?
709 link_cfg
->only_enhanced_framing
=
710 (dpcd_data
& NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES
) ?
713 link_cfg
->lane_count
= link_cfg
->max_lane_count
;
714 link_cfg
->link_bw
= link_cfg
->max_link_bw
;
715 link_cfg
->enhanced_framing
= link_cfg
->support_enhanced_framing
;
717 tegra_dc_dp_calc_config(dp
, config
, link_cfg
);
721 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data
*dp
, int ena
)
726 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE
:
727 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE
;
729 CHECK_RET(tegra_dc_dp_dpcd_write(dp
, NV_DPCD_EDP_CONFIG_SET
,
732 /* Also reset the scrambler to 0xfffe */
733 tegra_dc_sor_set_internal_panel(&dp
->sor
, ena
);
737 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data
*dp
, u8 link_bw
)
739 tegra_dc_sor_set_link_bandwidth(&dp
->sor
, link_bw
);
742 return tegra_dc_dp_dpcd_write(dp
, NV_DPCD_LINK_BANDWIDTH_SET
, link_bw
);
745 static int tegra_dp_set_lane_count(struct tegra_dc_dp_data
*dp
,
746 const struct tegra_dc_dp_link_config
*link_cfg
)
751 /* check if panel support enhanched_framing */
752 dpcd_data
= link_cfg
->lane_count
;
753 if (link_cfg
->enhanced_framing
)
754 dpcd_data
|= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T
;
755 CHECK_RET(tegra_dc_dp_dpcd_write(dp
, NV_DPCD_LANE_COUNT_SET
,
758 tegra_dc_sor_set_lane_count(&dp
->sor
, link_cfg
->lane_count
);
760 /* Also power down lanes that will not be used */
764 #if DO_FAST_LINK_TRAINING
765 static int tegra_dc_dp_link_trained(struct tegra_dc_dp_data
*dp
,
766 const struct tegra_dc_dp_link_config
*link_cfg
)
773 for (lane
= 0; lane
< link_cfg
->lane_count
; ++lane
) {
774 CHECK_RET(tegra_dc_dp_dpcd_read(dp
, (lane
/2) ?
775 NV_DPCD_LANE2_3_STATUS
: NV_DPCD_LANE0_1_STATUS
,
778 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES
|
779 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES
|
780 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES
:
781 NV_DPCD_STATUS_LANEX_CR_DONE_YES
|
782 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES
|
783 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES
;
784 if ((data
& mask
) != mask
)
789 #endif /* DO_FAST_LINK_TRAINING */
791 static int tegra_dp_channel_eq_status(struct tegra_dc_dp_data
*dp
)
794 u32 n_lanes
= dp
->link_cfg
.lane_count
;
798 for (cnt
= 0; cnt
< n_lanes
/ 2; cnt
++) {
799 tegra_dc_dp_dpcd_read(dp
, (NV_DPCD_LANE0_1_STATUS
+ cnt
),
804 (data
& (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT
)) &&
805 (data
& (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT
));
808 if (!(data
& (0x1 << NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT
)) ||
809 !(data
& (0x1 << NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT
)) ||
810 !(data
& (0x1 << NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT
)) ||
811 !(data
& (0x1 << NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT
)))
816 tegra_dc_dp_dpcd_read(dp
, NV_DPCD_LANE_ALIGN_STATUS_UPDATED
,
818 if (!(data
& NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES
))
825 static u8
tegra_dp_clock_recovery_status(struct tegra_dc_dp_data
*dp
)
828 u32 n_lanes
= dp
->link_cfg
.lane_count
;
831 for (cnt
= 0; cnt
< n_lanes
/ 2; cnt
++) {
832 tegra_dc_dp_dpcd_read(dp
,
833 (NV_DPCD_LANE0_1_STATUS
+ cnt
), &data_ptr
);
836 return (data_ptr
& NV_DPCD_STATUS_LANEX_CR_DONE_YES
) ? 1 : 0;
837 else if (!(data_ptr
& NV_DPCD_STATUS_LANEX_CR_DONE_YES
) ||
838 !(data_ptr
& (NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES
)))
845 static void tegra_dp_lt_adjust(struct tegra_dc_dp_data
*dp
,
846 u32 pe
[4], u32 vs
[4], u32 pc
[4],
851 u32 n_lanes
= dp
->link_cfg
.lane_count
;
853 for (cnt
= 0; cnt
< n_lanes
/ 2; cnt
++) {
854 tegra_dc_dp_dpcd_read(dp
,
855 (NV_DPCD_LANE0_1_ADJUST_REQ
+ cnt
), &data_ptr
);
856 pe
[2 * cnt
] = (data_ptr
& NV_DPCD_ADJUST_REQ_LANEX_PE_MASK
) >>
857 NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT
;
858 vs
[2 * cnt
] = (data_ptr
& NV_DPCD_ADJUST_REQ_LANEX_DC_MASK
) >>
859 NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT
;
861 (data_ptr
& NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK
) >>
862 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT
;
864 (data_ptr
& NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK
) >>
865 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT
;
868 tegra_dc_dp_dpcd_read(dp
,
869 NV_DPCD_ADJUST_REQ_POST_CURSOR2
, &data_ptr
);
870 for (cnt
= 0; cnt
< n_lanes
; cnt
++) {
871 pc
[cnt
] = (data_ptr
>>
872 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(cnt
)) &
873 NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK
;
878 static inline u32
tegra_dp_wait_aux_training(struct tegra_dc_dp_data
*dp
,
881 if (!dp
->link_cfg
.aux_rd_interval
)
882 is_clk_recovery
? udelay(200) :
885 mdelay(dp
->link_cfg
.aux_rd_interval
* 4);
887 return dp
->link_cfg
.aux_rd_interval
;
890 static void tegra_dp_tpg(struct tegra_dc_dp_data
*dp
, u32 tp
, u32 n_lanes
)
892 u8 data
= (tp
== training_pattern_disabled
)
893 ? (tp
| NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F
)
894 : (tp
| NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T
);
896 tegra_dc_sor_set_dp_linkctl(&dp
->sor
, 1, tp
, &dp
->link_cfg
);
897 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_PATTERN_SET
, data
);
900 static int tegra_dp_link_config(struct tegra_dc_dp_data
*dp
,
901 const struct tegra_dc_dp_link_config
*link_cfg
)
906 if (link_cfg
->lane_count
== 0) {
907 printk(BIOS_ERR
, "dp: error: lane count is 0. "
908 "Can not set link config.\n");
912 /* Set power state if it is not in normal level */
913 if (tegra_dc_dp_dpcd_read(dp
, NV_DPCD_SET_POWER
, &dpcd_data
))
916 if (dpcd_data
== NV_DPCD_SET_POWER_VAL_D3_PWRDWN
) {
917 dpcd_data
= NV_DPCD_SET_POWER_VAL_D0_NORMAL
;
919 /* DP spec requires 3 retries */
920 for (retry
= 3; retry
> 0; --retry
) {
921 if (tegra_dc_dp_dpcd_write(dp
, NV_DPCD_SET_POWER
,
925 printk(BIOS_ERR
, "dp: Failed to set DP panel"
932 /* Enable ASSR if possible */
933 if (link_cfg
->alt_scramber_reset_cap
)
934 if (tegra_dc_dp_set_assr(dp
, 1))
937 if (tegra_dp_set_link_bandwidth(dp
, link_cfg
->link_bw
)) {
938 printk(BIOS_ERR
, "dp: Failed to set link bandwidth\n");
941 if (tegra_dp_set_lane_count(dp
, link_cfg
)) {
942 printk(BIOS_ERR
, "dp: Failed to set lane count\n");
945 tegra_dc_sor_set_dp_linkctl(&dp
->sor
, 1, training_pattern_none
,
947 return DP_LT_SUCCESS
;
950 static int tegra_dp_lower_link_config(struct tegra_dc_dp_data
*dp
,
951 struct tegra_dc_dp_link_config
*cfg
)
953 struct tegra_dc_dp_link_config tmp_cfg
;
955 tmp_cfg
= dp
->link_cfg
;
958 if (_tegra_dp_lower_link_config(dp
, cfg
))
961 if (tegra_dc_dp_calc_config(dp
, dp
->dc
->config
, cfg
))
963 tegra_dp_link_config(dp
, cfg
);
965 return DP_LT_SUCCESS
;
967 dp
->link_cfg
= tmp_cfg
;
968 tegra_dp_link_config(dp
, &tmp_cfg
);
972 static void tegra_dp_lt_config(struct tegra_dc_dp_data
*dp
,
973 u32 pe
[4], u32 vs
[4], u32 pc
[4])
975 struct tegra_dc_sor_data
*sor
= &dp
->sor
;
976 u32 n_lanes
= dp
->link_cfg
.lane_count
;
977 u8 pc_supported
= dp
->link_cfg
.tps3_supported
;
981 for (cnt
= 0; cnt
< n_lanes
; cnt
++) {
983 u32 pe_reg
, vs_reg
, pc_reg
;
988 mask
= NV_SOR_PR_LANE2_DP_LANE0_MASK
;
989 shift
= NV_SOR_PR_LANE2_DP_LANE0_SHIFT
;
992 mask
= NV_SOR_PR_LANE1_DP_LANE1_MASK
;
993 shift
= NV_SOR_PR_LANE1_DP_LANE1_SHIFT
;
996 mask
= NV_SOR_PR_LANE0_DP_LANE2_MASK
;
997 shift
= NV_SOR_PR_LANE0_DP_LANE2_SHIFT
;
1000 mask
= NV_SOR_PR_LANE3_DP_LANE3_MASK
;
1001 shift
= NV_SOR_PR_LANE3_DP_LANE3_SHIFT
;
1005 "dp: incorrect lane cnt\n");
1008 pe_reg
= tegra_dp_pe_regs
[pc
[cnt
]][vs
[cnt
]][pe
[cnt
]];
1009 vs_reg
= tegra_dp_vs_regs
[pc
[cnt
]][vs
[cnt
]][pe
[cnt
]];
1010 pc_reg
= tegra_dp_pc_regs
[pc
[cnt
]][vs
[cnt
]][pe
[cnt
]];
1012 tegra_dp_set_pe_vs_pc(sor
, mask
, pe_reg
<< shift
,
1013 vs_reg
<< shift
, pc_reg
<< shift
, pc_supported
);
1016 tegra_dp_disable_tx_pu(&dp
->sor
);
1019 for (cnt
= 0; cnt
< n_lanes
; cnt
++) {
1020 u32 max_vs_flag
= tegra_dp_is_max_vs(pe
[cnt
], vs
[cnt
]);
1021 u32 max_pe_flag
= tegra_dp_is_max_pe(pe
[cnt
], vs
[cnt
]);
1023 val
= (vs
[cnt
] << NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT
) |
1025 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T
:
1026 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F
) |
1027 (pe
[cnt
] << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT
) |
1029 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T
:
1030 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F
);
1031 tegra_dc_dp_dpcd_write(dp
,
1032 (NV_DPCD_TRAINING_LANE0_SET
+ cnt
), val
);
1036 for (cnt
= 0; cnt
< n_lanes
/ 2; cnt
++) {
1037 u32 max_pc_flag0
= tegra_dp_is_max_pc(pc
[cnt
]);
1038 u32 max_pc_flag1
= tegra_dp_is_max_pc(pc
[cnt
+ 1]);
1039 val
= (pc
[cnt
] << NV_DPCD_LANEX_SET2_PC2_SHIFT
) |
1041 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T
:
1042 NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F
) |
1044 NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT
) |
1046 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T
:
1047 NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F
);
1048 tegra_dc_dp_dpcd_write(dp
,
1049 (NV_DPCD_TRAINING_LANE0_1_SET2
+ cnt
), val
);
1054 static int _tegra_dp_channel_eq(struct tegra_dc_dp_data
*dp
, u32 pe
[4],
1055 u32 vs
[4], u32 pc
[4], u8 pc_supported
,
1060 for (retry_cnt
= 0; retry_cnt
< 4; retry_cnt
++) {
1062 tegra_dp_lt_adjust(dp
, pe
, vs
, pc
, pc_supported
);
1063 tegra_dp_lt_config(dp
, pe
, vs
, pc
);
1066 tegra_dp_wait_aux_training(dp
, 0);
1068 if (!tegra_dp_clock_recovery_status(dp
)) {
1069 printk(BIOS_ERR
, "dp: CR failed in channel EQ"
1074 if (tegra_dp_channel_eq_status(dp
))
1075 return DP_LT_SUCCESS
;
1078 return DP_LT_FAILED
;
1081 static int tegra_dp_channel_eq(struct tegra_dc_dp_data
*dp
,
1082 u32 pe
[4], u32 vs
[4], u32 pc
[4])
1084 u32 n_lanes
= dp
->link_cfg
.lane_count
;
1085 u8 pc_supported
= dp
->link_cfg
.tps3_supported
;
1087 u32 tp_src
= training_pattern_2
;
1090 tp_src
= training_pattern_3
;
1092 tegra_dp_tpg(dp
, tp_src
, n_lanes
);
1094 err
= _tegra_dp_channel_eq(dp
, pe
, vs
, pc
, pc_supported
, n_lanes
);
1096 tegra_dp_tpg(dp
, training_pattern_disabled
, n_lanes
);
1101 static int _tegra_dp_clk_recovery(struct tegra_dc_dp_data
*dp
, u32 pe
[4],
1102 u32 vs
[4], u32 pc
[4], u8 pc_supported
,
1109 tegra_dp_lt_config(dp
, pe
, vs
, pc
);
1110 tegra_dp_wait_aux_training(dp
, 1);
1112 if (tegra_dp_clock_recovery_status(dp
))
1113 return DP_LT_SUCCESS
;
1115 memcpy(vs_temp
, vs
, sizeof(vs_temp
));
1116 tegra_dp_lt_adjust(dp
, pe
, vs
, pc
, pc_supported
);
1118 if (memcmp(vs_temp
, vs
, sizeof(vs_temp
)))
1122 } while (retry_cnt
< 5);
1124 return DP_LT_FAILED
;
1127 static int tegra_dp_clk_recovery(struct tegra_dc_dp_data
*dp
,
1128 u32 pe
[4], u32 vs
[4], u32 pc
[4])
1130 u32 n_lanes
= dp
->link_cfg
.lane_count
;
1131 u8 pc_supported
= dp
->link_cfg
.tps3_supported
;
1134 tegra_dp_tpg(dp
, training_pattern_1
, n_lanes
);
1136 err
= _tegra_dp_clk_recovery(dp
, pe
, vs
, pc
, pc_supported
, n_lanes
);
1138 tegra_dp_tpg(dp
, training_pattern_disabled
, n_lanes
);
1143 static int tegra_dc_dp_full_link_training(struct tegra_dc_dp_data
*dp
)
1145 struct tegra_dc_sor_data
*sor
= &dp
->sor
;
1147 u32 pe
[4], vs
[4], pc
[4];
1149 printk(BIOS_INFO
, "dp: %s\n", __func__
);
1150 tegra_sor_precharge_lanes(sor
);
1153 memset(pe
, preEmphasis_Disabled
, sizeof(pe
));
1154 memset(vs
, driveCurrent_Level0
, sizeof(vs
));
1155 memset(pc
, postCursor2_Level0
, sizeof(pc
));
1157 err
= tegra_dp_clk_recovery(dp
, pe
, vs
, pc
);
1158 if (err
!= DP_LT_SUCCESS
) {
1159 if (!tegra_dp_lower_link_config(dp
, &dp
->link_cfg
))
1162 printk(BIOS_ERR
, "dp: clk recovery failed\n");
1166 err
= tegra_dp_channel_eq(dp
, pe
, vs
, pc
);
1167 if (err
!= DP_LT_SUCCESS
) {
1168 if (!tegra_dp_lower_link_config(dp
, &dp
->link_cfg
))
1172 "dp: channel equalization failed\n");
1176 tegra_dc_dp_dump_link_cfg(dp
, &dp
->link_cfg
);
1185 * All link training functions are ported from kernel dc driver.
1186 * See more details at drivers/video/tegra/dc/dp.c
1188 #if DO_FAST_LINK_TRAINING
1189 static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data
*dp
,
1190 const struct tegra_dc_dp_link_config
*link_cfg
)
1192 struct tegra_dc_sor_data
*sor
= &dp
->sor
;
1200 u32 mask
= 0xffff >> ((4 - link_cfg
->lane_count
) * 4);
1203 printk(BIOS_INFO
, "dp: %s\n", __func__
);
1205 tegra_dc_sor_set_lane_parm(sor
, link_cfg
);
1206 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET
,
1207 NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B
);
1210 tegra_dc_sor_set_dp_linkctl(sor
, 1, training_pattern_1
, link_cfg
);
1211 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_PATTERN_SET
,
1212 NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1
);
1214 for (j
= 0; j
< link_cfg
->lane_count
; ++j
)
1215 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_LANE0_SET
+ j
,
1219 size
= sizeof(data16
);
1220 tegra_dc_dpaux_read(dp
, DPAUX_DP_AUXCTL_CMD_AUXRD
,
1221 NV_DPCD_LANE0_1_STATUS
, (u8
*)&data16
, &size
, &status
);
1222 status
= mask
& 0x1111;
1223 if ((data16
& status
) != status
) {
1225 "dp: Link training error for TP1 (%#x)\n", data16
);
1230 tegra_dc_dp_set_assr(dp
, link_cfg
->scramble_ena
);
1231 tegra_dc_sor_set_dp_linkctl(sor
, 1, training_pattern_3
, link_cfg
);
1233 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_PATTERN_SET
,
1234 link_cfg
->link_bw
== 20 ? 0x23 : 0x22);
1235 for (j
= 0; j
< link_cfg
->lane_count
; ++j
)
1236 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_LANE0_SET
+ j
,
1240 size
= sizeof(data32
);
1241 tegra_dc_dpaux_read(dp
, DPAUX_DP_AUXCTL_CMD_AUXRD
,
1242 NV_DPCD_LANE0_1_STATUS
, (u8
*)&data32
, &size
, &status
);
1243 if ((data32
& mask
) != (0x7777 & mask
)) {
1245 "dp: Link training error for TP2/3 (0x%x)\n", data32
);
1249 tegra_dc_sor_set_dp_linkctl(sor
, 1, training_pattern_disabled
,
1251 tegra_dc_dp_dpcd_write(dp
, NV_DPCD_TRAINING_PATTERN_SET
, 0);
1253 if (tegra_dc_dp_link_trained(dp
, link_cfg
)) {
1254 tegra_dc_sor_read_link_config(&dp
->sor
, &link_bw
,
1257 "Fast link trainging failed, link bw %d, lane # %d\n",
1258 link_bw
, lane_count
);
1263 "Fast link trainging succeeded, link bw %d, lane %d\n",
1264 link_cfg
->link_bw
, link_cfg
->lane_count
);
1268 #endif /* DO_FAST_LINK_TRAINING */
1270 static int tegra_dp_do_link_training(struct tegra_dc_dp_data
*dp
,
1271 const struct tegra_dc_dp_link_config
*link_cfg
)
1275 #if DO_FAST_LINK_TRAINING
1278 /* Now do the fast link training for eDP */
1279 ret
= tegra_dc_dp_fast_link_training(dp
, link_cfg
);
1281 printk(BIOS_ERR
, "dp: fast link training failed\n");
1283 /* Try full link training then */
1284 if (tegra_dc_dp_full_link_training(dp
)) {
1285 printk(BIOS_ERR
, "dp: full link training failed\n");
1289 /* set to a known-good drive setting if fast link succeeded */
1290 tegra_dc_sor_set_voltage_swing(&dp
->sor
);
1293 if (tegra_dc_dp_full_link_training(dp
)) {
1294 printk(BIOS_ERR
, "dp: full link training failed\n");
1299 /* Everything goes well, double check the link config */
1300 /* TODO: record edc/c2 data for debugging */
1301 tegra_dc_sor_read_link_config(&dp
->sor
, &link_bw
, &lane_count
);
1303 if ((link_cfg
->link_bw
== link_bw
) &&
1304 (link_cfg
->lane_count
== lane_count
))
1310 static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data
*dp
,
1311 struct tegra_dc_dp_link_config
*link_cfg
,
1312 const struct soc_nvidia_tegra210_config
*config
)
1314 struct tegra_dc_dp_link_config temp_cfg
;
1316 if (!config
->pixel_clock
|| !config
->xres
|| !config
->yres
) {
1318 "dp: error mode configuration");
1321 if (!link_cfg
->max_link_bw
|| !link_cfg
->max_lane_count
) {
1323 "dp: error link configuration");
1327 link_cfg
->is_valid
= 0;
1329 memcpy(&temp_cfg
, link_cfg
, sizeof(temp_cfg
));
1331 temp_cfg
.link_bw
= temp_cfg
.max_link_bw
;
1332 temp_cfg
.lane_count
= temp_cfg
.max_lane_count
;
1335 * set to max link config
1337 if ((!tegra_dc_dp_calc_config(dp
, config
, &temp_cfg
)) &&
1338 (!tegra_dp_link_config(dp
, &temp_cfg
)) &&
1339 (!tegra_dp_do_link_training(dp
, &temp_cfg
)))
1340 /* the max link cfg is doable */
1341 memcpy(link_cfg
, &temp_cfg
, sizeof(temp_cfg
));
1343 return link_cfg
->is_valid
? 0 : -EFAULT
;
1346 static void tegra_dp_update_config(struct tegra_dc_dp_data
*dp
,
1347 struct soc_nvidia_tegra210_config
*config
)
1351 u32 size
= sizeof(buf
), aux_stat
= 0;
1353 printk(BIOS_ERR
, "%s: enable r/w dump.\n",
1356 tegra_dc_dpaux_enable(dp
);
1357 if (tegra_dc_i2c_aux_read(dp
, TEGRA_EDID_I2C_ADDRESS
, 0, buf
, &size
,
1359 printk(BIOS_ERR
, "%s: Failed to read EDID. Use defaults.\n",
1364 if (decode_edid(buf
, sizeof(buf
), &edid
)) {
1365 printk(BIOS_ERR
, "%s: Failed to decode EDID. Use defaults.\n",
1370 config
->xres
= config
->display_xres
= edid
.mode
.ha
;
1371 config
->yres
= config
->display_yres
= edid
.mode
.va
;
1373 config
->pixel_clock
= edid
.mode
.pixel_clock
* 1000;
1375 config
->hfront_porch
= edid
.mode
.hso
;
1376 config
->hsync_width
= edid
.mode
.hspw
;
1377 config
->hback_porch
= edid
.mode
.hbl
- edid
.mode
.hso
- edid
.mode
.hspw
;
1379 config
->vfront_porch
= edid
.mode
.vso
;
1380 config
->vsync_width
= edid
.mode
.vspw
;
1381 config
->vback_porch
= edid
.mode
.vbl
- edid
.mode
.vso
- edid
.mode
.vspw
;
1384 * Note edid->framebuffer_bits_per_pixel is currently hard-coded as 32,
1385 * so we should keep the default value in device config.
1387 * EDID v1.3 panels may not have color depth info, so we need to check
1388 * if these values are zero before updating config.
1390 if (edid
.panel_bits_per_pixel
)
1391 config
->panel_bits_per_pixel
= edid
.panel_bits_per_pixel
;
1392 if (edid
.panel_bits_per_color
)
1393 config
->color_depth
= edid
.panel_bits_per_color
;
1394 printk(BIOS_SPEW
, "%s: configuration updated by EDID.\n", __func__
);
1397 void dp_init(void *_config
)
1399 struct soc_nvidia_tegra210_config
*config
= (void *)_config
;
1400 struct tegra_dc
*dc
= config
->dc_data
;
1401 struct tegra_dc_dp_data
*dp
= &dp_data
;
1403 /* set up links among config, dc, dp and sor */
1408 dp
->sor
.power_is_up
= 0;
1409 dp
->sor
.base
= (void *)TEGRA_ARM_SOR
;
1410 dp
->sor
.pmc_base
= (void *)TEGRA_PMC_BASE
;
1411 dp
->sor
.portnum
= 0;
1412 dp
->sor
.link_cfg
= &dp
->link_cfg
;
1413 dp
->aux_base
= (void *)TEGRA_ARM_DPAUX
;
1414 dp
->link_cfg
.is_valid
= 0;
1417 tegra_dp_update_config(dp
, config
);
1420 static void tegra_dp_hpd_config(struct tegra_dc_dp_data
*dp
,
1421 struct soc_nvidia_tegra210_config
*config
)
1425 val
= config
->dp
.hpd_plug_min_us
|
1426 (config
->dp
.hpd_unplug_min_us
<<
1427 DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT
);
1428 tegra_dpaux_writel(dp
, DPAUX_HPD_CONFIG
, val
);
1430 tegra_dpaux_writel(dp
, DPAUX_HPD_IRQ_CONFIG
, config
->dp
.hpd_irq_min_us
);
1433 static int tegra_dp_hpd_plug(struct tegra_dc_dp_data
*dp
, int timeout_ms
)
1436 u32 timeout
= timeout_ms
* 1000;
1438 val
= tegra_dpaux_readl(dp
, DPAUX_DP_AUXSTAT
);
1439 if (val
& DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED
)
1443 } while (timeout
> 0);
1447 static int tegra_dc_dp_sink_out_of_sync(struct tegra_dc_dp_data
*dp
,
1454 tegra_dc_dp_dpcd_read(dp
, NV_DPCD_SINK_STATUS
, &dpcd_data
);
1456 out_of_sync
= ((dpcd_data
& NV_DPCD_SINK_STATUS_PORT0_IN_SYNC
) !=
1457 NV_DPCD_SINK_STATUS_PORT0_IN_SYNC
);
1461 "SINK receive port 0 is out of synchronization\n");
1464 "SINK is in synchronization\n");
1469 static void tegra_dc_dp_check_sink(struct tegra_dc_dp_data
*dp
,
1470 struct soc_nvidia_tegra210_config
*config
)
1476 /* DP TCON may skip some main stream frames, thus we need to wait
1477 some delay before reading the DPCD SINK STATUS register, starting
1481 while (tegra_dc_dp_sink_out_of_sync(dp
, FRAME_IN_MS
* delay_frame
) &&
1483 tegra_dc_detach(&dp
->sor
);
1484 if (tegra_dc_dp_explore_link_cfg(dp
, &dp
->link_cfg
, config
)) {
1485 printk(BIOS_ERR
, "dp: %s: error to configure link\n",
1490 tegra_dc_sor_set_power_state(&dp
->sor
, 1);
1491 tegra_dc_sor_attach(&dp
->sor
);
1493 /* Increase delay_frame for next try in case the sink is
1494 skipping more frames */
1499 void dp_enable(void *_dp
)
1501 struct tegra_dc_dp_data
*dp
= _dp
;
1502 struct tegra_dc
*dc
= dp
->dc
;
1503 struct soc_nvidia_tegra210_config
*config
= dc
->config
;
1509 tegra_dc_dpaux_enable(dp
);
1511 tegra_dp_hpd_config(dp
, config
);
1512 if (tegra_dp_hpd_plug(dp
, config
->dp
.vdd_to_hpd_delay_ms
) < 0) {
1513 printk(BIOS_ERR
, "dp: hpd plug failed\n");
1517 if (tegra_dc_dp_init_max_link_cfg(config
, dp
, &dp
->link_cfg
)) {
1518 printk(BIOS_ERR
, "dp: failed to init link configuration\n");
1522 tegra_dc_sor_enable_dp(&dp
->sor
);
1524 tegra_dc_sor_set_panel_power(&dp
->sor
, 1);
1526 /* Write power on to DPCD */
1527 data
= NV_DPCD_SET_POWER_VAL_D0_NORMAL
;
1530 ret
= tegra_dc_dp_dpcd_write(dp
,
1531 NV_DPCD_SET_POWER
, data
);
1532 } while ((retry
++ < DP_POWER_ON_MAX_TRIES
) && ret
);
1534 if (ret
|| retry
>= DP_POWER_ON_MAX_TRIES
) {
1536 "dp: failed to power on panel (0x%x)\n", ret
);
1540 /* Confirm DP is plugging status */
1541 if (!(tegra_dpaux_readl(dp
, DPAUX_DP_AUXSTAT
) &
1542 DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED
)) {
1543 printk(BIOS_ERR
, "dp: could not detect HPD\n");
1547 /* Check DP version */
1548 if (tegra_dc_dp_dpcd_read(dp
, NV_DPCD_REV
, &dp
->revision
))
1550 "dp: failed to read the revision number from sink\n");
1552 if (tegra_dc_dp_explore_link_cfg(dp
, &dp
->link_cfg
, config
)) {
1553 printk(BIOS_ERR
, "dp: error to configure link\n");
1557 tegra_dc_sor_set_power_state(&dp
->sor
, 1);
1558 tegra_dc_sor_attach(&dp
->sor
);
1560 tegra_dc_dp_check_sink(dp
, config
);
1563 * Power down the unused lanes to save power
1564 * (about hundreds milli-watts, varies from boards).
1566 tegra_dc_sor_power_down_unused_lanes(&dp
->sor
);
1573 void dp_display_startup(device_t dev
)
1575 struct soc_nvidia_tegra210_config
*config
= dev
->chip_info
;
1576 struct display_controller
*disp_ctrl
=
1577 (void *)config
->display_controller
;
1579 u32 framebuffer_size_mb
= config
->framebuffer_size
/ MiB
;
1580 u32 framebuffer_base_mb
= config
->framebuffer_base
/ MiB
;
1582 struct pwm_controller
*pwm
= (void *)TEGRA_PWM_BASE
;
1583 struct tegra_dc
*dc
= &dc_data
;
1586 printk(BIOS_INFO
, "%s: entry: disp_ctrl: %p.\n",
1587 __func__
, disp_ctrl
);
1589 if (disp_ctrl
== NULL
) {
1590 printk(BIOS_ERR
, "Error: No dc is assigned by dt.\n");
1594 dc
->base
= (void *)disp_ctrl
;
1595 dc
->config
= config
;
1596 config
->dc_data
= dc
;
1598 /* Note dp_init may read EDID and change some config values. */
1601 if (framebuffer_size_mb
== 0) {
1602 framebuffer_size_mb
= ALIGN_UP(config
->display_xres
*
1603 config
->display_yres
*
1604 (config
->framebuffer_bits_per_pixel
/ 8), MiB
)/MiB
;
1607 config
->framebuffer_size
= framebuffer_size_mb
* MiB
;
1608 config
->framebuffer_base
= framebuffer_base_mb
* MiB
;
1610 /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
1611 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
1612 * update_display_mode() for detail.
1614 plld_rate
= clock_configure_plld(config
->pixel_clock
* 2);
1615 if (plld_rate
== 0) {
1616 printk(BIOS_ERR
, "dc: clock init failed\n");
1618 } else if (plld_rate
!= config
->pixel_clock
* 2) {
1619 printk(BIOS_WARNING
, "dc: plld rounded to %u\n", plld_rate
);
1620 config
->pixel_clock
= plld_rate
/ 2;
1623 /* set disp1's clock source to PLLD_OUT0 */
1624 clock_configure_source(disp1
, PLLD
, (plld_rate
/KHz
)/2);
1627 if (tegra_dc_init(disp_ctrl
)) {
1628 printk(BIOS_ERR
, "dc: init failed\n");
1632 /* Configure dc mode */
1633 if (update_display_mode(disp_ctrl
, config
)) {
1634 printk(BIOS_ERR
, "dc: failed to configure display mode.\n");
1641 /* Set up Tegra PWM n (where n is specified in config->dp.pwm) to drive the
1644 printk(BIOS_SPEW
, "%s: enable panel backlight pwm\n", __func__
);
1645 WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT
) |
1646 (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT
) | /* 220/256 */
1647 0x02e), /* frequency divider */
1648 &pwm
->pwm
[config
->dp
.pwm
].csr
);
1651 update_window(config
);
1652 printk(BIOS_INFO
, "%s: display init done.\n", __func__
);
1654 /* Save panel mode to cb tables */
1655 pass_mode_info_to_payload(config
);
1658 * After this point, it is payload's responsibility to allocate
1659 * framebuffer and sets the base address to dc's
1660 * WINBUF_START_ADDR register and enables window by setting dc's
1661 * DISP_DISP_WIN_OPTIONS register.