src/mainboard/pcengines/apu2/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <AGESA.h>
  17 #include <northbridge/amd/pi/agesawrapper.h>
  18
  19
  20 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  21         {
  22                 0,
  23                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
  24                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
  25                                 HotplugDisabled,
  26                                 PcieGenMaxSupported,
  27                                 PcieGenMaxSupported,
  28                                 AspmDisabled, 0x01, 0)
  29         },
  30         /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
  31         {
  32                 0,
  33                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
  34                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
  35                                 HotplugDisabled,
  36                                 PcieGenMaxSupported,
  37                                 PcieGenMaxSupported,
  38                                 AspmDisabled, 0x02, 0)
  39         },
  40         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  41         {
  42                 0,
  43                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
  44                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
  45                                 HotplugDisabled,
  46                                 PcieGenMaxSupported,
  47                                 PcieGenMaxSupported,
  48                                 AspmDisabled, 0x03, 0)
  49         },
  50         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  51         {
  52                 0,
  53                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
  54                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
  55                                 HotplugDisabled,
  56                                 PcieGenMaxSupported,
  57                                 PcieGenMaxSupported,
  58                                 AspmDisabled, 0x04, 0)
  59         },
  60         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
  61         {
  62                 DESCRIPTOR_TERMINATE_LIST,
  63                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
  64                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
  65                                 HotplugDisabled,
  66                                 PcieGenMaxSupported,
  67                                 PcieGenMaxSupported,
  68                                 AspmDisabled, 0x05, 0)
  69         }
  70 };
  71
  72 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  73         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  74         .SocketId     = 0,
  75         .PciePortList = PortList,
  76         .DdiLinkList  = NULL,
  77 };
  78
  79 /*---------------------------------------------------------------------------------------*/
  80 /**
  81  *  OemCustomizeInitEarly
  82  *
  83  *  Description:
  84  *    This stub function will call the host environment through the binary block
  85  *    interface (call-out port) to provide a user hook opportunity
  86  *
  87  *  Parameters:
  88  *    @param[in]      *InitEarly
  89  *
  90  *    @retval         VOID
  91  *
  92  **/
  93 /*---------------------------------------------------------------------------------------*/
  94 VOID
  95 OemCustomizeInitEarly (
  96         IN  OUT AMD_EARLY_PARAMS    *InitEarly
  97         )
  98 {
  99         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 100         InitEarly->PlatformConfig.CStateMode = CStateModeC6;
 101         InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
 102 }