src/northbridge/intel/sandybridge/report_platform.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/cpu.h>
  22 #include <string.h>
  23 #include "southbridge/intel/bd82x6x/pch.h"
  24 #include <arch/io.h>
  25 #include <arch/romcc_io.h>
  26 #include "sandybridge.h"
  27
  28 static void report_cpu_info(void)
  29 {
  30         struct cpuid_result cpuidr;
  31         u32 i, index;
  32         char cpu_string[50]; /* 48 bytes are reported */
  33         int vt, txt, aes;
  34         const char *mode[] = {"NOT ", ""};
  35
  36         index = 0x80000000;
  37         cpuidr = cpuid(index);
  38         if (cpuidr.eax < 0x80000004) {
  39                 strcpy(cpu_string, "Platform info not available");
  40         } else {
  41                 u32 *p = (u32*) cpu_string;
  42                 for (i = 2; i <= 4 ; i++) {
  43                         cpuidr = cpuid(index + i);
  44                         *p++ = cpuidr.eax;
  45                         *p++ = cpuidr.ebx;
  46                         *p++ = cpuidr.ecx;
  47                         *p++ = cpuidr.edx;
  48                 }
  49         }
  50         cpuidr = cpuid(1);
  51         printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_string);
  52         aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
  53         txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
  54         vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
  55         printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
  56                mode[aes], mode[txt], mode[vt]);
  57 }
  58
  59 /* The PCI id name match comes from Intel document 472178 */
  60 static struct {
  61         u16 dev_id;
  62         const char *dev_name;
  63 } pch_table [] = {
  64         {0x1E41, "Desktop Sample"},
  65         {0x1E47, "Q77"},
  66         {0x1E48, "Q75"},
  67         {0x1E49, "B75"},
  68         {0x1E44, "Z77"},
  69         {0x1E46, "Z75"},
  70         {0x1E4A, "H77"},
  71         {0x1E53, "C216"},
  72         {0x1E42, "Mobile Sample"},
  73         {0x1E55, "QM77"},
  74         {0x1E58, "UM77"},
  75         {0x1E57, "HM77"},
  76         {0x1E59, "HM76"},
  77         {0x1E5d, "HM75"},
  78         {0x1E43, "SFF Sample"},
  79         {0x1E56, "QS77"},
  80 };
  81
  82 static void report_pch_info(void)
  83 {
  84         int i;
  85         u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
  86
  87
  88         const char *pch_type = "Unknown";
  89         for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
  90                 if (pch_table[i].dev_id == dev_id) {
  91                         pch_type = pch_table[i].dev_name;
  92                         break;
  93                 }
  94         }
  95         printk (BIOS_DEBUG, "PCH type: %s rev id %x\n",
  96                 pch_type, pci_read_config8(PCH_LPC_DEV, 8));
  97 }
  98
  99 void report_platform_info(void)
 100 {
 101         report_cpu_info();
 102         report_pch_info();
 103 }