1 # SPDX-License-Identifier: GPL-2.0-only
10 config CPU_SPECIFIC_OPTIONS
12 select ARCH_BOOTBLOCK_X86_32
13 select ARCH_RAMSTAGE_X86_32
14 select ARCH_ROMSTAGE_X86_32
15 select ARCH_VERSTAGE_X86_32
16 select NO_MMCONF_SUPPORT
18 select PLATFORM_USES_FSP2_0
19 select SOC_INTEL_COMMON
20 select SOC_INTEL_COMMON_RESET
23 select UART_OVERRIDE_REFCLK
25 select TSC_MONOTONIC_TIMER
26 select UNCOMPRESSED_RAMSTAGE
32 # The following options configure the debug serial port
35 config ENABLE_BUILTIN_HSUART0
36 bool "Enable built-in HSUART0"
38 select NO_UART_ON_SUPERIO
39 select DRIVERS_UART_8250MEM_32
41 The Quark SoC has two HSUART. Choose this option to configure the pads
42 and enable HSUART0, which can be used for the debug console.
44 config ENABLE_BUILTIN_HSUART1
45 bool "Enable built-in HSUART1"
47 depends on ! ENABLE_BUILTIN_HSUART0
48 select NO_UART_ON_SUPERIO
49 select DRIVERS_UART_8250MEM_32
51 The Quark SoC has two HSUART. Choose this option to configure the pads
52 and enable HSUART1, which can be used for the debug console.
55 hex "HSUART Base Address"
57 depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
59 Memory mapped MMIO of HSUART.
64 depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
66 # Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
67 # Valid bit, PCI UART in use: 1 << 31
70 default 0x800a1000 if ENABLE_BUILTIN_HSUART0
71 default 0x800a5000 if ENABLE_BUILTIN_HSUART1
72 depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
76 # The following options provide debug support for the Quark coreboot
77 # code. The SD LED is used as a binary marker to determine if a
78 # specific point in the execution flow has been reached.
81 config ENABLE_DEBUG_LED
85 Enable the use of the SD LED for early debugging before serial output
86 is available. Setting this LED indicates that control has reached the
89 config ENABLE_DEBUG_LED_ESRAM
90 bool "SD LED indicates ESRAM initialized"
92 select ENABLE_DEBUG_LED
94 Indicate that ESRAM has been successfully initialized. If the SD LED
95 does not light then the ESRAM initialization needs to be debugged.
97 config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
98 bool "SD LED indicates bootblock.c successfully entered"
100 select ENABLE_DEBUG_LED
102 Indicate that bootblock_c_entry was entered. If the SD LED does not
103 light then debug the code between ESRAM and bootblock_c_entry.
105 config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
106 bool "SD LED indicates bootblock_soc_early_init successfully entered"
108 select ENABLE_DEBUG_LED
110 Indicate that bootblock_soc_early_init was entered. If the SD LED
111 does not light then debug the code in bootblock_main_with_timestamp.
113 config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT
114 bool "SD LED indicates bootblock_soc_early_init successfully exited"
116 select ENABLE_DEBUG_LED
118 Indicate that bootblock_soc_early_init exited. If the SD LED does not
119 light then debug the scripts in bootblock_soc_early_init.
121 config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
122 bool "SD LED indicates bootblock_soc_init successfully entered"
124 select ENABLE_DEBUG_LED
126 Indicate that bootblock_soc_init was entered. If the SD LED does not
127 light then debug the code in bootblock_mainboard_early_init and
128 console_init. If the SD LED does light but there is no serial then
129 debug the serial port configuration and initialization.
133 # Specify the portion of the ESRAM for coreboot to use as its data area.
136 config DCACHE_RAM_BASE
140 config DCACHE_RAM_SIZE
144 config DISPLAY_ESRAM_LAYOUT
145 bool "Display ESRAM layout"
148 Select this option to display coreboot's use of ESRAM.
152 # Specify the size of the coreboot file system in the read-only
153 # (recovery) portion of the flash part.
160 Specify the size of the coreboot file system in the read-only (recovery)
161 portion of the flash part. On Quark systems the firmware image stores
162 more than just coreboot, including:
163 - The chipset microcode (RMU) binary file located at 0xFFF00000
164 - Intel Trusted Execution Engine firmware
168 # The following options control the FSP binary file placement in
169 # the flash image and ESRAM. This file is required by the Quark
170 # SoC code to boot coreboot and its payload.
177 The location in ESRAM where a copy of the FSP binary is placed.
181 default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
185 default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
189 # The following options control the Quark chipset microcode file
190 # placement in the flash image. This file is required to bring
191 # the Quark processor out of reset.
195 bool "Should the RMU binary be added to the flash image?"
198 The RMU file is required to get the chip out of reset.
202 default "3rdparty/blobs/soc/intel/quark/rmu.bin"
203 depends on ADD_RMU_FILE
205 The path and filename of the Intel Quark RMU binary.
210 depends on ADD_RMU_FILE
212 The location in CBFS that the RMU is located. It must match the
213 strap-determined base address.
215 config DCACHE_BSP_STACK_SIZE
219 config C_ENV_BOOTBLOCK_SIZE
228 bool "Test SD/MMC/eMMC card or device access"
230 select COMMONLIB_STORAGE
231 select SDHCI_CONTROLLER
233 Read block 0 from each parition of the storage device. User
234 must also enable one or both of COMMONLIB_STORAGE_SD or
235 COMMONLIB_STORAGE_MMC.
238 bool "Log and display SD/MMC commands"
240 depends on STORAGE_TEST
247 bool "Enable I2C debugging"
250 Display the I2C segments and controller errors
252 endif # SOC_INTEL_QUARK