src/soc/intel/broadwell/ramstage.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <cbmem.h>
   5 #include <device/device.h>
   6 #include <string.h>
   7 #include <soc/nvs.h>
   8 #include <soc/pm.h>
   9 #include <soc/ramstage.h>
  10 #include <soc/intel/broadwell/chip.h>
  11 #include <soc/intel/common/acpi.h>
  12 #include <assert.h>
  13
  14 /* Save wake source information for calculating ACPI _SWS values */
  15 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
  16 {
  17         struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
  18         static uint32_t gpe0_sts[GPE0_REG_MAX];
  19         int i;
  20
  21         assert(ps != NULL);
  22
  23         *pm1 = ps->pm1_sts & ps->pm1_en;
  24
  25         /* Mask off GPE0 status bits that are not enabled */
  26         *gpe0 = &gpe0_sts[0];
  27         for (i = 0; i < GPE0_REG_MAX; i++)
  28                 gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
  29
  30         return GPE0_REG_MAX;
  31 }
  32
  33 static void s3_resume_prepare(void)
  34 {
  35         struct global_nvs *gnvs;
  36
  37         gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
  38         if (gnvs == NULL)
  39                 return;
  40
  41         if (!acpi_is_wakeup_s3())
  42                 memset(gnvs, 0, sizeof(struct global_nvs));
  43 }
  44
  45 void broadwell_init_pre_device(void *chip_info)
  46 {
  47         s3_resume_prepare();
  48         broadwell_run_reference_code();
  49 }