1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pciexp.h>
7 #include <device/pci_def.h>
8 #include <device/pci_ids.h>
9 #include <device/pci_ops.h>
14 #include <soc/pci_devs.h>
16 #include <soc/intel/broadwell/chip.h>
20 /* Low Power variant has 6 root ports. */
21 #define NUM_ROOT_PORTS 6
23 struct root_port_config
{
24 /* RPFN is a write-once register so keep a copy until it is written */
37 struct device
*ports
[NUM_ROOT_PORTS
];
40 static struct root_port_config rpc
;
42 static inline int root_port_is_first(struct device
*dev
)
44 return PCI_FUNC(dev
->path
.pci
.devfn
) == 0;
47 static inline int root_port_is_last(struct device
*dev
)
49 return PCI_FUNC(dev
->path
.pci
.devfn
) == (rpc
.num_ports
- 1);
52 /* Root ports are numbered 1..N in the documentation. */
53 static inline int root_port_number(struct device
*dev
)
55 return PCI_FUNC(dev
->path
.pci
.devfn
) + 1;
58 static void root_port_config_update_gbe_port(void)
60 /* Is the Gbe Port enabled? */
61 if (!((rpc
.strpfusecfg1
>> 19) & 1))
64 switch ((rpc
.strpfusecfg1
>> 16) & 0x7) {
75 /* Lanes 0-4 of Root Port 5. */
79 printk(BIOS_DEBUG
, "Invalid GbE Port Selection.\n");
83 static void pcie_iosf_port_grant_count(struct device
*dev
)
86 u32 rpcd
= (pci_read_config32(dev
, 0xfc) >> 14) & 0x3;
101 RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val
;
104 static void root_port_init_config(struct device
*dev
)
110 if (root_port_is_first(dev
)) {
111 rpc
.orig_rpfn
= RCBA32(RPFN
);
112 rpc
.new_rpfn
= rpc
.orig_rpfn
;
113 rpc
.num_ports
= NUM_ROOT_PORTS
;
115 /* RP0 f5[3:0] = 0101b*/
116 pci_update_config8(dev
, 0xf5, ~0xa, 0x5);
118 pcie_iosf_port_grant_count(dev
);
120 rpc
.pin_ownership
= pci_read_config32(dev
, 0x410);
121 root_port_config_update_gbe_port();
123 pci_update_config8(dev
, 0xe2, ~(3 << 4), (3 << 4));
124 config_t
*config
= config_of(dev
);
125 rpc
.coalesce
= config
->pcie_port_coalesce
;
128 rp
= root_port_number(dev
);
129 if (rp
> rpc
.num_ports
) {
130 printk(BIOS_ERR
, "Found Root Port %d, expecting %d\n",
135 /* Read the fuse configuration and pin ownership. */
138 rpc
.strpfusecfg1
= pci_read_config32(dev
, 0xfc);
139 rpc
.b0d28f0_32c
= pci_read_config32(dev
, 0x32c);
142 rpc
.strpfusecfg2
= pci_read_config32(dev
, 0xfc);
143 rpc
.b0d28f4_32c
= pci_read_config32(dev
, 0x32c);
146 rpc
.b0d28f5_32c
= pci_read_config32(dev
, 0x32c);
147 rpc
.strpfusecfg3
= pci_read_config32(dev
, 0xfc);
153 pci_update_config32(dev
, 0x418, 0, 0x02000430);
155 if (root_port_is_first(dev
)) {
157 * set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1
158 * before configuring ASPM
160 id
= 0xe0 + (u8
)(RCBA32(RPFN
) & 0x07);
161 pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ
, id
, &data
, &resp
);
162 data
|= ((0x30 << 16) | (0x40 << 8));
163 pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE
, id
, &data
, &resp
);
166 /* Cache pci device. */
167 rpc
.ports
[rp
- 1] = dev
;
170 /* Update devicetree with new Root Port function number assignment */
171 static void pch_pcie_device_set_func(int index
, int pci_func
)
174 unsigned int new_devfn
;
176 dev
= rpc
.ports
[index
];
178 /* Set the new PCI function field for this Root Port. */
179 rpc
.new_rpfn
&= ~RPFN_FNMASK(index
);
180 rpc
.new_rpfn
|= RPFN_FNSET(index
, pci_func
);
182 /* Determine the new devfn for this port */
183 new_devfn
= PCI_DEVFN(PCH_DEV_SLOT_PCIE
, pci_func
);
185 if (dev
->path
.pci
.devfn
!= new_devfn
) {
187 "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
188 PCI_SLOT(dev
->path
.pci
.devfn
),
189 PCI_FUNC(dev
->path
.pci
.devfn
),
190 PCI_SLOT(new_devfn
), PCI_FUNC(new_devfn
));
192 dev
->path
.pci
.devfn
= new_devfn
;
196 static void pcie_enable_clock_gating(void)
199 int enabled_ports
= 0;
200 int is_broadwell
= !!(cpu_family_model() == BROADWELL_FAMILY_ULT
);
202 for (i
= 0; i
< rpc
.num_ports
; i
++) {
207 rp
= root_port_number(dev
);
210 /* Configure shared resource clock gating. */
211 if (rp
== 1 || rp
== 5 || rp
== 6)
212 pci_update_config8(dev
, 0xe1, 0xc3, 0x3c);
214 pci_update_config8(dev
, 0xe2, ~(3 << 4), (3 << 4));
215 pci_update_config32(dev
, 0x420, ~(1 << 31), (1 << 31));
217 /* Per-Port CLKREQ# handling. */
218 if (gpio_is_native(18 + rp
- 1))
219 pci_update_config32(dev
, 0x420, ~0, (3 << 29));
221 /* Enable static clock gating. */
222 if (rp
== 1 && !rpc
.ports
[1]->enabled
&&
223 !rpc
.ports
[2]->enabled
&& !rpc
.ports
[3]->enabled
) {
224 pci_update_config8(dev
, 0xe2, ~1, 1);
225 pci_update_config8(dev
, 0xe1, 0x7f, 0x80);
226 } else if (rp
== 5 || rp
== 6) {
227 pci_update_config8(dev
, 0xe2, ~1, 1);
228 pci_update_config8(dev
, 0xe1, 0x7f, 0x80);
235 /* Enable dynamic clock gating. */
236 pci_update_config8(dev
, 0xe1, 0xfc, 0x03);
237 pci_update_config8(dev
, 0xe2, ~(1 << 6), (1 << 6));
238 pci_update_config8(dev
, 0xe8, ~(3 << 2), (2 << 2));
240 /* Update PECR1 register. */
241 pci_update_config8(dev
, 0xe8, ~0, 3);
243 pci_update_config32(dev
, 0x324, ~((1 << 5) | (1 << 14)),
244 ((1 << 5) | (1 << 14)));
246 pci_update_config32(dev
, 0x324, ~(1 << 5), (1 << 5));
248 /* Per-Port CLKREQ# handling. */
249 if (gpio_is_native(18 + rp
- 1))
251 * In addition to D28Fx PCICFG 420h[30:29] = 11b,
252 * set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
254 pci_update_config32(dev
, 0x420, ~0x20000,
257 /* Configure shared resource clock gating. */
258 if (rp
== 1 || rp
== 5 || rp
== 6)
259 pci_update_config8(dev
, 0xe1, 0xc3, 0x3c);
261 /* CLKREQ# VR Idle Enable */
262 RCBA32_OR(0x2b1c, (1 << (16 + i
)));
266 pci_update_config8(rpc
.ports
[0], 0xe1, ~(1 << 6), (1 << 6));
269 static void root_port_commit_config(void)
273 /* If the first root port is disabled the coalesce ports. */
274 if (!rpc
.ports
[0]->enabled
)
277 /* Perform clock gating configuration. */
278 pcie_enable_clock_gating();
280 for (i
= 0; i
< rpc
.num_ports
; i
++) {
288 printk(BIOS_ERR
, "Root Port %d device is NULL?\n", i
+1);
295 printk(BIOS_DEBUG
, "%s: Disabling device\n", dev_path(dev
));
297 /* 8.2 Configuration of PCI Express Root Ports */
298 pci_update_config32(dev
, 0x338, ~(1 << 26), 1 << 26);
301 reg32
= pci_read_config32(dev
, 0x328);
303 if (((reg32
& 0xff000000) == 0x01000000) || (n
> 50))
309 printk(BIOS_DEBUG
, "%s: Timeout waiting for 328h\n",
312 pci_update_config32(dev
, 0x408, ~(1 << 27), 1 << 27);
314 /* Disable this device if possible */
315 pch_disable_devfn(dev
);
321 /* For all Root Ports N enabled ports get assigned the lower
322 * PCI function number. The disabled ones get upper PCI
323 * function numbers. */
325 for (i
= 0; i
< rpc
.num_ports
; i
++) {
326 if (!rpc
.ports
[i
]->enabled
)
328 pch_pcie_device_set_func(i
, current_func
);
332 /* Allocate the disabled devices' PCI function number. */
333 for (i
= 0; i
< rpc
.num_ports
; i
++) {
334 if (rpc
.ports
[i
]->enabled
)
336 pch_pcie_device_set_func(i
, current_func
);
341 printk(BIOS_SPEW
, "PCH: RPFN 0x%08x -> 0x%08x\n",
342 rpc
.orig_rpfn
, rpc
.new_rpfn
);
343 RCBA32(RPFN
) = rpc
.new_rpfn
;
346 static void root_port_mark_disable(struct device
*dev
)
348 /* Mark device as disabled. */
350 /* Mark device to be hidden. */
351 rpc
.new_rpfn
|= RPFN_HIDE(PCI_FUNC(dev
->path
.pci
.devfn
));
354 static void root_port_check_disable(struct device
*dev
)
358 /* Device already disabled. */
360 root_port_mark_disable(dev
);
364 rp
= root_port_number(dev
);
366 /* Is the GbE port mapped to this Root Port? */
367 if (rp
== rpc
.gbe_port
) {
368 root_port_mark_disable(dev
);
372 /* Check Root Port Configuration. */
375 /* Root Port 2 is disabled for all lane configurations
376 * but config 00b (4x1 links). */
377 if ((rpc
.strpfusecfg1
>> 14) & 0x3) {
378 root_port_mark_disable(dev
);
383 /* Root Port 3 is disabled in config 11b (1x4 links). */
384 if (((rpc
.strpfusecfg1
>> 14) & 0x3) == 0x3) {
385 root_port_mark_disable(dev
);
390 /* Root Port 4 is disabled in configs 11b (1x4 links)
391 * and 10b (2x2 links). */
392 if ((rpc
.strpfusecfg1
>> 14) & 0x2) {
393 root_port_mark_disable(dev
);
399 /* Check Pin Ownership. */
402 /* Bit 0 is Root Port 1 ownership. */
403 if ((rpc
.pin_ownership
& 0x1) == 0) {
404 root_port_mark_disable(dev
);
409 /* Bit 2 is Root Port 2 ownership. */
410 if ((rpc
.pin_ownership
& 0x4) == 0) {
411 root_port_mark_disable(dev
);
416 /* Bits 7:4 are Root Port 6 pin-lane ownership. */
417 if ((rpc
.pin_ownership
& 0xf0) == 0) {
418 root_port_mark_disable(dev
);
425 static void pcie_add_0x0202000_iobp(u32 reg
)
429 reg32
= pch_iobp_read(reg
);
430 reg32
+= (0x2 << 16) | (0x2 << 8);
431 pch_iobp_write(reg
, reg32
);
434 static void pch_pcie_early(struct device
*dev
)
436 config_t
*config
= config_of(dev
);
438 int rp
= root_port_number(dev
);
446 * Bits 31:28 of b0d28f0 0x32c register correspond to
449 do_aspm
= !!(rpc
.b0d28f0_32c
& (1 << (28 + rp
- 1)));
453 * Bit 28 of b0d28f4 0x32c register correspond to
456 do_aspm
= !!(rpc
.b0d28f4_32c
& (1 << 28));
460 * Bit 28 of b0d28f5 0x32c register correspond to
463 do_aspm
= !!(rpc
.b0d28f5_32c
& (1 << 28));
467 /* Allow ASPM to be forced on in devicetree */
468 if ((config
->pcie_port_force_aspm
& (1 << (rp
- 1))))
471 printk(BIOS_DEBUG
, "PCIe Root Port %d ASPM is %sabled\n",
472 rp
, do_aspm
? "en" : "dis");
475 /* Set ASPM bits in MPC2 register. */
476 pci_update_config32(dev
, 0xd4, ~(0x3 << 2),
477 (1 << 4) | (0x2 << 2));
479 /* Set unique clock exit latency in MPC register. */
480 pci_update_config32(dev
, 0xd8, ~(0x7 << 18), (0x7 << 18));
484 pcie_add_0x0202000_iobp(0xe9002440);
487 pcie_add_0x0202000_iobp(0xe9002640);
490 pcie_add_0x0202000_iobp(0xe9000840);
493 pcie_add_0x0202000_iobp(0xe9000a40);
496 pcie_add_0x0202000_iobp(0xe9000c40);
497 pcie_add_0x0202000_iobp(0xe9000e40);
498 pcie_add_0x0202000_iobp(0xe9001040);
499 pcie_add_0x0202000_iobp(0xe9001240);
502 /* Update IOBP based on lane ownership. */
503 if (rpc
.pin_ownership
& (1 << 4))
504 pcie_add_0x0202000_iobp(0xea002040);
505 if (rpc
.pin_ownership
& (1 << 5))
506 pcie_add_0x0202000_iobp(0xea002240);
507 if (rpc
.pin_ownership
& (1 << 6))
508 pcie_add_0x0202000_iobp(0xea002440);
509 if (rpc
.pin_ownership
& (1 << 7))
510 pcie_add_0x0202000_iobp(0xea002640);
514 pci_update_config32(dev
, 0x338, ~(1 << 26), 0);
517 /* Enable LTR in Root Port. Disable OBFF. */
518 pci_update_config32(dev
, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
519 pci_update_config32(dev
, 0x68, ~(1 << 10), (1 << 10));
521 pci_update_config32(dev
, 0x318, ~(0xffff << 16), (0x1414 << 16));
523 /* Set L1 exit latency in LCAP register. */
524 if (!do_aspm
&& (pci_read_config8(dev
, 0xf5) & 0x1))
525 pci_update_config32(dev
, 0x4c, ~(0x7 << 15), (0x4 << 15));
527 pci_update_config32(dev
, 0x4c, ~(0x7 << 15), (0x2 << 15));
529 pci_update_config32(dev
, 0x314, 0x0, 0x743a361b);
531 /* Set Common Clock Exit Latency in MPC register. */
532 pci_update_config32(dev
, 0xd8, ~(0x7 << 15), (0x3 << 15));
534 pci_update_config32(dev
, 0x33c, ~0x00ffffff, 0x854d74);
536 /* Set Invalid Receive Range Check Enable in MPC register. */
537 pci_update_config32(dev
, 0xd8, ~0, (1 << 25));
539 pci_update_config8(dev
, 0xf5, 0x0f, 0);
541 /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
542 if (CONFIG(PCIEXP_AER
))
543 pci_update_config32(dev
, 0x100, ~(1 << 29) & ~0xfffff,
544 (1 << 29) | 0x10001);
546 pci_update_config32(dev
, 0x100, ~(1 << 29) & ~0xfffff,
549 /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
550 if (CONFIG(PCIEXP_L1_SUB_STATE
))
551 pci_update_config32(dev
, 0x200, ~0xfffff, 0x001e);
553 pci_update_config32(dev
, 0x200, ~0xfffff, 0);
555 pci_update_config32(dev
, 0x320, ~(3 << 20) & ~(7 << 6),
556 (1 << 20) | (3 << 6));
557 /* Enable Relaxed Order from Root Port. */
558 pci_update_config32(dev
, 0x320, ~(3 << 23), (3 << 23));
560 if (rp
== 1 || rp
== 5 || rp
== 6)
561 pci_update_config8(dev
, 0xf7, ~0xc, 0);
563 /* Set EOI forwarding disable. */
564 pci_update_config32(dev
, 0xd4, ~0, (1 << 1));
566 /* Read and write back write-once capability registers. */
567 pci_update_config32(dev
, 0x34, ~0, 0);
568 pci_update_config32(dev
, 0x40, ~0, 0);
569 pci_update_config32(dev
, 0x80, ~0, 0);
570 pci_update_config32(dev
, 0x90, ~0, 0);
573 static void pch_pcie_init(struct device
*dev
)
577 printk(BIOS_DEBUG
, "Initializing PCH PCIe bridge.\n");
580 pci_or_config16(dev
, PCI_COMMAND
, PCI_COMMAND_SERR
);
582 /* Enable Bus Master */
583 pci_or_config16(dev
, PCI_COMMAND
, PCI_COMMAND_MASTER
);
585 /* Set Cache Line Size to 0x10 */
586 pci_write_config8(dev
, 0x0c, 0x10);
588 reg16
= pci_read_config16(dev
, PCI_BRIDGE_CONTROL
);
589 reg16
&= ~PCI_BRIDGE_CTL_PARITY
;
590 pci_write_config16(dev
, PCI_BRIDGE_CONTROL
, reg16
);
592 /* Clear errors in status registers */
593 reg16
= pci_read_config16(dev
, 0x06);
594 pci_write_config16(dev
, 0x06, reg16
);
595 reg16
= pci_read_config16(dev
, 0x1e);
596 pci_write_config16(dev
, 0x1e, reg16
);
599 static void pch_pcie_enable(struct device
*dev
)
601 /* Add this device to the root port config structure. */
602 root_port_init_config(dev
);
604 /* Check to see if this Root Port should be disabled. */
605 root_port_check_disable(dev
);
607 /* Power Management init before enumeration */
612 * When processing the last PCIe root port we can now
613 * update the Root Port Function Number and Hide register.
615 if (root_port_is_last(dev
))
616 root_port_commit_config();
619 static void pcie_set_L1_ss_max_latency(struct device
*dev
, unsigned int off
)
621 /* Set max snoop and non-snoop latency for Broadwell */
622 pci_write_config32(dev
, off
,
623 PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US
<< 16 |
624 PCIE_LTR_MAX_SNOOP_LATENCY_3146US
);
627 static struct pci_operations pcie_ops
= {
628 .set_subsystem
= pci_dev_set_subsystem
,
629 .set_L1_ss_latency
= pcie_set_L1_ss_max_latency
,
632 static struct device_operations device_ops
= {
633 .read_resources
= pci_bus_read_resources
,
634 .set_resources
= pci_dev_set_resources
,
635 .enable_resources
= pci_bus_enable_resources
,
636 .init
= pch_pcie_init
,
637 .enable
= pch_pcie_enable
,
638 .scan_bus
= pciexp_scan_bridge
,
639 .ops_pci
= &pcie_ops
,
642 static const unsigned short pcie_device_ids
[] = {
644 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
646 0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448,
650 static const struct pci_driver pch_pcie __pci_driver
= {
652 .vendor
= PCI_VENDOR_ID_INTEL
,
653 .devices
= pcie_device_ids
,