src/soc/intel/broadwell/igd.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <device/mmio.h>
   5 #include <device/pci_ops.h>
   6 #include <bootmode.h>
   7 #include <console/console.h>
   8 #include <delay.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pci_ids.h>
  12 #include <string.h>
  13 #include <reg_script.h>
  14 #include <drivers/intel/gma/i915.h>
  15 #include <drivers/intel/gma/i915_reg.h>
  16 #include <drivers/intel/gma/libgfxinit.h>
  17 #include <drivers/intel/gma/opregion.h>
  18 #include <soc/cpu.h>
  19 #include <soc/pm.h>
  20 #include <soc/ramstage.h>
  21 #include <soc/systemagent.h>
  22 #include <soc/intel/broadwell/chip.h>
  23 #include <security/vboot/vbnv.h>
  24 #include <soc/igd.h>
  25 #include <types.h>
  26
  27 #define GT_RETRY                1000
  28 enum {
  29         GT_CDCLK_DEFAULT = 0,
  30         GT_CDCLK_337,
  31         GT_CDCLK_450,
  32         GT_CDCLK_540,
  33         GT_CDCLK_675,
  34 };
  35
  36 static u32 reg_em4;
  37 static u32 reg_em5;
  38
  39 u32 igd_get_reg_em4(void) { return reg_em4; }
  40 u32 igd_get_reg_em5(void) { return reg_em5; }
  41
  42 struct reg_script haswell_early_init_script[] = {
  43         /* Enable Force Wake */
  44         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020),
  45         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
  46         REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
  47
  48         /* Enable Counters */
  49         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016),
  50
  51         /* GFXPAUSE settings */
  52         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020),
  53
  54         /* ECO Settings */
  55         REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000),
  56
  57         /* Enable DOP Clock Gating */
  58         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),
  59
  60         /* Enable Unit Level Clock Gating */
  61         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
  62         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
  63         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
  64         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
  65
  66         /*
  67          * RC6 Settings
  68          */
  69
  70         /* Wake Rate Limits */
  71         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000),
  72         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000),
  73         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000),
  74         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848),
  75         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019),
  76
  77         /* Render/Video/Blitter Idle Max Count */
  78         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
  79         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
  80         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
  81         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
  82
  83         /* RC Sleep / RCx Thresholds */
  84         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000),
  85         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8),
  86         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350),
  87
  88         /* RP Settings */
  89         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240),
  90         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000),
  91         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808),
  92         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08),
  93         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0),
  94         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730),
  95         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
  96
  97         /* RP Control */
  98         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
  99
 100         /* HW RC6 Control */
 101         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000),
 102
 103         /* Video Frequency Request */
 104         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
 105
 106         /* Set RC6 VIDs */
 107         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
 108         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
 109         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
 110         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
 111
 112         /* Enable PM Interrupts */
 113         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
 114
 115         /* Enable RC6 in idle */
 116         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
 117
 118         REG_SCRIPT_END
 119 };
 120
 121 static const struct reg_script haswell_late_init_script[] = {
 122         /* Lock settings */
 123         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
 124         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)),
 125         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)),
 126         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
 127
 128         /* Disable Force Wake */
 129         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
 130         REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
 131         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001),
 132
 133         /* Enable power well for DP and Audio */
 134         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
 135         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
 136                        (1 << 30), (1 << 30), GT_RETRY),
 137
 138         REG_SCRIPT_END
 139 };
 140
 141 static const struct reg_script broadwell_early_init_script[] = {
 142         /* Enable Force Wake */
 143         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001),
 144         REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY),
 145
 146         /* Enable push bus metric control and shift */
 147         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004),
 148         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
 149         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
 150
 151         /* GFXPAUSE settings (set based on stepping) */
 152
 153         /* ECO Settings */
 154         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
 155
 156         /* Enable DOP Clock Gating */
 157         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd),
 158
 159         /* Enable Unit Level Clock Gating */
 160         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000),
 161         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000),
 162         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000),
 163         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001),
 164         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a),
 165
 166         /* Video Frequency Request */
 167         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
 168
 169         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009),
 170         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d),
 171
 172         /*
 173          * RC6 Settings
 174          */
 175
 176         /* Wake Rate Limits */
 177         REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0),
 178         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000),
 179         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000),
 180         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848),
 181         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019),
 182
 183         /* Render/Video/Blitter Idle Max Count */
 184         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a),
 185         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a),
 186         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a),
 187
 188         /* RC Sleep / RCx Thresholds */
 189         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000),
 190         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271),
 191
 192         /* RP Settings */
 193         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240),
 194         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000),
 195         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808),
 196         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08),
 197         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0),
 198         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730),
 199         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a),
 200         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006),
 201
 202         /* RP Control */
 203         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92),
 204
 205         /* HW RC6 Control */
 206         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000),
 207
 208         /* Set RC6 VIDs */
 209         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
 210         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0),
 211         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004),
 212         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY),
 213
 214         /* Enable PM Interrupts */
 215         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
 216
 217         /* Enable RC6 in idle */
 218         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000),
 219
 220         REG_SCRIPT_END
 221 };
 222
 223 static const struct reg_script broadwell_late_init_script[] = {
 224         /* Lock settings */
 225         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)),
 226         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)),
 227         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)),
 228
 229         /* Disable Force Wake */
 230         REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000),
 231         REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY),
 232
 233         /* Enable power well for DP and Audio */
 234         REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)),
 235         REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400,
 236                        (1 << 30), (1 << 30), GT_RETRY),
 237
 238         REG_SCRIPT_END
 239 };
 240
 241 u32 map_oprom_vendev(u32 vendev)
 242 {
 243         return SA_IGD_OPROM_VENDEV;
 244 }
 245
 246 static struct resource *gtt_res = NULL;
 247
 248 u32 gtt_read(u32 reg)
 249 {
 250         u32 val;
 251         val = read32(res2mmio(gtt_res, reg, 0));
 252         return val;
 253
 254 }
 255
 256 void gtt_write(u32 reg, u32 data)
 257 {
 258         write32(res2mmio(gtt_res, reg, 0), data);
 259 }
 260
 261 static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
 262 {
 263         u32 val = gtt_read(reg);
 264         val &= andmask;
 265         val |= ormask;
 266         gtt_write(reg, val);
 267 }
 268
 269 int gtt_poll(u32 reg, u32 mask, u32 value)
 270 {       unsigned int try = GT_RETRY;
 271         u32 data;
 272
 273         while (try--) {
 274                 data = gtt_read(reg);
 275                 if ((data & mask) == value)
 276                         return 1;
 277                 udelay(10);
 278         }
 279
 280         printk(BIOS_ERR, "GT init timeout\n");
 281         return 0;
 282 }
 283
 284 static void igd_setup_panel(struct device *dev)
 285 {
 286         config_t *conf = config_of(dev);
 287         u32 reg32;
 288
 289         /* Setup Digital Port Hotplug */
 290         reg32 = gtt_read(PCH_PORT_HOTPLUG);
 291         if (!reg32) {
 292                 reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
 293                 reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
 294                 reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
 295                 gtt_write(PCH_PORT_HOTPLUG, reg32);
 296         }
 297
 298         /* Setup Panel Power On Delays */
 299         reg32 = gtt_read(PCH_PP_ON_DELAYS);
 300         if (!reg32) {
 301                 reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
 302                 reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
 303                 gtt_write(PCH_PP_ON_DELAYS, reg32);
 304         }
 305
 306         /* Setup Panel Power Off Delays */
 307         reg32 = gtt_read(PCH_PP_OFF_DELAYS);
 308         if (!reg32) {
 309                 reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
 310                 reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
 311                 gtt_write(PCH_PP_OFF_DELAYS, reg32);
 312         }
 313
 314         /* Setup Panel Power Cycle Delay */
 315         if (conf->gpu_panel_power_cycle_delay) {
 316                 reg32 = gtt_read(PCH_PP_DIVISOR);
 317                 reg32 &= ~0xff;
 318                 reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
 319                 gtt_write(PCH_PP_DIVISOR, reg32);
 320         }
 321
 322         /* So far all devices seem to use the PCH PWM function.
 323            The CPU PWM registers are all zero after reset.      */
 324         if (conf->gpu_pch_backlight_pwm_hz) {
 325                 /* For Lynx Point-LP:
 326                    Reference clock is 24MHz. We can choose either a 16
 327                    or a 128 step increment. Use 16 if we would have less
 328                    than 100 steps otherwise. */
 329                 const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
 330                 unsigned int pwm_increment, pwm_period;
 331                 u32 south_chicken2;
 332
 333                 south_chicken2 = gtt_read(SOUTH_CHICKEN2);
 334                 if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
 335                         pwm_increment = 16;
 336                         south_chicken2 |= 1 << 5;
 337                 } else {
 338                         pwm_increment = 128;
 339                         south_chicken2 &= ~(1 << 5);
 340                 }
 341                 gtt_write(SOUTH_CHICKEN2, south_chicken2);
 342
 343                 pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
 344                 /* Start with a 50% duty cycle. */
 345                 gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
 346
 347                 gtt_write(BLC_PWM_PCH_CTL1,
 348                         (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
 349                         BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
 350         }
 351 }
 352
 353 static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
 354                                  struct device *const dev)
 355 {
 356         const config_t *const conf = config_of(dev);
 357         int cdclk = conf->cdclk;
 358
 359         /* Check for ULX GT1 or GT2 */
 360         const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
 361         const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
 362                                 devid == IGD_HASWELL_ULX_GT2;
 363
 364         /* Check for fixed fused clock */
 365         if (gtt_read(0x42014) & 1 << 24)
 366                 cdclk = GT_CDCLK_450;
 367
 368         /*
 369          *    ULX defaults to 337MHz with possible override for 450MHz
 370          *    ULT is fixed at 450MHz
 371          * others default  to 540MHz with possible override for 450MHz
 372          */
 373         if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
 374                 cdclk = GT_CDCLK_337;
 375         else if (gpu_is_ulx || cpu_is_ult() ||
 376                         cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
 377                 cdclk = GT_CDCLK_450;
 378         else
 379                 cdclk = GT_CDCLK_540;
 380
 381         *cdsel = cdclk != GT_CDCLK_450;
 382         *inform_pc = gpu_is_ulx;
 383         return cdclk;
 384 }
 385
 386 static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
 387                                    struct device *const dev)
 388 {
 389         static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
 390         const config_t *const conf = config_of(dev);
 391         int cdclk = conf->cdclk;
 392
 393         /* Check for ULX */
 394         const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
 395         const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
 396
 397         /* Inform power controller of upcoming frequency change */
 398         gtt_write(0x138128, 0);
 399         gtt_write(0x13812c, 0);
 400         gtt_write(0x138124, 0x80000018);
 401
 402         /* Poll GT driver mailbox for run/busy clear */
 403         if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
 404                 *inform_pc = 1;
 405         } else {
 406                 cdclk = GT_CDCLK_450;
 407                 *inform_pc = 0;
 408         }
 409
 410         /* Check for fixed fused clock */
 411         if (gtt_read(0x42014) & 1 << 24)
 412                 cdclk = GT_CDCLK_450;
 413
 414         /*
 415          *    ULX defaults to 450MHz with possible override up to 540MHz
 416          *    ULT defaults to 540MHz with possible override up to 675MHz
 417          * others default  to 675MHz with possible override for lower freqs
 418          */
 419         if (cdclk == GT_CDCLK_337)
 420                 cdclk = GT_CDCLK_337;
 421         else if (cdclk == GT_CDCLK_450 ||
 422                         (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
 423                 cdclk = GT_CDCLK_450;
 424         else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
 425                         (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT))
 426                 cdclk = GT_CDCLK_540;
 427         else
 428                 cdclk = GT_CDCLK_675;
 429
 430         *cdsel = cdsel_by_cdclk[cdclk];
 431         return cdclk;
 432 }
 433
 434 static void igd_cdclk_init(struct device *dev, const int is_broadwell)
 435 {
 436         u32 dpdiv, cdsel, cdval;
 437         int cdclk, inform_pc;
 438
 439         if (is_broadwell)
 440                 cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev);
 441         else
 442                 cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev);
 443
 444         /* Set variables based on CD Clock setting */
 445         switch (cdclk) {
 446         case GT_CDCLK_337:
 447                 cdval = 337;
 448                 dpdiv = 169;
 449                 reg_em4 = 16;
 450                 reg_em5 = 225;
 451                 break;
 452         case GT_CDCLK_450:
 453                 cdval = 449;
 454                 dpdiv = 225;
 455                 reg_em4 = 4;
 456                 reg_em5 = 75;
 457                 break;
 458         case GT_CDCLK_540:
 459                 cdval = 539;
 460                 dpdiv = 270;
 461                 reg_em4 = 4;
 462                 reg_em5 = 90;
 463                 break;
 464         case GT_CDCLK_675:
 465                 cdval = 674;
 466                 dpdiv = 338;
 467                 reg_em4 = 8;
 468                 reg_em5 = 225;
 469         default:
 470                 return;
 471         }
 472
 473         /* Set LPCLL_CTL CD Clock Frequency Select */
 474         gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26);
 475
 476         if (inform_pc) {
 477                 /* Inform power controller of selected frequency */
 478                 gtt_write(0x138128, cdsel);
 479                 gtt_write(0x13812c, 0);
 480                 gtt_write(0x138124, 0x80000017);
 481         }
 482
 483         /* Program CD Clock Frequency */
 484         gtt_rmw(0x46200, 0xfffffc00, cdval);
 485
 486         /* Set CPU DP AUX 2X bit clock dividers */
 487         gtt_rmw(0x64010, 0xfffff800, dpdiv);
 488         gtt_rmw(0x64810, 0xfffff800, dpdiv);
 489 }
 490
 491 static void igd_init(struct device *dev)
 492 {
 493         int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 494         u32 rp1_gfx_freq;
 495
 496         intel_gma_init_igd_opregion();
 497
 498         gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 499         if (!gtt_res || !gtt_res->base)
 500                 return;
 501
 502         if (!CONFIG(NO_GFX_INIT))
 503                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 504
 505         /* Wait for any configured pre-graphics delay */
 506         if (!acpi_is_wakeup_s3()) {
 507 #if CONFIG(CHROMEOS)
 508                 if (display_init_required())
 509                         mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 510 #else
 511                 mdelay(CONFIG_PRE_GRAPHICS_DELAY);
 512 #endif
 513         }
 514
 515         /* Early init steps */
 516         if (is_broadwell) {
 517                 reg_script_run_on_dev(dev, broadwell_early_init_script);
 518
 519                 /* Set GFXPAUSE based on stepping */
 520                 if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
 521                     systemagent_revision() <= 9) {
 522                         gtt_write(0xa000, 0x300ff);
 523                 } else {
 524                         gtt_write(0xa000, 0x30020);
 525                 }
 526         } else {
 527                 reg_script_run_on_dev(dev, haswell_early_init_script);
 528         }
 529
 530         /* Set RP1 graphics frequency */
 531         rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff;
 532         gtt_write(0xa008, rp1_gfx_freq << 24);
 533
 534         /* Post VBIOS panel setup */
 535         igd_setup_panel(dev);
 536
 537         /* Initialize PCI device, load/execute BIOS Option ROM */
 538         pci_dev_init(dev);
 539
 540         /* Late init steps */
 541         igd_cdclk_init(dev, is_broadwell);
 542         if (is_broadwell)
 543                 reg_script_run_on_dev(dev, broadwell_late_init_script);
 544         else
 545                 reg_script_run_on_dev(dev, haswell_late_init_script);
 546
 547         if (gfx_get_init_done()) {
 548                 /*
 549                  * Work around VBIOS issue that is not clearing first 64
 550                  * bytes of the framebuffer during VBE mode set.
 551                  */
 552                 struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2);
 553                 memset((void *)((u32)fb->base), 0, 64);
 554         }
 555
 556         if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
 557                 /*
 558                  * Enable DDI-A if the Option ROM did not execute:
 559                  *
 560                  * bit 0: Display detected (RO)
 561                  * bit 4: DDI A supports 4 lanes and DDI E is not used
 562                  * bit 7: DDI buffer is idle
 563                  */
 564                 gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
 565                           DDI_INIT_DISPLAY_DETECTED);
 566         }
 567
 568         if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 569                 int lightup_ok;
 570                 gma_gfxinit(&lightup_ok);
 571                 gfx_set_init_done(lightup_ok);
 572         }
 573 }
 574
 575 static void gma_generate_ssdt(const struct device *dev)
 576 {
 577         const struct soc_intel_broadwell_config *chip = dev->chip_info;
 578
 579         drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
 580 }
 581
 582 static struct device_operations igd_ops = {
 583         .read_resources         = &pci_dev_read_resources,
 584         .set_resources          = &pci_dev_set_resources,
 585         .enable_resources       = &pci_dev_enable_resources,
 586         .init                   = &igd_init,
 587         .ops_pci                = &broadwell_pci_ops,
 588         .acpi_fill_ssdt         = gma_generate_ssdt,
 589 };
 590
 591 static const unsigned short pci_device_ids[] = {
 592         IGD_HASWELL_ULT_GT1,
 593         IGD_HASWELL_ULT_GT2,
 594         IGD_HASWELL_ULT_GT3,
 595         IGD_BROADWELL_U_GT1,
 596         IGD_BROADWELL_U_GT2,
 597         IGD_BROADWELL_U_GT3_15W,
 598         IGD_BROADWELL_U_GT3_28W,
 599         IGD_BROADWELL_Y_GT2,
 600         IGD_BROADWELL_H_GT2,
 601         IGD_BROADWELL_H_GT3,
 602         0,
 603 };
 604
 605 static const struct pci_driver igd_driver __pci_driver = {
 606         .ops     = &igd_ops,
 607         .vendor  = PCI_VENDOR_ID_INTEL,
 608         .devices = pci_device_ids,
 609 };