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soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros
[coreboot.git] / src / soc / rockchip / common / edp.c
blob422b306a1430fcd1c21228db8412e1bb7548fb94
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <device/device.h>
7 #include <edid.h>
8 #include <string.h>
9 #include <soc/addressmap.h>
10 #include <soc/display.h>
11 #include <soc/edp.h>
12 #include <timer.h>
13 #include <types.h>
14
15 #define edp_debug(x...) do {if (0) printk(BIOS_DEBUG, x); } while (0)
16
17 static struct rk_edp rk_edp;
18
19 #define MAX_CR_LOOP 5
20 #define MAX_EQ_LOOP 5
21 #define DP_LINK_STATUS_SIZE 6
22
23 static const char *voltage_names[] = {
24 "0.4V", "0.6V", "0.8V", "1.2V"
25 };
26 static const char *pre_emph_names[] = {
27 "0dB", "3.5dB", "6dB", "9.5dB"
28 };
29
30 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
31 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
32
33 static void rk_edp_init_refclk(struct rk_edp *edp)
34 {
35 write32(&edp->regs->analog_ctl_2, SEL_24M);
36 write32(&edp->regs->pll_reg_1, REF_CLK_24M);
37
38 /*initial value*/
39 write32(&edp->regs->pll_reg_2, LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT |
40 CHG_PUMP_CUR_SEL_5US | V2L_CUR_SEL_1MA);
41
42 write32(&edp->regs->pll_reg_3, LOCK_DET_CNT_SEL_256 |
43 LOOP_FILTER_RESET | PALL_SSC_RESET | LOCK_DET_BYPASS |
44 PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE);
45
46 write32(&edp->regs->pll_reg_5, REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
47 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP);
48
49 write32(&edp->regs->ssc_reg, SSC_OFFSET | SSC_MODE | SSC_DEPTH);
50
51 write32(&edp->regs->tx_common, TX_SWING_PRE_EMP_MODE |
52 PRE_DRIVER_PW_CTRL1 | LP_MODE_CLK_REGULATOR |
53 RESISTOR_MSB_CTRL | RESISTOR_CTRL);
54
55 write32(&edp->regs->dp_aux, DP_AUX_COMMON_MODE |
56 DP_AUX_EN | AUX_TERM_50OHM);
57
58 write32(&edp->regs->dp_bias, DP_BG_OUT_SEL | DP_DB_CUR_CTRL |
59 DP_BG_SEL | DP_RESISTOR_TUNE_BG);
60
61 write32(&edp->regs->dp_reserv2,
62 CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL);
63 }
64
65 static void rk_edp_init_interrupt(struct rk_edp *edp)
66 {
67 /* Set interrupt pin assertion polarity as high */
68 write32(&edp->regs->int_ctl, INT_POL);
69
70 /* Clear pending registers */
71 write32(&edp->regs->common_int_sta_1, 0xff);
72 write32(&edp->regs->common_int_sta_2, 0x4f);
73 write32(&edp->regs->common_int_sta_3, 0xff);
74 write32(&edp->regs->common_int_sta_4, 0x27);
75 write32(&edp->regs->dp_int_sta, 0x7f);
76
77 /* 0:mask,1: unmask */
78 write32(&edp->regs->common_int_mask_1, 0x00);
79 write32(&edp->regs->common_int_mask_2, 0x00);
80 write32(&edp->regs->common_int_mask_3, 0x00);
81 write32(&edp->regs->common_int_mask_4, 0x00);
82 write32(&edp->regs->int_sta_mask, 0x00);
83 }
84
85 static void rk_edp_enable_sw_function(struct rk_edp *edp)
86 {
87 clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N);
88 }
89
90 static int rk_edp_get_pll_lock_status(struct rk_edp *edp)
91 {
92 u32 val;
93
94 val = read32(&edp->regs->dp_debug_ctl);
95 return (val & PLL_LOCK) ? DP_PLL_LOCKED : DP_PLL_UNLOCKED;
96 }
97
98 static void rk_edp_init_analog_func(struct rk_edp *edp)
99 {
100 struct stopwatch sw;
101
102 write32(&edp->regs->dp_pd, 0x00);
103
104 write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG);
105
106 clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
107
108 stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT);
109
110 while (rk_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
111 if (stopwatch_expired(&sw)) {
112 printk(BIOS_ERR, "%s: PLL is not locked\n", __func__);
113 return;
114 }
115 }
116
117 /* Enable Serdes FIFO function and Link symbol clock domain module */
118 clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
119 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
120 SSC_FUNC_EN_N);
121 }
122
123 static void rk_edp_init_aux(struct rk_edp *edp)
124 {
125 /* Clear interrupts related to AUX channel */
126 write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
127
128 /* Disable AUX channel module */
129 setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
130
131 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
132 write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1));
133
134 /* Enable AUX channel module */
135 clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
136 }
137
138 static int rk_edp_aux_enable(struct rk_edp *edp)
139 {
140 struct stopwatch sw;
141
142 setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN);
143 stopwatch_init_msecs_expire(&sw, 20);
144 do {
145 if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN))
146 return 0;
147 } while (!stopwatch_expired(&sw));
148
149 return -1;
150
151 }
152
153 static int rk_edp_is_aux_reply(struct rk_edp *edp)
154 {
155 struct stopwatch sw;
156
157 stopwatch_init_msecs_expire(&sw, 10);
158
159 while (!(read32(&edp->regs->dp_int_sta) & RPLY_RECEIV)) {
160 if (stopwatch_expired(&sw))
161 return -1;
162 }
163
164 write32(&edp->regs->dp_int_sta, RPLY_RECEIV);
165
166 return 0;
167 }
168
169 static int rk_edp_start_aux_transaction(struct rk_edp *edp)
170 {
171 int val;
172
173 /* Enable AUX CH operation */
174 if (rk_edp_aux_enable(edp)) {
175 edp_debug("AUX CH enable timeout!\n");
176 return -1;
177 }
178
179 /* Is AUX CH command reply received? */
180 if (rk_edp_is_aux_reply(edp)) {
181 edp_debug("AUX CH command reply failed!\n");
182 return -1;
183 }
184
185 /* Clear interrupt source for AUX CH access error */
186 val = read32(&edp->regs->dp_int_sta);
187 if (val & AUX_ERR) {
188 write32(&edp->regs->dp_int_sta, AUX_ERR);
189 return -1;
190 }
191
192 /* Check AUX CH error access status */
193 val = read32(&edp->regs->dp_int_sta);
194 if ((val & AUX_STATUS_MASK) != 0) {
195 edp_debug("AUX CH error happens: %d\n\n",
196 val & AUX_STATUS_MASK);
197 return -1;
198 }
199
200 return 0;
201 }
202
203 static int rk_edp_dpcd_transfer(struct rk_edp *edp,
204 unsigned int val_addr, u8 *data,
205 unsigned int length,
206 enum dpcd_request request)
207 {
208 int val;
209 int i, try_times;
210 int retval = 0;
211 u32 len = 0;
212
213 while (length) {
214 len = MIN(length, 16);
215 for (try_times = 0; try_times < 10; try_times++) {
216
217 /* Clear AUX CH data buffer */
218 val = BUF_CLR;
219 write32(&edp->regs->buf_data_ctl, val);
220
221 /* Select DPCD device address */
222 val = AUX_ADDR_7_0(val_addr);
223 write32(&edp->regs->aux_addr_7_0, val);
224 val = AUX_ADDR_15_8(val_addr);
225 write32(&edp->regs->aux_addr_15_8, val);
226 val = AUX_ADDR_19_16(val_addr);
227 write32(&edp->regs->aux_addr_19_16, val);
228
229 /*
230 * Set DisplayPort transaction and read 1 byte
231 * If bit 3 is 1, DisplayPort transaction.
232 * If Bit 3 is 0, I2C transaction.
233 */
234 if (request == DPCD_WRITE) {
235 val = AUX_LENGTH(len) |
236 AUX_TX_COMM_DP_TRANSACTION |
237 AUX_TX_COMM_WRITE;
238 for (i = 0; i < len; i++)
239 write32(&edp->regs->buf_data[i],
240 *data++);
241 } else
242 val = AUX_LENGTH(len) |
243 AUX_TX_COMM_DP_TRANSACTION |
244 AUX_TX_COMM_READ;
245
246 write32(&edp->regs->aux_ch_ctl_1, val);
247
248 /* Start AUX transaction */
249 retval = rk_edp_start_aux_transaction(edp);
250 if (retval == 0)
251 break;
252 else
253 printk(BIOS_WARNING, "read dpcd Aux Transaction fail!\n");
254
255 }
256
257 if (retval)
258 return -1;
259
260 if (request == DPCD_READ) {
261 for (i = 0; i < len; i++)
262 *data++ = (u8)read32(&edp->regs->buf_data[i]);
263 }
264
265 length -= len;
266 val_addr += 16;
267 }
268 return 0;
269 }
270
271 static int rk_edp_dpcd_read(struct rk_edp *edp, u32 addr,
272 u8 *values, size_t size)
273 {
274 return rk_edp_dpcd_transfer(edp, addr, values, size, DPCD_READ);
275 }
276
277 static int rk_edp_dpcd_write(struct rk_edp *edp, u32 addr,
278 u8 *values, size_t size)
279 {
280 return rk_edp_dpcd_transfer(edp, addr, values, size, DPCD_WRITE);
281 }
282
283 static int rk_edp_link_power_up(struct rk_edp *edp)
284 {
285 u8 value;
286 int err;
287
288 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
289 if (edp->link_train.revision < 0x11)
290 return 0;
291
292 err = rk_edp_dpcd_read(edp, DPCD_LINK_POWER_STATE, &value, 1);
293 if (err < 0)
294 return err;
295
296 value &= ~DP_SET_POWER_MASK;
297 value |= DP_SET_POWER_D0;
298
299 err = rk_edp_dpcd_write(edp, DPCD_LINK_POWER_STATE, &value, 1);
300 if (err < 0)
301 return err;
302
303 /*
304 * According to the DP 1.1 specification, a "Sink Device must exit the
305 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
306 * Control Field" (register 0x600).
307 */
308 mdelay(1);
309
310 return 0;
311 }
312
313 static int rk_edp_link_configure(struct rk_edp *edp)
314 {
315 u8 values[2];
316
317 values[0] = edp->link_train.link_rate;
318 values[1] = edp->link_train.lane_count;
319
320 return rk_edp_dpcd_write(edp, DPCD_LINK_BW_SET, values, sizeof(values));
321 }
322
323 static void rk_edp_set_link_training(struct rk_edp *edp,
324 const u8 *training_values)
325 {
326 int i;
327
328 for (i = 0; i < edp->link_train.lane_count; i++)
329 write32(&edp->regs->ln_link_trn_ctl[i], training_values[i]);
330 }
331
332 static u8 edp_link_status(const u8 *link_status, int r)
333 {
334 return link_status[r - DPCD_LANE0_1_STATUS];
335 }
336
337 static int rk_edp_dpcd_read_link_status(struct rk_edp *edp, u8 *link_status)
338 {
339 return rk_edp_dpcd_read(edp, DPCD_LANE0_1_STATUS, link_status,
340 DP_LINK_STATUS_SIZE);
341 }
342
343 static u8 edp_get_lane_status(const u8 *link_status, int lane)
344 {
345 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
346 int s = (lane & 1) * 4;
347 u8 l = edp_link_status(link_status, i);
348
349 return (l >> s) & 0xf;
350 }
351
352 static int rk_edp_clock_recovery_ok(const u8 *link_status, int lane_count)
353 {
354 int lane;
355 u8 lane_status;
356
357 for (lane = 0; lane < lane_count; lane++) {
358 lane_status = edp_get_lane_status(link_status, lane);
359 if ((lane_status & DP_LANE_CR_DONE) == 0)
360 return 0;
361 }
362 return 1;
363 }
364
365 static int rk_edp_channel_eq_ok(const u8 *link_status, int lane_count)
366 {
367 u8 lane_align;
368 u8 lane_status;
369 int lane;
370
371 lane_align = edp_link_status(link_status,
372 DPCD_LANE_ALIGN_STATUS_UPDATED);
373 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
374 return 0;
375 for (lane = 0; lane < lane_count; lane++) {
376 lane_status = edp_get_lane_status(link_status, lane);
377 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
378 return 0;
379 }
380 return 1;
381 }
382
383 static u8
384 rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
385 {
386 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
387 int s = ((lane & 1) ?
388 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
389 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
390 u8 l = edp_link_status(link_status, i);
391
392 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
393 }
394
395 static u8 rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
396 int lane)
397 {
398 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
399 int s = ((lane & 1) ?
400 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
401 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
402 u8 l = edp_link_status(link_status, i);
403
404 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
405 }
406
407 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
408 u8 train_set[])
409 {
410 u8 v = 0;
411 u8 p = 0;
412 int lane;
413
414 for (lane = 0; lane < lane_count; lane++) {
415 u8 this_v =
416 rk_edp_get_adjust_request_voltage(link_status, lane);
417 u8 this_p =
418 rk_edp_get_adjust_request_pre_emphasis(link_status,
419 lane);
420
421 printk(BIOS_DEBUG, "requested signal parameters: lane %d "
422 "voltage %s pre_emph %s\n", lane,
423 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
424 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
425
426 if (this_v > v)
427 v = this_v;
428 if (this_p > p)
429 p = this_p;
430 }
431
432 if (v >= DP_VOLTAGE_MAX)
433 v |= DP_TRAIN_MAX_SWING_REACHED;
434
435 if (p >= DP_PRE_EMPHASIS_MAX)
436 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
437
438 printk(BIOS_DEBUG, "using signal parameters: voltage %s pre_emph %s\n",
439 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
440 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
441 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
442 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
443
444 for (lane = 0; lane < 4; lane++)
445 train_set[lane] = v | p;
446 }
447
448 static int rk_edp_link_train_cr(struct rk_edp *edp)
449 {
450 int clock_recovery;
451 u8 voltage, tries = 0;
452 u8 status[DP_LINK_STATUS_SIZE];
453 int i;
454 u8 value;
455
456 value = DP_TRAINING_PATTERN_1;
457 write32(&edp->regs->dp_training_ptn_set, value);
458 rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1);
459 memset(edp->train_set, 0, 4);
460
461 /* clock recovery loop */
462 clock_recovery = 0;
463 tries = 0;
464 voltage = 0xff;
465
466 while (1) {
467 rk_edp_set_link_training(edp, edp->train_set);
468 rk_edp_dpcd_write(edp, DPCD_TRAINING_LANE0_SET,
469 edp->train_set,
470 edp->link_train.lane_count);
471
472 mdelay(1);
473
474 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
475 printk(BIOS_ERR, "displayport link status failed\n");
476 break;
477 }
478
479 if (rk_edp_clock_recovery_ok(status,
480 edp->link_train.lane_count)) {
481 clock_recovery = 1;
482 break;
483 }
484
485 for (i = 0; i < edp->link_train.lane_count; i++) {
486 if ((edp->train_set[i] &
487 DP_TRAIN_MAX_SWING_REACHED) == 0)
488 break;
489 }
490 if (i == edp->link_train.lane_count) {
491 printk(BIOS_ERR, "clock recovery reached max voltage\n");
492 break;
493 }
494
495 if ((edp->train_set[0] &
496 DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
497 ++tries;
498 if (tries == MAX_CR_LOOP) {
499 printk(BIOS_ERR, "clock recovery tried 5 times\n");
500 break;
501 }
502 } else
503 tries = 0;
504
505 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
506
507 /* Compute new train_set as requested by sink */
508 edp_get_adjust_train(status, edp->link_train.lane_count,
509 edp->train_set);
510 }
511 if (!clock_recovery) {
512 printk(BIOS_ERR, "clock recovery failed\n");
513 return -1;
514 } else {
515 printk(BIOS_DEBUG, "clock recovery at voltage %d pre-emphasis %d\n",
516 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
517 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
518 DP_TRAIN_PRE_EMPHASIS_SHIFT);
519 return 0;
520 }
521 }
522
523 static int rk_edp_link_train_ce(struct rk_edp *edp)
524 {
525 int channel_eq;
526 u8 value, tries = 0;
527 u8 status[DP_LINK_STATUS_SIZE];
528
529 value = DP_TRAINING_PATTERN_2;
530 write32(&edp->regs->dp_training_ptn_set, value);
531 rk_edp_dpcd_write(edp, DPCD_TRAINING_PATTERN_SET, &value, 1);
532
533 /* channel equalization loop */
534 channel_eq = 0;
535 for (tries = 0; tries < 5; tries++) {
536 rk_edp_set_link_training(edp, edp->train_set);
537 rk_edp_dpcd_write(edp, DPCD_TRAINING_LANE0_SET,
538 edp->train_set,
539 edp->link_train.lane_count);
540
541 udelay(400);
542 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
543 printk(BIOS_ERR, "displayport link status failed\n");
544 return -1;
545 }
546
547 if (rk_edp_channel_eq_ok(status,
548 edp->link_train.lane_count)) {
549 channel_eq = 1;
550 break;
551 }
552 edp_get_adjust_train(status,
553 edp->link_train.lane_count,
554 edp->train_set);
555 }
556
557 if (!channel_eq) {
558 printk(BIOS_ERR, "channel eq failed\n");
559 return -1;
560 } else {
561 printk(BIOS_DEBUG, "channel eq at voltage %d pre-emphasis %d\n",
562 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
563 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
564 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
565 return 0;
566 }
567 }
568
569 static int rk_edp_init_training(struct rk_edp *edp)
570 {
571 u8 values[3];
572 int err;
573
574 err = rk_edp_dpcd_read(edp, DPCD_DPCD_REV, values, sizeof(values));
575 if (err < 0)
576 return err;
577
578 edp->link_train.revision = values[0];
579 edp->link_train.link_rate = values[1];
580 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
581
582 edp_debug("max link rate:%d.%dGps max number of lanes:%d\n",
583 edp->link_train.link_rate * 27 / 100,
584 edp->link_train.link_rate * 27 % 100,
585 edp->link_train.lane_count);
586
587 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
588 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
589 edp_debug("Rx Max Link Rate is abnormal :%x\n",
590 edp->link_train.link_rate);
591 return -1;
592 }
593
594 if (edp->link_train.lane_count == 0) {
595 edp_debug("Rx Max Lane count is abnormal :%x\n",
596 edp->link_train.lane_count);
597 return -1;
598 }
599
600 rk_edp_link_power_up(edp);
601 rk_edp_link_configure(edp);
602 return 0;
603 }
604
605 static int rk_edp_hw_link_training(struct rk_edp *edp)
606 {
607 u32 val;
608 struct stopwatch sw;
609
610 /* Set link rate and count as you want to establish*/
611 write32(&edp->regs->link_bw_set, edp->link_train.link_rate);
612 write32(&edp->regs->lane_count_set, edp->link_train.lane_count);
613
614 if (rk_edp_link_train_cr(edp))
615 return -1;
616 if (rk_edp_link_train_ce(edp))
617 return -1;
618
619 write32(&edp->regs->dp_hw_link_training, HW_LT_EN);
620 stopwatch_init_msecs_expire(&sw, 10);
621 do {
622 val = read32(&edp->regs->dp_hw_link_training);
623 if (!(val & HW_LT_EN))
624 break;
625 } while (!stopwatch_expired(&sw));
626 if (val & HW_LT_ERR_CODE_MASK) {
627 printk(BIOS_ERR, "edp hw link training error: %d\n",
628 val >> HW_LT_ERR_CODE_SHIFT);
629 return -1;
630 }
631 return 0;
632
633 }
634
635 static int rk_edp_select_i2c_device(struct rk_edp *edp,
636 unsigned int device_addr,
637 unsigned int val_addr)
638 {
639 u32 val;
640 int retval;
641
642 /* Set EDID device address */
643 val = device_addr;
644 write32(&edp->regs->aux_addr_7_0, val);
645 write32(&edp->regs->aux_addr_15_8, 0x0);
646 write32(&edp->regs->aux_addr_19_16, 0x0);
647
648 /* Set offset from base address of EDID device */
649 write32(&edp->regs->buf_data[0], val_addr);
650
651 /*
652 * Set I2C transaction and write address
653 * If bit 3 is 1, DisplayPort transaction.
654 * If Bit 3 is 0, I2C transaction.
655 */
656 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
657 AUX_TX_COMM_WRITE;
658 write32(&edp->regs->aux_ch_ctl_1, val);
659
660 /* Start AUX transaction */
661 retval = rk_edp_start_aux_transaction(edp);
662 if (retval != 0)
663 edp_debug("select_i2c_device Aux Transaction fail!\n");
664
665 return retval;
666 }
667
668 static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp,
669 unsigned int device_addr,
670 unsigned int val_addr,
671 unsigned int count,
672 u8 edid[])
673 {
674 u32 val;
675 unsigned int i, j;
676 unsigned int cur_data_idx;
677 unsigned int defer = 0;
678 int retval = 0;
679
680 for (i = 0; i < count; i += 16) {
681 for (j = 0; j < 10; j++) { /* try 10 times */
682 /* Clear AUX CH data buffer */
683 val = BUF_CLR;
684 write32(&edp->regs->buf_data_ctl, val);
685
686 /* Set normal AUX CH command */
687 clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY);
688
689 /*
690 * If Rx sends defer, Tx sends only reads
691 * request without sending address
692 */
693 if (!defer)
694 retval = rk_edp_select_i2c_device(edp,
695 device_addr, val_addr + i);
696 else
697 defer = 0;
698
699 /*
700 * Set I2C transaction and write data
701 * If bit 3 is 1, DisplayPort transaction.
702 * If Bit 3 is 0, I2C transaction.
703 */
704 val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
705 AUX_TX_COMM_READ;
706 write32(&edp->regs->aux_ch_ctl_1, val);
707
708 /* Start AUX transaction */
709 retval = rk_edp_start_aux_transaction(edp);
710 if (retval == 0)
711 break;
712 else {
713 edp_debug("Aux Transaction fail!\n");
714 continue;
715 }
716
717 /* Check if Rx sends defer */
718 val = read32(&edp->regs->aux_rx_comm);
719 if (val == AUX_RX_COMM_AUX_DEFER ||
720 val == AUX_RX_COMM_I2C_DEFER) {
721 edp_debug("Defer: %d\n\n", val);
722 defer = 1;
723 }
724 }
725
726 if (retval)
727 return -1;
728
729 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
730 val = read32(&edp->regs->buf_data[cur_data_idx]);
731 edid[i + cur_data_idx] = (u8)val;
732 }
733 }
734
735 return retval;
736 }
737
738 static int rk_edp_read_edid(struct rk_edp *edp, struct edid *edid)
739 {
740 u8 buf[EDID_LENGTH * 2];
741 u32 edid_size = EDID_LENGTH;
742 int retval;
743
744 /* Read EDID data */
745 retval = rk_edp_read_bytes_from_i2c(edp, EDID_ADDR,
746 EDID_HEADER, EDID_LENGTH,
747 &buf[EDID_HEADER]);
748 if (retval != 0) {
749 printk(BIOS_ERR, "EDID Read failed!\n");
750 return -1;
751 }
752
753 /* check if edid have extension flag, and read additional EDID data */
754 if (buf[EDID_EXTENSION_FLAG]) {
755 edid_size += EDID_LENGTH;
756 retval = rk_edp_read_bytes_from_i2c(edp, EDID_ADDR,
757 EDID_LENGTH, EDID_LENGTH,
758 &buf[EDID_LENGTH]);
759 if (retval != 0) {
760 printk(BIOS_ERR, "EDID Read failed!\n");
761 return -1;
762 }
763 }
764
765 if (decode_edid(buf, edid_size, edid) != EDID_CONFORMANT) {
766 printk(BIOS_ERR, "%s: Failed to decode EDID.\n",
767 __func__);
768 return -1;
769 }
770
771 edp_debug("EDID Read success!\n");
772 return 0;
773 }
774
775 static int rk_edp_set_link_train(struct rk_edp *edp)
776 {
777 int retval;
778
779 if (rk_edp_init_training(edp)) {
780 printk(BIOS_ERR, "DP LT init failed!\n");
781 return -1;
782 }
783
784 retval = rk_edp_hw_link_training(edp);
785
786 return retval;
787 }
788
789 static void rk_edp_init_video(struct rk_edp *edp)
790 {
791 u32 val;
792
793 val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
794 write32(&edp->regs->common_int_sta_1, val);
795
796 val = CHA_CRI(4) | CHA_CTRL;
797 write32(&edp->regs->sys_ctl_2, val);
798
799 val = VID_HRES_TH(2) | VID_VRES_TH(0);
800 write32(&edp->regs->video_ctl_8, val);
801 }
802
803 static void rk_edp_config_video_slave_mode(struct rk_edp *edp)
804 {
805 clrbits32(&edp->regs->func_en_1,
806 VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
807 }
808
809 static void rk_edp_set_video_cr_mn(struct rk_edp *edp,
810 enum clock_recovery_m_value_type type,
811 u32 m_value,
812 u32 n_value)
813 {
814 u32 val;
815
816 if (type == REGISTER_M) {
817 setbits32(&edp->regs->sys_ctl_4, FIX_M_VID);
818 val = m_value & 0xff;
819 write32(&edp->regs->m_vid_0, val);
820 val = (m_value >> 8) & 0xff;
821 write32(&edp->regs->m_vid_1, val);
822 val = (m_value >> 16) & 0xff;
823 write32(&edp->regs->m_vid_2, val);
824
825 val = n_value & 0xff;
826 write32(&edp->regs->n_vid_0, val);
827 val = (n_value >> 8) & 0xff;
828 write32(&edp->regs->n_vid_1, val);
829 val = (n_value >> 16) & 0xff;
830 write32(&edp->regs->n_vid_2, val);
831 } else {
832 clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID);
833
834 write32(&edp->regs->n_vid_0, 0x00);
835 write32(&edp->regs->n_vid_1, 0x80);
836 write32(&edp->regs->n_vid_2, 0x00);
837 }
838 }
839
840 static int rk_edp_is_video_stream_clock_on(struct rk_edp *edp)
841 {
842 u32 val;
843 struct stopwatch sw;
844
845 stopwatch_init_msecs_expire(&sw, 100);
846 do {
847 val = read32(&edp->regs->sys_ctl_1);
848
849 /*must write value to update DET_STA bit status*/
850 write32(&edp->regs->sys_ctl_1, val);
851 val = read32(&edp->regs->sys_ctl_1);
852 if (!(val & DET_STA))
853 continue;
854
855 val = read32(&edp->regs->sys_ctl_2);
856
857 /*must write value to update CHA_STA bit status*/
858 write32(&edp->regs->sys_ctl_2, val);
859 val = read32(&edp->regs->sys_ctl_2);
860 if (!(val & CHA_STA))
861 return 0;
862 } while (!stopwatch_expired(&sw));
863
864 return -1;
865 }
866
867 static int rk_edp_is_video_stream_on(struct rk_edp *edp)
868 {
869 u32 val;
870 struct stopwatch sw;
871
872 stopwatch_init_msecs_expire(&sw, 100);
873 do {
874 val = read32(&edp->regs->sys_ctl_3);
875
876 /*must write value to update STRM_VALID bit status*/
877 write32(&edp->regs->sys_ctl_3, val);
878
879 val = read32(&edp->regs->sys_ctl_3);
880 if (!(val & STRM_VALID))
881 return 0;
882 } while (!stopwatch_expired(&sw));
883
884 return -1;
885 }
886
887 static int rk_edp_config_video(struct rk_edp *edp)
888 {
889 rk_edp_config_video_slave_mode(edp);
890
891 if (rk_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
892 edp_debug("PLL is not locked yet.\n");
893 return -1;
894 }
895
896 if (rk_edp_is_video_stream_clock_on(edp))
897 return -1;
898
899 /* Set to use the register calculated M/N video */
900 rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
901
902 /* For video bist, Video timing must be generated by register */
903 clrbits32(&edp->regs->video_ctl_10, F_SEL);
904
905 /* Disable video mute */
906 clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE);
907
908 return 0;
909 }
910
911 static void rockchip_edp_force_hpd(struct rk_edp *edp)
912 {
913 u32 val;
914
915 val = read32(&edp->regs->sys_ctl_3);
916 val |= (F_HPD | HPD_CTRL);
917 write32(&edp->regs->sys_ctl_3, val);
918 }
919
920 static int rockchip_edp_get_plug_in_status(struct rk_edp *edp)
921 {
922 u32 val;
923
924 val = read32(&edp->regs->sys_ctl_3);
925 if (val & HPD_STATUS)
926 return 1;
927
928 return 0;
929 }
930
931 /*
932 * support edp HPD function
933 * some hardware version do not support edp hdp,
934 * we use 360ms to try to get the hpd single now,
935 * if we can not get edp hpd single, it will delay 360ms,
936 * also meet the edp power timing request, to compatible
937 * all of the hardware version
938 */
939 static void rk_edp_wait_hpd(struct rk_edp *edp)
940 {
941 struct stopwatch hpd;
942
943 stopwatch_init_msecs_expire(&hpd, 360);
944 do {
945 if (rockchip_edp_get_plug_in_status(edp))
946 return;
947 udelay(100);
948 } while (!stopwatch_expired(&hpd));
949
950 printk(BIOS_DEBUG, "do not get hpd single, force hpd\n");
951 rockchip_edp_force_hpd(edp);
952 }
953
954 int rk_edp_get_edid(struct edid *edid)
955 {
956 int i;
957 int retval;
958
959 /* Read EDID */
960 for (i = 0; i < 3; i++) {
961 retval = rk_edp_read_edid(&rk_edp, edid);
962 if (retval == 0)
963 break;
964 }
965
966 return retval;
967 }
968
969 int rk_edp_prepare(void)
970 {
971 int ret = 0;
972
973 if (rk_edp_set_link_train(&rk_edp)) {
974 printk(BIOS_ERR, "link train failed!\n");
975 return -1;
976 }
977
978 rk_edp_init_video(&rk_edp);
979 ret = rk_edp_config_video(&rk_edp);
980 if (ret)
981 printk(BIOS_ERR, "config video failed\n");
982
983 return ret;
984 }
985
986 int rk_edp_enable(void)
987 {
988 /* Enable video at next frame */
989 setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN);
990
991 return rk_edp_is_video_stream_on(&rk_edp);
992 }
993
994 void rk_edp_init(void)
995 {
996 rk_edp.regs = (struct rk_edp_regs *)EDP_BASE;
997
998 rk_edp_wait_hpd(&rk_edp);
999
1000 rk_edp_init_refclk(&rk_edp);
1001 rk_edp_init_interrupt(&rk_edp);
1002 rk_edp_enable_sw_function(&rk_edp);
1003 rk_edp_init_analog_func(&rk_edp);
1004 rk_edp_init_aux(&rk_edp);
1005 }
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