4 register
"deep_s3_enable_ac" = "0"
5 register
"deep_s3_enable_dc" = "0"
6 register
"deep_s5_enable_ac" = "1"
7 register
"deep_s5_enable_dc" = "1"
8 register
"deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
11 # Note that GPE events called out in ASL code rely on this
12 # route. i.e.
If this route changes
then the affected GPE
13 # offset bits also need
to be changed.
14 register
"gpe0_dw0" = "GPP_A"
15 register
"gpe0_dw1" = "GPP_D"
16 register
"gpe0_dw2" = "GPP_E"
18 # EC host command ranges are in
0x800-0x8ff & 0x200-0x20f
19 register
"gen1_dec" = "0x00fc0801"
20 register
"gen2_dec" = "0x000c0201"
21 # EC memory map range is
0x900-0x9ff
22 register
"gen3_dec" = "0x00fc0901"
25 register
"dptf_enable" = "1"
28 register
"s0ix_enable" = "1"
30 # Disable Command TriState
31 register
"CmdTriStateDis" = "1"
34 register
"ProbelessTrace" = "0"
35 register
"EnableLan" = "0"
36 register
"EnableSata" = "0"
37 register
"SataSalpSupport" = "0"
38 register
"SataMode" = "0"
39 register
"SataPortsEnable[0]" = "0"
40 register
"EnableAzalia" = "1"
41 register
"DspEnable" = "1"
42 register
"IoBufferOwnership" = "3"
43 register
"EnableTraceHub" = "0"
44 register
"SsicPortEnable" = "0"
45 register
"SmbusEnable" = "1"
46 register
"Cio2Enable" = "1"
47 register
"SaImguEnable" = "1"
48 register
"ScsEmmcEnabled" = "1"
49 register
"ScsEmmcHs400Enabled" = "1"
50 register
"ScsSdCardEnabled" = "0"
51 register
"PttSwitch" = "0"
52 register
"InternalGfx" = "1"
53 register
"SkipExtGfxScan" = "1"
54 register
"Device4Enable" = "1"
55 register
"HeciEnabled" = "0"
57 register
"SerialIrqConfigSirqEnable" = "1"
58 register
"PmConfigSlpS3MinAssert" = "2" #
50ms
59 register
"PmConfigSlpS4MinAssert" = "1" #
1s
60 register
"PmConfigSlpSusMinAssert" = "1" #
500ms
61 register
"PmConfigSlpAMinAssert" = "3" #
2s
62 register
"PmTimerDisabled" = "1"
63 register
"VmxEnable" = "1"
65 register
"speed_shift_enable" = "1"
66 register
"dptf_enable" = "1"
67 register
"tdp_pl2_override" = "15"
68 register
"psys_pmax" = "45"
69 register
"tcc_offset" = "10"
70 register
"pch_trip_temp" = "75"
72 register
"pirqa_routing" = "PCH_IRQ11"
73 register
"pirqb_routing" = "PCH_IRQ10"
74 register
"pirqc_routing" = "PCH_IRQ11"
75 register
"pirqd_routing" = "PCH_IRQ11"
76 register
"pirqe_routing" = "PCH_IRQ11"
77 register
"pirqf_routing" = "PCH_IRQ11"
78 register
"pirqg_routing" = "PCH_IRQ11"
79 register
"pirqh_routing" = "PCH_IRQ11"
81 # VR Settings Configuration
for 4 Domains
82 #
+----------------+-------+-------+-------+-------+
83 #| Domain
/Setting | SA | IA | GTUS | GTS |
84 #
+----------------+-------+-------+-------+-------+
85 #| Psi1Threshold |
20A |
20A |
20A |
20A |
86 #| Psi2Threshold |
2A |
2A |
2A |
2A |
87 #| Psi3Threshold |
1A |
1A |
1A |
1A |
88 #| Psi3Enable |
1 |
1 |
1 |
1 |
89 #| Psi4Enable |
1 |
1 |
1 |
1 |
90 #| ImonSlope |
0 |
0 |
0 |
0 |
91 #| ImonOffset |
0 |
0 |
0 |
0 |
92 #| IccMax |
set by SoC code per CPU SKU |
93 #| VrVoltageLimit |
1.52V |
1.52V |
1.52V |
1.52V |
94 #| AcLoadline |
14.75 |
4.42 |
4.7 |
4.7 |
95 #| DcLoadline |
14.2 |
4.2 |
4.41 |
4.41 |
96 #
+----------------+-------+-------+-------+-------+
97 register
"domain_vr_config[VR_SYSTEM_AGENT]" = "{
98 .vr_config_enable = 1,
99 .psi1threshold = VR_CFG_AMP(20),
100 .psi2threshold = VR_CFG_AMP(2),
101 .psi3threshold = VR_CFG_AMP(1),
106 .voltage_limit = 1520,
111 register
"domain_vr_config[VR_IA_CORE]" = "{
112 .vr_config_enable = 1,
113 .psi1threshold = VR_CFG_AMP(20),
114 .psi2threshold = VR_CFG_AMP(2),
115 .psi3threshold = VR_CFG_AMP(1),
120 .voltage_limit = 1520,
125 register
"domain_vr_config[VR_GT_UNSLICED]" = "{
126 .vr_config_enable = 1,
127 .psi1threshold = VR_CFG_AMP(20),
128 .psi2threshold = VR_CFG_AMP(2),
129 .psi3threshold = VR_CFG_AMP(1),
134 .voltage_limit = 1520,
139 register
"domain_vr_config[VR_GT_SLICED]" = "{
140 .vr_config_enable = 1,
141 .psi1threshold = VR_CFG_AMP(20),
142 .psi2threshold = VR_CFG_AMP(2),
143 .psi3threshold = VR_CFG_AMP(1),
148 .voltage_limit = 1520,
153 # PCIe Root port
1 with SRCCLKREQ1#
(WLAN
)
154 register
"PcieRpEnable[0]" = "1"
155 register
"PcieRpClkReqSupport[0]" = "1"
156 register
"PcieRpClkReqNumber[0]" = "1"
157 register
"PcieRpClkSrcNumber[0]" = "1"
158 register
"PcieRpAdvancedErrorReporting[0]" = "1"
159 register
"PcieRpLtrEnable[0]" = "1"
161 # PCIe Root port
5 (NVMe
)
162 # PcieRpEnable
: Enable root port
163 # PcieRpClkReqSupport
: Enable CLKREQ#
164 # PcieRpClkReqNumber
: Uses SRCCLKREQ4#
165 # PcieRpClkSrcNumber
: Uses CLKOUT_PCIE_4
166 # PcieRpAdvancedErrorReporting
: Enable Advanced Error Reporting
167 # PcieRpLtrEnable
: Enable Latency Tolerance Reporting Mechanism
168 register
"PcieRpEnable[4]" = "1"
169 register
"PcieRpClkReqSupport[4]" = "1"
170 register
"PcieRpClkReqNumber[4]" = "4"
171 register
"PcieRpClkSrcNumber[4]" = "4"
172 register
"PcieRpAdvancedErrorReporting[4]" = "1"
173 register
"PcieRpLtrEnable[4]" = "1"
176 register
"usb2_ports[0]" = "USB2_PORT_LONG(OC0)" #
Type-C Port
1
177 register
"usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
178 register
"usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
179 register
"usb2_ports[4]" = "USB2_PORT_LONG(OC1)" #
Type-C Port
2
180 register
"usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty
181 register
"usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
184 register
"usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" #
Type-C Port
1
185 register
"usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" #
Type-C Port
2
186 register
"usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
187 register
"usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
189 # Intel Common SoC Config
190 #
+-------------------+---------------------------+
192 #
+-------------------+---------------------------+
193 #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
194 #| GSPI0 | cr50 TPM. Early init is |
195 #| | required
to set up a BAR |
196 #| |
for TPM communication |
197 #| | before memory is up |
198 #| I2C0 | Touchscreen |
202 #
+-------------------+---------------------------+
203 register
"common_soc_config" = "{
204 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
206 .speed = I2C_SPEED_FAST,
211 .speed = I2C_SPEED_FAST_PLUS,
213 .speed = I2C_SPEED_FAST_PLUS,
221 .speed = I2C_SPEED_FAST,
226 .speed = I2C_SPEED_FAST,
228 .speed = I2C_SPEED_FAST,
240 register
"i2c_voltage[0]" = "I2C_VOLTAGE_3V3"
243 register
"i2c_voltage[2]" = "I2C_VOLTAGE_1V8"
246 register
"i2c_voltage[3]" = "I2C_VOLTAGE_1V8"
249 register
"i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
251 register
"SerialIoDevMode" = "{
252 [PchSerialIoIndexI2C0] = PchSerialIoPci,
253 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
254 [PchSerialIoIndexI2C2] = PchSerialIoPci,
255 [PchSerialIoIndexI2C3] = PchSerialIoPci,
256 [PchSerialIoIndexI2C4] = PchSerialIoPci,
257 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
258 [PchSerialIoIndexSpi0] = PchSerialIoPci,
259 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
260 [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
261 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
262 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
265 device cpu_cluster
0 on
266 device lapic
0 on
end
269 device pci
00.0 on
end # Host Bridge
270 device pci
02.0 on
end # Integrated Graphics Device
271 device pci
13.0 off
end # Integrated Sensor Hub
272 device pci
14.0 on
end # USB xHCI
273 device pci
14.1 on
end # USB xDCI
(OTG
)
274 device pci
14.2 on
end # Thermal Subsystem
277 register
"generic.hid" = ""ACPI0C50
""
278 register
"generic.desc" = ""STM Touchscreen
""
279 register
"generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
280 register
"generic.speed" = "I2C_SPEED_FAST"
281 register
"generic.probed" = "1"
282 register
"generic.has_power_resource" = "1"
283 register
"generic.disable_gpio_export_in_crs" = "1"
284 register
"generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
285 #
2ms
for load switch slew
+ 5 ms
for touchscreen
286 register
"generic.enable_delay_ms" = "7"
287 register
"generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
288 register
"generic.reset_delay_ms" = "20"
289 register
"generic.reset_off_delay_ms" = "1"
290 register
"hid_desc_reg_offset" = "0xab"
291 device i2c
0x49 on
end
293 end # I2C #
0 - Touchscreen
294 device pci
15.1 off
end # I2C #
1
297 register
"generic.hid" = ""ACPI0C50
""
298 register
"generic.desc" = ""ELAN Touchpad
""
299 register
"generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)"
300 register
"generic.speed" = "I2C_SPEED_FAST_PLUS"
301 register
"generic.wake" = "GPE0_DW0_23" # GPP_A23
302 register
"hid_desc_reg_offset" = "0x01"
303 device i2c
0x15 on
end
305 end # I2C #
2 - Trackpad
306 device pci
15.3 on
end # I2C #
3 - Camera
307 device pci
16.0 on
end # Management Engine Interface
1
308 device pci
16.1 off
end # Management Engine Interface
2
309 device pci
16.2 off
end # Management Engine IDE
-R
310 device pci
16.3 off
end # Management Engine KT Redirection
311 device pci
16.4 off
end # Management Engine Interface
3
312 device pci
17.0 off
end # SATA
313 device pci
19.0 on
end # UART #
2
314 device pci
19.1 off
end # I2C #
5
316 chip drivers
/i2c
/max98373
317 register
"vmon_slot_no" = "4"
318 register
"imon_slot_no" = "5"
320 register
"desc" = ""RIGHT SPEAKER AMP
""
321 register
"name" = ""MAXR
""
324 chip drivers
/i2c
/max98373
325 register
"vmon_slot_no" = "6"
326 register
"imon_slot_no" = "7"
328 register
"desc" = ""LEFT SPEAKER AMP
""
329 register
"name" = ""MAXL
""
332 chip drivers
/i2c
/da7219
333 register
"irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
334 register
"btn_cfg" = "50"
335 register
"mic_det_thr" = "500"
336 register
"jack_ins_deb" = "20"
337 register
"jack_det_rate" = ""32ms_64ms
""
338 register
"jack_rem_deb" = "1"
339 register
"a_d_btn_thr" = "0xa"
340 register
"d_b_btn_thr" = "0x16"
341 register
"b_c_btn_thr" = "0x21"
342 register
"c_mic_btn_thr" = "0x3e"
343 register
"btn_avg" = "4"
344 register
"adc_1bit_rpt" = "1"
345 register
"micbias_lvl" = "2600"
346 register
"mic_amp_in_sel" = ""diff
""
351 chip drivers
/intel
/wifi
352 register
"wake" = "GPE0_DW0_00"
353 device pci
00.0 on
end
355 end # PCI Express Port
1
356 device pci
1c
.1 off
end # PCI Express Port
2
357 device pci
1c
.2 off
end # PCI Express Port
3
358 device pci
1c
.3 off
end # PCI Express Port
4
359 device pci
1c
.4 on
end # PCI Express Port
5 (NVMe
)
360 device pci
1c
.5 off
end # PCI Express Port
6
361 device pci
1c
.6 off
end # PCI Express Port
7
362 device pci
1c
.7 off
end # PCI Express Port
8
363 device pci
1d
.0 off
end # PCI Express Port
9
364 device pci
1d
.1 off
end # PCI Express Port
10
365 device pci
1d
.2 off
end # PCI Express Port
11
366 device pci
1d
.3 off
end # PCI Express Port
12
367 device pci
1e
.0 on
end # UART #
0
368 device pci
1e
.1 off
end # UART #
1
370 chip drivers
/spi
/acpi
371 register
"hid" = "ACPI_DT_NAMESPACE_HID"
372 register
"compat_string" = ""google
,cr50
""
373 register
"irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
377 device pci
1e
.3 off
end # GSPI #
1
378 device pci
1e
.4 on
end # eMMC
379 device pci
1e
.5 off
end # SDIO
380 device pci
1e
.6 off
end # SDCard
382 chip ec
/google
/chromeec
383 device pnp
0c09.0 on
end
386 device pci
1f
.1 on
end # P2SB
387 device pci
1f
.2 on
end # Power Management Controller
388 device pci
1f
.3 on
end # Intel HDA
389 device pci
1f
.4 on
end # SMBus
390 device pci
1f
.5 on
end # PCH SPI
391 device pci
1f
.6 off
end # GbE