We call this cache as ram everywhere, so let's call it the same in Kconfig
[coreboot.git] / src / mainboard / broadcom / blast / Kconfig
blob2c14b0a1eda7bb1e96ef72f9c46f76a89281b8b9
1 if BOARD_BROADCOM_BLAST
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_940
7         select NORTHBRIDGE_AMD_AMDK8
8         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
9         select SOUTHBRIDGE_BROADCOM_BCM5780
10         select SOUTHBRIDGE_BROADCOM_BCM5785
11         select SUPERIO_NSC_PC87417
12         select HAVE_BUS_CONFIG
13         select HAVE_OPTION_TABLE
14         select HAVE_PIRQ_TABLE
15         select HAVE_MP_TABLE
16         select CACHE_AS_RAM
17         select HAVE_HARD_RESET
18         select BOARD_ROMSIZE_KB_512
19         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
21 config MAINBOARD_DIR
22         string
23         default broadcom/blast
25 config DCACHE_RAM_BASE
26         hex
27         default 0xcf000
29 config DCACHE_RAM_SIZE
30         hex
31         default 0x01000
33 config DCACHE_RAM_GLOBAL_VAR_SIZE
34         hex
35         default 0x0
37 config APIC_ID_OFFSET
38         hex
39         default 0x0
41 config SB_HT_CHAIN_ON_BUS0
42         int
43         default 1
45 config MAINBOARD_PART_NUMBER
46         string
47         default "Blast"
49 config HW_MEM_HOLE_SIZEK
50         hex
51         default 0x100000
53 config MAX_CPUS
54         int
55         default 4
57 config MAX_PHYSICAL_CPUS
58         int
59         default 2
61 config HT_CHAIN_END_UNITID_BASE
62         hex
63         default 0x1
65 config HT_CHAIN_UNITID_BASE
66         hex
67         default 0x6
69 config SB_HT_CHAIN_ON_BUS0
70         int
71         default 2
73 config IRQ_SLOT_COUNT
74         int
75         default 11
77 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
78         hex
79         default 0x161f
81 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
82         hex
83         default 0x3050
85 endif # BOARD_BROADCOM_BLAST