We call this cache as ram everywhere, so let's call it the same in Kconfig
[coreboot.git] / src / mainboard / artecgroup / dbe61 / Kconfig
blob3997be8856866409eb1e9218feeb55d8c7588057
1 if BOARD_ARTECGROUP_DBE61
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_LX
7         select NORTHBRIDGE_AMD_LX
8         select SOUTHBRIDGE_AMD_CS5536
9         select HAVE_PIRQ_TABLE
10         select PIRQ_ROUTE
11         select UDELAY_TSC
12         select CACHE_AS_RAM
13         select BOARD_ROMSIZE_KB_256
15 config MAINBOARD_DIR
16         string
17         default artecgroup/dbe61
19 config MAINBOARD_PART_NUMBER
20         string
21         default "DBE61"
23 config IRQ_SLOT_COUNT
24         int
25         default 3
27 #config RAMBASE
28 #       hex
29 #       default 0x4000
31 endif # BOARD_ARTECGROUP_DBE61