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fix printk types
[coreboot.git] / src / northbridge / intel / i5000 / raminit.c
blob9c694c7d2801fa9078577c193039b7b6f5e235c6
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19 * MA 02110-1301 USA
20 */
21
22 #include "raminit.h"
23 #include <arch/io.h>
24 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <cpu/x86/lapic.h>
27 #include <cpu/intel/speedstep.h>
28 #include <console/console.h>
29 #include <spd.h>
30 #include <types.h>
31 #include <string.h>
32 #include <cbmem.h>
33 #include <stdlib.h>
34 #include <lib.h>
35 #include <delay.h>
36
37 static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
38 int (*cb)(struct i5000_fbd_channel *))
39 {
40 struct i5000_fbd_channel *c;
41 int ret;
42
43 for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
44 if (c->used && (ret = cb(c)))
45 return ret;
46 return 0;
47 }
48
49 static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
50 int (*cb)(struct i5000_fbd_branch *))
51 {
52 struct i5000_fbd_branch *b;
53 int ret;
54
55 for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
56 if (b->used && (ret = cb(b)))
57 return ret;
58 return 0;
59 }
60
61 static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
62 int (*cb)(struct i5000_fbdimm *))
63 {
64 struct i5000_fbdimm *d;
65 int ret, i;
66
67 for(i = 0; i < I5000_MAX_DIMMS; i++) {
68 d = setup->dimms[i];
69 if ((ret = cb(d))) {
70 return ret;
71 }
72 }
73 return 0;
74 }
75
76 static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
77 int (*cb)(struct i5000_fbdimm *))
78 {
79 struct i5000_fbdimm *d;
80 int ret, i;
81
82 for(i = 0; i < I5000_MAX_DIMMS; i++) {
83 d = setup->dimms[i];
84 if (d->present && (ret = cb(d)))
85 return ret;
86 }
87 return 0;
88 }
89
90 static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
91 {
92 u16 status;
93 device_t dev = d->branch->branchdev;
94
95 int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
96 int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
97
98 while(count-- > 0) {
99 pci_write_config32(dev, cmdreg, 0xa8000000 | \
100 (d->num & 0x03) << 24 | addr++ << 16);
101
102 int timeout = 1000;
103 while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--)
104 udelay(10);
105
106 if (status & I5000_SPD_SBE || !timeout)
107 return -1;
108
109 if (status & I5000_SPD_RDO) {
110 *out = status & 0xff;
111 out++;
112 }
113 }
114 return 0;
115 }
116
117 static void i5000_clear_fbd_errors(void)
118 {
119 device_t dev16_1, dev16_2;
120
121 dev16_1 = PCI_ADDR(0, 16, 1, 0);
122 dev16_2 = PCI_ADDR(0, 16, 2, 0);
123
124 pci_write_config32(dev16_1, I5000_EMASK_FBD,
125 pci_read_config32(dev16_1, I5000_EMASK_FBD));
126
127 pci_write_config32(dev16_1, I5000_NERR_FAT_FBD,
128 pci_read_config32(dev16_1, I5000_NERR_FAT_FBD));
129
130 pci_write_config32(dev16_1, I5000_FERR_FAT_FBD,
131 pci_read_config32(dev16_1, I5000_FERR_FAT_FBD));
132
133 pci_write_config32(dev16_1, I5000_NERR_NF_FBD,
134 pci_read_config32(dev16_1, I5000_NERR_NF_FBD));
135
136 pci_write_config32(dev16_1, I5000_FERR_NF_FBD,
137 pci_read_config32(dev16_1, I5000_FERR_NF_FBD));
138
139 pci_write_config32(dev16_2, I5000_FERR_GLOBAL,
140 pci_read_config32(dev16_2, I5000_FERR_GLOBAL));
141
142 pci_write_config32(dev16_2, I5000_NERR_GLOBAL,
143 pci_read_config32(dev16_2, I5000_NERR_GLOBAL));
144 }
145
146 static int i5000_branch_reset(struct i5000_fbd_branch *b)
147 {
148 device_t dev = b->branchdev;
149
150 pci_write_config8(dev, I5000_FBDRST, 0x00);
151
152 udelay(5000);
153
154 pci_write_config8(dev, I5000_FBDRST, 0x05);
155 udelay(1);
156 pci_write_config8(dev, I5000_FBDRST, 0x04);
157 udelay(2);
158 pci_write_config8(dev, I5000_FBDRST, 0x05);
159 pci_write_config8(dev, I5000_FBDRST, 0x07);
160 return 0;
161 }
162
163 static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
164 {
165 int div;
166
167 switch (d->setup->ddr_speed) {
168 case DDR_533MHZ:
169 div = 375;
170 break;
171
172 default:
173 printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
174 d->setup->ddr_speed);
175
176 case DDR_667MHZ:
177 div = 300;
178 break;
179 }
180
181 return (del * 100) / div;
182 }
183
184 static int mtb2clks(struct i5000_fbdimm *d, int del)
185 {
186 int val, div;
187
188 switch (d->setup->ddr_speed) {
189 case DDR_533MHZ:
190 div = 375;
191 break;
192 default:
193 printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
194 d->setup->ddr_speed);
195
196 case DDR_667MHZ:
197 div = 300;
198 break;
199 }
200
201 val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div);
202 if ((val % 10) > 0)
203 val += 10;
204 return val / 10;
205 }
206
207 static int i5000_read_spd_data(struct i5000_fbdimm *d)
208 {
209 struct i5000_fbd_setup *s = d->setup;
210 u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
211 u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
212 u8 cmd2data_addr;
213 int t_ck_min, dimmsize;
214
215 if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
216 printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
217 d->branch->num, d->channel->num, d->num);
218 return 0; // No FBDIMM present
219 }
220
221 if (val != 0x09)
222 return -1; // SDRAM type not FBDIMM
223
224 if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
225 return -1;
226
227 switch(s->ddr_speed) {
228 case DDR_533MHZ:
229 cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
230 break;
231
232 case DDR_667MHZ:
233 cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
234 break;
235
236 default:
237 printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
238 return -1;
239 }
240
241 if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
242 spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
243 spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
244 spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
245 spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
246 spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
247 spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
248 spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
249 spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
250 spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
251 spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
252 spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
253 spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
254 spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
255 spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
256 spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
257 spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
258 spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
259 spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
260 spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
261 spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
262 spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
263 spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
264 spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
265 printk(BIOS_ERR, "failed to read data from SPD\n");
266 return 0;
267 }
268
269
270 t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
271 if (t_ck_min <= 300)
272 d->speed = DDR_667MHZ;
273 else if (t_ck_min <= 375)
274 d->speed = DDR_533MHZ;
275 else {
276 printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
277 return -1;
278 }
279
280 d->sdram_width = org & 0x07;
281 if (d->sdram_width > 1) {
282 printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
283 return -1;
284 }
285
286 if (s->ddr_speed == DDR_667MHZ && d->speed == DDR_533MHZ)
287 s->ddr_speed = DDR_533MHZ;
288
289 d->banks = 4 << (addr & 0x03);
290 d->columns = 9 + ((addr >> 2) & 0x03);
291 d->rows = 12 + ((addr >> 5) & 0x03);
292 d->ranks = (org >> 3) & 0x03;
293 d->min_cas_latency = cas & 0x0f;
294
295 s->bl &= bl;
296
297 if (!s->bl) {
298 printk(BIOS_ERR, "no compatible burst length found\n");
299 return -1;
300 }
301
302 s->t_rc = MAX(s->t_rc, mtb2clks(d,
303 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
304 s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
305 s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
306 s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
307 s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
308 s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
309 s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
310 s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
311 s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
312 s->t_ras = MAX(s->t_ras, mtb2clks(d,
313 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
314 s->t_r2r = MAX(s->t_r2r, bb & 3);
315 s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
316 s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3);
317
318 d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20;
319 dimmsize = d->ranksize * d->ranks;
320 d->branch->totalmem += dimmsize;
321 s->totalmem += dimmsize;
322
323 d->channel->columns = d->columns;
324 d->channel->rows = d->rows;
325 d->channel->ranks = d->ranks;
326 d->channel->banks = d->banks;
327 d->channel->width = d->sdram_width;
328
329 printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, "
330 "%d columns, %d rows, %d ranks\n",
331 d->branch->num, d->channel->num, d->num, dimmsize,
332 d->banks, d->columns, d->rows, d->ranks);
333
334 d->present = 1;
335 d->branch->used |= 1;
336 d->channel->used |= 1;
337 d->channel->highest_amb = d->num;
338 return 0;
339 }
340
341 static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2)
342 {
343 u16 status;
344 device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
345 int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
346 int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
347 int timeout = 1000;
348
349 pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
350 (byte1 << 16) | (byte2 << 8) | 1);
351
352 while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
353 udelay(10);
354
355 if (status & I5000_SPD_WOD && timeout)
356 return 0;
357
358 printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
359 d->branch->num, d->channel->num, d->num, byte1, byte2, status);
360 for(;;);
361 return -1;
362 }
363
364 static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
365 {
366 u16 status;
367 device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
368 int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
369 int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
370 int timeout = 1000;
371
372 pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
373 (byte1 << 16));
374
375 while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
376 udelay(10);
377
378 if ((status & I5000_SPD_RDO) && timeout)
379 *out = status & 0xff;
380
381 if (status & I5000_SPD_SBE || !timeout) {
382 printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n",
383 d->branch->num, d->channel->num, d->num, byte1, status);
384 return -1;
385 }
386 return 0;
387
388 }
389
390 static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
391 int fn, int reg, u8 val)
392 {
393 if (i5000_amb_smbus_write(d, 0x84, 00) ||
394 i5000_amb_smbus_write(d, 0x04, fn) ||
395 i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
396 i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
397 i5000_amb_smbus_write(d, 0x44, val)) {
398 printk(BIOS_ERR, "AMB SMBUS write failed\n");
399 return 1;
400 }
401 return 0;
402 }
403
404 static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
405 int fn, int reg, u16 val)
406 {
407 if (i5000_amb_smbus_write(d, 0x88, 00) ||
408 i5000_amb_smbus_write(d, 0x08, fn) ||
409 i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
410 i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
411 i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
412 i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
413 printk(BIOS_ERR, "AMB SMBUS write failed\n");
414 return 1;
415 }
416 return 0;
417 }
418
419 static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
420 int fn, int reg, u32 val)
421 {
422 if (i5000_amb_smbus_write(d, 0x8c, 00) ||
423 i5000_amb_smbus_write(d, 0x0c, fn) ||
424 i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
425 i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
426 i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
427 i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
428 i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
429 i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
430 printk(BIOS_ERR, "AMB SMBUS write failed\n");
431 return 1;
432 }
433 return 0;
434 }
435
436 static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
437 int fn, int reg, u32 *val)
438 {
439 u8 byte3, byte2, byte1, byte0;
440
441 if (i5000_amb_smbus_write(d, 0x80, 00) ||
442 i5000_amb_smbus_write(d, 0x00, fn) ||
443 i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
444 i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
445 i5000_amb_smbus_read(d, 0x80, &byte3) ||
446 i5000_amb_smbus_read(d, 0x00, &byte3) ||
447 i5000_amb_smbus_read(d, 0x00, &byte2) ||
448 i5000_amb_smbus_read(d, 0x00, &byte1) ||
449 i5000_amb_smbus_read(d, 0x40, &byte0)) {
450 printk(BIOS_ERR, "AMB SMBUS read failed\n");
451 return 1;
452 }
453 *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
454 return 0;
455 }
456
457 static void i5000_amb_write_config8(struct i5000_fbdimm *d,
458 int fn, int reg, u32 val)
459 {
460 write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
461 }
462
463 static void i5000_amb_write_config16(struct i5000_fbdimm *d,
464 int fn, int reg, u32 val)
465 {
466 write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
467 }
468
469 static void i5000_amb_write_config32(struct i5000_fbdimm *d,
470 int fn, int reg, u32 val)
471 {
472 write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
473 }
474
475 static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
476 int fn, int reg)
477 {
478 return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
479 }
480
481 static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
482 {
483 u32 drc, status;
484
485 printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
486 d->branch->num, d->channel->num, d->num, rank, command, addr);
487
488 drc = i5000_amb_read_config32(d, 3, AMB_DRC);
489 drc &= ~((3 << 9) | (1 << 12));
490 drc |= (rank << 9);
491
492 command &= 0x0f;
493 command |= AMB_DCALCSR_START | (rank << 21);
494
495 printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command);
496 i5000_amb_write_config32(d, 3, AMB_DRC, drc);
497 i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
498 i5000_amb_write_config32(d, 4, AMB_DCALCSR, command);
499
500 udelay(1000);
501 while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
502 & (1 << 31));
503
504 if (status & (1 << 30)) {
505 printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
506 return -1;
507 }
508
509 printk(BIOS_SPEW, "done\n");
510 return 0;
511 }
512
513 static int i5000_ddr_calibration(struct i5000_fbdimm *d)
514 {
515 u32 status;
516
517 i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
518 i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
519 while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
520
521 i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
522 while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
523
524 if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
525 ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
526 return -1;
527 return 0;
528 }
529
530 static int i5000_ddr_init(struct i5000_fbdimm *d)
531 {
532
533 int rank;
534 u32 val;
535 u8 odt;
536
537 for(rank = 0; rank < d->ranks; rank++) {
538 printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
539 d->branch->num, d->channel->num, d->num, rank);
540
541 if (ddr_command(d, 1 << rank,
542 0, AMB_DCALCSR_OPCODE_NOP))
543 return -1;
544
545 if (ddr_command(d, 1 << rank,
546 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
547 return -1;
548
549 /* EMRS(2) */
550 if (ddr_command(d, 1 << rank,
551 2, AMB_DCALCSR_OPCODE_MRS_EMRS))
552 return -1;
553
554 /* EMRS(3) */
555 if (ddr_command(d, 1 << rank,
556 3, AMB_DCALCSR_OPCODE_MRS_EMRS))
557 return -1;
558
559 /* EMRS(1) */
560 if (ddr_command(d, 1 << rank,
561 1, AMB_DCALCSR_OPCODE_MRS_EMRS))
562 return -1;
563
564 /* MRS: DLL reset */
565 if (ddr_command(d, 1 << rank,
566 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
567 return -1;
568
569 udelay(20);
570
571 if (ddr_command(d, 1 << rank,
572 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
573 return -1;
574
575 if (ddr_command(d, 1 << rank,
576 0, AMB_DCALCSR_OPCODE_REFRESH))
577 return -1;
578
579 if (ddr_command(d, 1 << rank, 0,
580 AMB_DCALCSR_OPCODE_REFRESH))
581 return -1;
582
583 /* burst length + cas latency */
584 val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
585 (1 << 19) /* interleaved burst */ |
586 (d->setup->t_cl << 20) |
587 (((d->setup->t_wr - 1) & 7) << 25);
588
589 printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
590 if (ddr_command(d, 1 << rank,
591 val, AMB_DCALCSR_OPCODE_MRS_EMRS))
592 return -1;
593
594 /* OCD calibration default */
595 if (ddr_command(d, 1 << rank, 0x03800001,
596 AMB_DCALCSR_OPCODE_MRS_EMRS))
597 return -1;
598
599
600 odt = d->odt;
601 if (rank)
602 odt >>= 4;
603
604 val = (d->setup->t_al << 19) |
605 ((odt & 1) << 18) |
606 ((odt & 2) << 21) | 1;
607
608 printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
609
610 /* ODT, OCD exit, additive latency */
611 if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
612 return -1;
613 }
614 return 0;
615 }
616
617 static int i5000_amb_preinit(struct i5000_fbdimm *d)
618 {
619 u32 *p32 = (u32 *)d->amb_personality_bytes;
620 u16 *p16 = (u16 *)d->amb_personality_bytes;
621 u32 id, drc, fbdsbcfg = 0x0909;
622
623 printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
624 d->branch->num, d->channel->num, d->num);
625
626 i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
627 i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
628
629 drc = (d->setup->t_al << 4) | (d->setup->t_cl);
630 printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
631 d->cmd2datanxt[d->setup->ddr_speed]);
632
633 switch(d->setup->ddr_speed) {
634 case DDR_533MHZ:
635 fbdsbcfg |= (1 << 16);
636 break;
637 case DDR_667MHZ:
638 fbdsbcfg |= (2 << 16);
639 break;
640 default:
641 return -1;
642 }
643
644 printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg);
645 i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg);
646 i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
647 i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
648 d->cmd2datanxt[d->setup->ddr_speed]);
649
650 i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
651
652 if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
653 d->vendor = id & 0xffff;
654 d->device = id >> 16;
655 }
656
657 pci_write_config8(d->branch->branchdev,
658 d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
659 return 0;
660 }
661
662 static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
663 {
664 int timeout = 10000;
665 device_t dev = b->branchdev;
666
667 printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state);
668
669 pci_write_config8(dev, I5000_FBDHPC, state);
670
671 printk(BIOS_DEBUG, "waiting for new state...");
672
673 while(pci_read_config8(dev, I5000_FBDST) != state && timeout--)
674 udelay(10);
675
676 if (timeout) {
677 printk(BIOS_DEBUG, "done\n");
678 return;
679 }
680
681 printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n",
682 state, b->num);
683 }
684
685 static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
686 {
687 int i = 10;
688 device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
689 c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
690
691 printk(BIOS_DEBUG, " waiting for pattern recognition...");
692 while(pci_read_config16(dev, 0) != 0x1fff && --i > 0)
693 udelay(5000);
694
695 printk(BIOS_DEBUG, i ? "done\n" : "failed\n");
696 printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,
697 pci_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
698 return !i;
699 }
700
701 static const char *pattern_names[16] = {
702 "EI", "EI", "EI", "EI",
703 "EI", "EI", "EI", "EI",
704 "TS0", "TS1", "TS2", "TS3",
705 "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
706 };
707
708 static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
709 {
710 device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
711 c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
712
713 printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n",
714 c->branch->num, c->num,
715 pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
716 pci_write_config8(dev, 0, pattern);
717
718 if (!wait)
719 return 0;
720
721 return i5000_wait_pattern_recognized(c);
722 }
723
724 static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
725 {
726 int i;
727 device_t branchdev = c->branch->branchdev;
728 u16 ambpresent = 0x8000;
729
730 for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
731 if (c->dimm[i].present)
732 ambpresent |= (1 << i);
733 }
734
735 printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
736 pci_write_config16(branchdev,
737 c->num ?
738 I5000_AMBPRESENT1 : \
739 I5000_AMBPRESENT0, ambpresent);
740
741 return 0;
742 }
743
744
745 static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
746 {
747 device_t branchdev = c->branch->branchdev;
748 int off = c->num ? 0x100 : 0;
749 u32 portctl;
750 int i, cnt = 1000;
751
752 portctl = pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
753 portctl &= ~0x01000020;
754 if (mchpad)
755 portctl |= 0x00800000;
756 else
757 portctl &= ~0x00800000;
758 portctl &= ~0x01000020;
759 pci_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
760
761 /* drive calibration patterns */
762 if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
763 return -1;
764
765 if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
766 return -1;
767
768 while (!(pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
769 udelay(10);
770
771 if (!cnt) {
772 printk(BIOS_ERR, "IBIST timeout\n");
773 return -1;
774 }
775
776 if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
777 return -1;
778
779 for(i = 0; i < highest_amb; i++) {
780 if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
781 return -1;
782 }
783
784 if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
785 return -1;
786
787 if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
788 return -1;
789
790 if (i5000_set_ambpresent(c))
791 return -1;
792 return 0;
793 }
794
795 static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
796 {
797 int i;
798 u32 fbdsbcfg = 0x0b1b;
799
800 switch(c->setup->ddr_speed) {
801 case DDR_533MHZ:
802 fbdsbcfg |= (1 << 16);
803 break;
804 case DDR_667MHZ:
805 fbdsbcfg |= (2 << 16);
806 break;
807 default:
808 return -1;
809 }
810
811 pci_write_config8(c->branch->branchdev,
812 c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
813
814 for(i = 0; i < 4; i++) {
815 if (c->dimm[i].present)
816 i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg);
817 }
818
819 return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
820 }
821
822 static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
823 {
824 if (i5000_train_channel_idle(c))
825 return -1;
826
827 return i5000_drive_test_patterns(c, c->highest_amb, 0);
828 }
829
830 static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
831 {
832 if (i5000_train_channel_idle(c))
833 return -1;
834
835 return i5000_drive_test_patterns(c, c->highest_amb, 1);
836 }
837
838 static int i5000_setup_channel(struct i5000_fbd_channel *c)
839 {
840 device_t branchdev = c->branch->branchdev;
841 int off = c->branch->num ? 0x100 : 0;
842 u32 val;
843
844 pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
845 pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
846 pci_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
847 pci_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
848
849 pci_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
850
851 /* unknown */
852 val = pci_read_config32(branchdev, off + 0x0164);
853 val &= 0xfffbcffc;
854 val |= 0x4004;
855 pci_write_config32(branchdev, off + 0x164, val);
856
857 pci_write_config32(branchdev, off + 0x15c, 0xff);
858 i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
859 return 0;
860 }
861
862 static int i5000_link_training0(struct i5000_fbd_branch *b)
863 {
864 device_t branchdev = b->branchdev;
865
866 pci_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
867
868 if (i5000_for_each_channel(b, i5000_setup_channel))
869 return -1;
870
871 if (i5000_for_each_channel(b, i5000_train_channel_idle))
872 return -1;
873
874 i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
875
876 if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
877 return -1;
878
879 i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
880 return 0;
881 }
882
883 static int i5000_link_training1(struct i5000_fbd_branch *b)
884 {
885 if (i5000_for_each_channel(b, i5000_train_channel_idle))
886 return -1;
887
888 i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
889
890 if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
891 return -1;
892
893 i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
894 return 0;
895 }
896
897
898 static int i5000_amb_check(struct i5000_fbdimm *d)
899 {
900 u32 id = i5000_amb_read_config32(d, 0, 0);
901
902 printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n",
903 d->branch->num, d->channel->num, d->num,
904 id & 0xffff, id >> 16);
905
906 if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
907 printk(BIOS_ERR, "AMB mapping failed\n");
908 return -1;
909 }
910 return 0;
911 }
912
913 static int i5000_amb_postinit(struct i5000_fbdimm *d)
914 {
915 u32 *p32 = (u32 *)d->amb_personality_bytes;
916 u16 *p16 = (u16 *)d->amb_personality_bytes;
917
918 i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
919 i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
920 i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
921 return 0;
922 }
923
924 static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
925 {
926 struct i5000_fbd_setup *s;
927 u32 val, tref;
928 int refi;
929
930 s = d->setup;
931
932 printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
933 d->branch->num, d->channel->num, d->num);
934
935 val = 0x44;
936 printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
937 i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
938
939 val = (0x0c << 24) | /* CLK control */
940 (1 << 18) | /* ODTZ enabled */
941 (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
942 ((d->setup->t_al & 0x0f) << 4) | /* additive latency */
943 (d->setup->t_cl & 0x0f); /* CAS latency */
944
945 if (d->ranks > 1) {
946 val |= (0x03 << 9);
947 } else {
948 val |= (0x01 << 9);
949 }
950
951 printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val);
952 i5000_amb_write_config32(d, 3, AMB_DRC, val);
953
954 val = (d->sdram_width << 30) |
955 ((d->ranks == 2 ? 1 : 0) << 29) |
956 ((d->banks == 8 ? 1 : 0) << 28) |
957 ((d->rows - 13) << 26) |
958 ((d->columns - 10) << 24) |
959 (1 << 16) | /* Auto refresh exit */
960 (0x27 << 8) | /* t_xsnr */
961 (d->setup->t_rp << 4) |
962 (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
963
964 printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
965 i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
966
967 tref = 15;
968
969 switch(d->t_refi & 0x0f) {
970 case 0:
971 refi = 15625;
972 break;
973 case 1:
974 refi = 3900;
975 tref = 3;
976 break;
977 case 2:
978 refi = 7800;
979 tref = 7;
980 break;
981 case 3:
982 refi = 31250;
983 break;
984 case 4:
985 refi = 62500;
986 break;
987 case 5:
988 refi = 125000;
989 break;
990 default:
991 printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n",
992 d->t_refi & 0x0f);
993 refi = 7800;
994 break;
995 }
996
997 s->t_ref = tref;
998 val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
999
1000 printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val);
1001 i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
1002
1003 u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
1004 (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
1005 u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
1006
1007 val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
1008 ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
1009 ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
1010 ((s->t_rtp - 2) << 27);
1011
1012 switch(s->t_ras) {
1013 case 15:
1014 val |= (1 << 29);
1015 break;
1016 case 12:
1017 val |= (2 << 29);
1018 break;
1019 default:
1020 break;
1021 }
1022
1023 printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val);
1024 i5000_amb_write_config32(d, 3, AMB_DRT, val);
1025 return 0;
1026 }
1027
1028 static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
1029 {
1030 printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
1031 d->branch->num, d->channel->num, d->num, rank, pattern);
1032
1033 i5000_amb_write_config32(d, 3, AMB_DAREFTC,
1034 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
1035
1036 i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
1037 i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
1038 i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
1039 return 0;
1040 }
1041
1042 static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
1043 {
1044 int cnt = 1000;
1045 u32 res;
1046
1047 while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
1048 udelay(1000);
1049
1050 if (cnt && !(res & (1 << 30)))
1051 return 0;
1052
1053 printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
1054 d->branch->num, d->channel->num, d->num, rank);
1055 return -1;
1056 }
1057
1058 static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
1059 {
1060 if (i5000_do_amb_membist_start(d, 1, 0))
1061 return -1;
1062 return 0;
1063 }
1064
1065 static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
1066 {
1067
1068 if (d->ranks < 2)
1069 return 0;
1070 if (i5000_do_amb_membist_start(d, 2, 0))
1071 return -1;
1072 return 0;
1073 }
1074
1075 static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
1076 {
1077 if (i5000_do_amb_membist_status(d, 1))
1078 return -1;
1079 return 0;
1080 }
1081
1082 static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
1083 {
1084 if (d->ranks < 2)
1085 return 0;
1086
1087 if (i5000_do_amb_membist_status(d, 2))
1088 return -1;
1089 return 0;
1090 }
1091
1092 static int i5000_amb_membist_end(struct i5000_fbdimm *d)
1093 {
1094 printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
1095 return 0;
1096 }
1097
1098 static int i5000_membist(struct i5000_fbd_setup *setup)
1099 {
1100 return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
1101 i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
1102 i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
1103 i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
1104 i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
1105 }
1106
1107 static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
1108 {
1109 u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
1110 tmp &= ~(1 << 16);
1111 printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
1112 i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
1113 return 0;
1114 }
1115
1116 static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
1117 {
1118 i5000_amb_write_config32(d, 1, AMB_FERR, 9);
1119 i5000_amb_write_config32(d, 1, AMB_NERR, 9);
1120 i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
1121 i5000_amb_write_config8(d, 3, 0x80, 0xcf);
1122 i5000_amb_write_config8(d, 3, 0x81, 0xd3);
1123 i5000_amb_write_config8(d, 3, 0x82, 0xf8);
1124 return 0;
1125 }
1126
1127 static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
1128 {
1129 u32 val;
1130
1131 if (c->dimm[0].present || c->dimm[1].present) {
1132 val = (((c->columns - 10) & 3) |
1133 (((c->rows - 13) & 3) << 2) |
1134 (((c->ranks == 2) ? 1 : 0) << 4) |
1135 (((c->banks == 8) ? 1 : 0) << 5) |
1136 ((c->width ? 1 : 0) << 6) |
1137 (1 << 7) | /* Electrical Throttling enabled */
1138 (1 << 8)); /* DIMM present and compatible */
1139 printk(BIOS_DEBUG, "MTR0: %04x\n", val);
1140 pci_write_config16(c->branch->branchdev, mtr, val);
1141 }
1142
1143 if (c->dimm[2].present || c->dimm[3].present) {
1144 val = (((c->columns - 10) & 3) |
1145 (((c->rows - 13) & 3) << 4) |
1146 ((c->ranks ? 1 : 0) << 4) |
1147 (((c->banks == 8) ? 1 : 0) << 5) |
1148 ((c->width ? 1 : 0) << 6) |
1149 (1 << 7) | /* Electrical Throttling enabled */
1150 (1 << 8)); /* DIMM present and compatible */
1151 printk(BIOS_DEBUG, "MTR1: %04x\n", val);
1152 pci_write_config16(c->branch->branchdev, mtr+2, val);
1153 }
1154 }
1155
1156 static int get_dmir(u8 *rankmap, int *_set, int limit)
1157 {
1158 int i, dmir = 0, set = 0;
1159
1160 for(i = 7; set < limit && i >= 0; i--) {
1161 if (!(*rankmap & (1 << i)))
1162 continue;
1163
1164 *rankmap &= ~(1 << i);
1165
1166 switch(limit) {
1167 case 1:
1168 dmir |= (i |
1169 (i << 3) |
1170 (i << 6) |
1171 (i << 9));
1172 break;
1173 case 2:
1174 dmir |= (i << (set * 3)) |
1175 (i << (6 + set * 3));
1176 break;
1177 case 4:
1178 dmir |= (i << (set * 3));
1179 break;
1180
1181 default:
1182 break;
1183 }
1184 set++;
1185 }
1186 *_set = set;
1187 return dmir;
1188 }
1189
1190 static int i5000_setup_dmir(struct i5000_fbd_branch *b)
1191 {
1192 struct i5000_fbdimm *d;
1193 device_t dev = b->branchdev;
1194 u8 rankmap = 0, dmir = 0;
1195 u32 dmirval = 0;
1196 int i, set, rankoffset = 0, ranksize = 0, ranks = 0;
1197
1198 if (!b->used)
1199 return 0;
1200
1201 for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
1202 rankmap >>= 2;
1203 d = b->channel[0].dimm + i;
1204
1205 if (!d->present)
1206 continue;
1207
1208 if (d->ranks == 2) {
1209 rankmap |= 0xc0;
1210 ranks += 2;
1211 } else {
1212 rankmap |= 0x40;
1213 ranks++;
1214 }
1215 }
1216
1217 printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);
1218
1219 dmir = I5000_DMIR0;
1220
1221 ranksize = b->channel[0].dimm[0].ranksize << 8;
1222
1223 if (!b->setup->single_channel)
1224 ranksize <<= 1;
1225
1226 while(ranks) {
1227
1228 if (ranks >= 4)
1229 dmirval = get_dmir(&rankmap, &set, 4);
1230 else if (ranks >= 2)
1231 dmirval = get_dmir(&rankmap, &set, 2);
1232 else
1233 dmirval = get_dmir(&rankmap, &set, 1);
1234
1235 ranks -= set;
1236
1237 dmirval |= rankoffset + (set * ranksize);
1238
1239 rankoffset += (set * ranksize);
1240
1241 printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
1242 dmirval);
1243 pci_write_config32(dev, dmir, dmirval);
1244 dmir += 4;
1245 }
1246
1247 for(; dmir <= I5000_DMIR4; dmir += 4) {
1248 printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
1249 dmirval);
1250 pci_write_config32(dev, dmir, dmirval);
1251 }
1252 return rankoffset;
1253 }
1254
1255 static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
1256 {
1257 device_t dev16 = PCI_ADDR(0, 16, 1, 0);
1258 u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
1259
1260 size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;
1261 size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;
1262
1263 minsize = MIN(size0, size1);
1264
1265 if (size0 > size1) {
1266 tmp = size1;
1267 size1 = size0;
1268 size0 = tmp;
1269 }
1270
1271 if (size0 == size1) {
1272 mir0 = (size0 << 1) | 3;
1273 mir1 = (size0 << 1);
1274 mir2 = (size0 << 1);
1275 } else if (!size0) {
1276 mir0 = size1 | 1;
1277 mir1 = size1;
1278 mir2 = size1;
1279 } else {
1280 mir0 = (size0 << 1) | 3;
1281 mir1 = (size1 + size0) | 1;
1282 mir2 = size1 + size0;
1283 }
1284
1285 printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
1286 printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);
1287 printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);
1288
1289 pci_write_config16(dev16, I5000_MIR0, mir0);
1290 pci_write_config16(dev16, I5000_MIR1, mir1);
1291 pci_write_config16(dev16, I5000_MIR2, mir2);
1292 }
1293
1294 static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
1295 {
1296 device_t dev16 = PCI_ADDR(0, 16, 1, 0);
1297 u32 tolm, drta, drtb, mc, mca;
1298 int t_wrc, bl2;
1299
1300 bl2 = (setup->bl & BL_BL8) ? 4 :2;
1301 t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
1302 setup->t_wr + setup->t_rp;
1303
1304 drta = (setup->t_ref & 0x0f) |
1305 ((setup->t_rrd & 0x0f) << 4) |
1306 ((setup->t_rfc & 0xff) << 8) |
1307 ((setup->t_rc & 0x3f) << 16) |
1308 ((t_wrc & 0x3f) << 22) |
1309 (setup->t_al & 0x07) << 28;
1310
1311 drtb = (bl2) |
1312 (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
1313 (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
1314 (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
1315 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
1316
1317 mc = (1 << 30) | /* enable retry */
1318 (3 << 25) | /* bad RAM threshold */
1319 (1 << 21) | /* INITDONE */
1320 (1 << 20) | /* FSB enable */
1321 /* Electrical throttling: 20 clocks */
1322 ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |
1323 (1 << 8) | /* enhanced scrub mode */
1324 (1 << 7) | /* enable patrol scrub */
1325 (1 << 6) | /* enable demand scrubing */
1326 (1 << 5); /* enable northbound error detection */
1327
1328 printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
1329 pci_write_config32(dev16, I5000_DRTA, drta);
1330 pci_write_config32(dev16, I5000_DRTB, drtb);
1331 pci_write_config32(dev16, I5000_MC, mc);
1332
1333 mca = pci_read_config32(dev16, I5000_MCA);
1334
1335 mca |= (7 << 28);
1336 if (setup->single_channel)
1337 mca |= (1 << 14);
1338 else
1339 mca &= ~(1 << 14);
1340 printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
1341 pci_write_config32(dev16, I5000_MCA, mca);
1342
1343 pci_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
1344
1345 i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
1346 i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
1347 i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
1348 i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
1349
1350 i5000_setup_interleave(setup);
1351
1352 if ((tolm = MIN(setup->totalmem, 0xd00)) > 0xd00)
1353 tolm = 0xd00;
1354
1355 tolm <<= 4;
1356 printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
1357 pci_write_config16(dev16, I5000_TOLM, tolm);
1358 return 0;
1359 }
1360
1361 static void i5000_init_setup(struct i5000_fbd_setup *setup)
1362 {
1363 int branch, channel, dimm, i = 0;
1364 struct i5000_fbdimm *d;
1365 struct i5000_fbd_channel *c;
1366 struct i5000_fbd_branch *b;
1367
1368 setup->bl = 3;
1369 /* default to highest memory frequency. If a module doesn't
1370 support it, it will decrease this setting in spd_read */
1371 setup->ddr_speed = DDR_667MHZ;
1372
1373 for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
1374 b = setup->branch + branch;
1375 b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
1376 b->setup = setup;
1377 b->num = branch;
1378
1379 for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
1380 c = b->channel + channel;
1381 c->branch = b;
1382 c->setup = setup;
1383 c->num = channel;
1384
1385 for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
1386 d = c->dimm + dimm;
1387 setup->dimms[i++] = d;
1388 d->channel = c;
1389 d->branch = b;
1390 d->setup = setup;
1391 d->num = dimm;
1392 d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
1393 }
1394 }
1395 }
1396 }
1397
1398 static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
1399 {
1400 /* register write captured from vendor BIOS, but undocument by Intel */
1401 pci_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
1402
1403 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
1404 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
1405 pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
1406 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
1407 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
1408
1409 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
1410 pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
1411 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
1412 pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
1413 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
1414
1415 pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
1416 pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
1417 pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
1418 pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
1419
1420 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
1421 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
1422 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
1423 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
1424 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
1425
1426 pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
1427 pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
1428
1429 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
1430 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
1431
1432 pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
1433 pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
1434 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
1435 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
1436 pci_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
1437 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
1438 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
1439 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
1440 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
1441 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
1442 pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
1443 pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
1444 pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
1445
1446 if (setup->branch[0].channel[0].used)
1447 pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
1448
1449 if (setup->branch[0].channel[1].used)
1450 pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
1451
1452 if (setup->branch[1].channel[0].used)
1453 pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
1454
1455 if (setup->branch[1].channel[1].used)
1456 pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
1457 }
1458 static void i5000_dump_error_registers(void)
1459 {
1460 device_t dev = PCI_ADDR(0, 16, 1, 0);
1461
1462 printk(BIOS_ERR, "Dump of FBD error registers:\n"
1463 "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
1464 "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n"
1465 "EMASK_FBD: 0x%08x\n"
1466 "ERR0_FBD: 0x%08x\n"
1467 "ERR1_FBD: 0x%08x\n"
1468 "ERR2_FBD: 0x%08x\n"
1469 "MC_ERR_FBD: 0x%08x\n",
1470 pci_read_config32(dev, I5000_FERR_FAT_FBD),
1471 pci_read_config32(dev, I5000_NERR_FAT_FBD),
1472 pci_read_config32(dev, I5000_FERR_NF_FBD),
1473 pci_read_config32(dev, I5000_NERR_NF_FBD),
1474 pci_read_config32(dev, I5000_EMASK_FBD),
1475 pci_read_config32(dev, I5000_ERR0_FBD),
1476 pci_read_config32(dev, I5000_ERR1_FBD),
1477 pci_read_config32(dev, I5000_ERR2_FBD),
1478 pci_read_config32(dev, I5000_MCERR_FBD));
1479
1480 printk(BIOS_ERR, "Non recoverable error registers:\n"
1481 "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n"
1482 "NRECFGLOG: 0x%08x\n",
1483 pci_read_config32(dev, I5000_NRECMEMA),
1484 pci_read_config32(dev, I5000_NRECMEMB),
1485 pci_read_config32(dev, I5000_NRECFGLOG));
1486
1487 printk(BIOS_ERR, "Packet data:\n"
1488 "NRECFBDA: 0x%08x\n"
1489 "NRECFBDB: 0x%08x\n"
1490 "NRECFBDC: 0x%08x\n"
1491 "NRECFBDD: 0x%08x\n"
1492 "NRECFBDE: 0x%08x\n",
1493 pci_read_config32(dev, I5000_NRECFBDA),
1494 pci_read_config32(dev, I5000_NRECFBDB),
1495 pci_read_config32(dev, I5000_NRECFBDC),
1496 pci_read_config32(dev, I5000_NRECFBDD),
1497 pci_read_config32(dev, I5000_NRECFBDE));
1498
1499 printk(BIOS_ERR, "recoverable error registers:\n"
1500 "RECMEMA: 0x%08x RECMEMB: 0x%08x\n"
1501 "RECFGLOG: 0x%08x\n",
1502 pci_read_config32(dev, I5000_RECMEMA),
1503 pci_read_config32(dev, I5000_RECMEMB),
1504 pci_read_config32(dev, I5000_RECFGLOG));
1505
1506 printk(BIOS_ERR, "Packet data:\n"
1507 "RECFBDA: 0x%08x\n"
1508 "RECFBDB: 0x%08x\n"
1509 "RECFBDC: 0x%08x\n"
1510 "RECFBDD: 0x%08x\n"
1511 "RECFBDE: 0x%08x\n",
1512 pci_read_config32(dev, I5000_RECFBDA),
1513 pci_read_config32(dev, I5000_RECFBDB),
1514 pci_read_config32(dev, I5000_RECFBDC),
1515 pci_read_config32(dev, I5000_RECFBDD),
1516 pci_read_config32(dev, I5000_RECFBDE));
1517
1518 }
1519
1520 static void i5000_try_restart(const char *msg)
1521 {
1522 printk(BIOS_INFO, "%s", msg);
1523 i5000_dump_error_registers();
1524 outb(0x06, 0xcf9);
1525 for(;;) asm volatile("hlt");
1526 }
1527
1528 static void i5000_pam_setup(void)
1529 {
1530 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
1531 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
1532 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
1533 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
1534 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
1535 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
1536 pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
1537 }
1538
1539 static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
1540 {
1541 int fbd, fsb, ddrfrq, ddrfrqnow;
1542 msr_t msr;
1543 device_t dev = PCI_ADDR(0, 16, 1, 0);
1544
1545 switch(setup->ddr_speed) {
1546 case DDR_667MHZ:
1547 fbd = 667;
1548 break;
1549 case DDR_533MHZ:
1550 fbd = 533;
1551 break;
1552 default:
1553 printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__);
1554 return 1;
1555 }
1556
1557 /* mainboard specific callback */
1558 if (mainboard_set_fbd_clock(fbd)) {
1559 printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__);
1560 return 1;
1561 }
1562
1563 msr = rdmsr(MSR_FSB_FREQ);
1564
1565 switch(msr.lo & 7) {
1566 case 1:
1567 fsb = 533;
1568 break;
1569 case 4:
1570 fsb = 667;
1571 break;
1572 default:
1573 printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7);
1574 return 1;
1575 }
1576
1577
1578 ddrfrq = pci_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56);
1579 ddrfrqnow = ddrfrq;
1580 ddrfrq &= ~0x3;
1581
1582 if (fsb < fbd)
1583 ddrfrq |= 2;
1584 else if (fsb > fbd)
1585 ddrfrq |= 3;
1586
1587 switch((ddrfrq >> 4) & 3) {
1588 case 0: /* 1:1 mapping */
1589 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff);
1590 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
1591 pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff);
1592 pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
1593 pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00);
1594 pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
1595 pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
1596 break;
1597 case 2: /* 4:5 mapping */
1598 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323);
1599 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400);
1600 pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023);
1601 pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04);
1602 pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08);
1603 pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
1604 pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04);
1605 break;
1606 case 3:
1607 /* 5:4 mapping */
1608 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230);
1609 pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
1610 pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323);
1611 pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
1612 pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02);
1613 pci_write_config8(dev, I5000_GRBUBBLECFG, 0x10);
1614 pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
1615 break;
1616 default:
1617 printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq);
1618 return -1;
1619 }
1620
1621 if (ddrfrq != ddrfrqnow) {
1622 printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n",
1623 ddrfrqnow, ddrfrq);
1624 pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
1625 /* FSB:FBD mapping changed, needs hard reset */
1626 outb(0x06, 0xcf9);
1627 for(;;) asm volatile("hlt");
1628 }
1629 return 0;
1630 }
1631
1632 void i5000_fbdimm_init(void)
1633 {
1634 struct i5000_fbd_setup setup;
1635 u32 mca, mc;
1636
1637 memset(&setup, 0, sizeof(setup));
1638
1639 pci_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
1640
1641 i5000_init_setup(&setup);
1642
1643 pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
1644 pci_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
1645
1646 i5000_clear_fbd_errors();
1647
1648 printk(BIOS_INFO, "detecting memory modules\n");
1649 if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
1650 printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
1651 return;
1652 }
1653
1654 if (i5000_setup_clocking(&setup)) {
1655 printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__);
1656 return;
1657 }
1658
1659 /* posted CAS requires t_AL = t_RCD - 1 */
1660 setup.t_al = setup.t_rcd - 1;
1661
1662 printk(BIOS_DEBUG, "global timing parameters:\n"
1663 "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
1664 "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
1665 setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
1666 setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
1667 setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
1668 setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
1669
1670 setup.single_channel = (!(setup.branch[0].channel[1].used ||
1671 setup.branch[1].channel[0].used ||
1672 setup.branch[1].channel[1].used));
1673
1674 pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
1675 pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
1676
1677 /* enable or disable single channel mode */
1678 mca = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
1679 if (setup.single_channel)
1680 mca |= (1 << 14);
1681 else
1682 mca &= ~(1 << 14);
1683 pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
1684
1685 /*
1686 * i5000 supports burst length 8 only in single channel mode
1687 * so strip BL_BL8 if we're operating in multichannel mode
1688 */
1689
1690 if (!setup.single_channel)
1691 setup.bl &= ~BL_BL8;
1692
1693 if (!setup.bl)
1694 die("No supported burst length found\n");
1695
1696 mc = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
1697 /* disable error checking for training */
1698 pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
1699
1700 printk(BIOS_INFO, "performing fbd link initialization...");
1701 if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
1702 i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
1703 i5000_for_each_branch(&setup, i5000_link_training0) ||
1704 i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
1705 i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
1706 i5000_for_each_branch(&setup, i5000_link_training1)) {
1707 i5000_try_restart("failed\n");
1708 }
1709 printk(BIOS_INFO, "done\n");
1710 printk(BIOS_INFO, "initializing memory...");
1711
1712 if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
1713 i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
1714 i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
1715 i5000_try_restart("failed\n");
1716 }
1717 printk(BIOS_INFO,"done\n");
1718 printk(BIOS_INFO, "clearing memory...");
1719
1720 if (i5000_membist(&setup))
1721 i5000_try_restart("failed\n");
1722 else
1723 printk(BIOS_INFO, "done\n");
1724
1725 if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
1726 i5000_try_restart("failed to enable auto refresh\n");
1727
1728 i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT);
1729 i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT);
1730
1731 if (i5000_for_each_branch(&setup, i5000_link_training0))
1732 i5000_try_restart("Channel training failed\n");
1733
1734 if (setup.branch[0].used)
1735 i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY);
1736
1737 if (setup.branch[1].used)
1738 i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY);
1739
1740 i5000_clear_fbd_errors();
1741
1742 /* enable error checking */
1743 pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
1744
1745 i5000_dram_timing_init(&setup);
1746
1747 i5000_reserved_register_init(&setup);
1748
1749 i5000_pam_setup();
1750
1751 if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
1752 i5000_try_restart("failed to clear error status\n");
1753
1754 if (setup.branch[0].used)
1755 i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
1756
1757 if (setup.branch[1].used)
1758 i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
1759
1760 #if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
1761 if (ram_check_nodie(0x000000, 0x0a0000) ||
1762 ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) {
1763 i5000_try_restart("RAM verification failed");
1764
1765 }
1766 #endif
1767
1768 printk(BIOS_INFO, "Memory initialization finished\n");
1769 }
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