src/soc/intel/quark/romstage/fsp2_0.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2016-2017 Intel Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/early_variables.h>
  17 #include <console/console.h>
  18 #include <cbmem.h>
  19 #include "../chip.h"
  20 #include <cpu/x86/cache.h>
  21 #include <fsp/util.h>
  22 #include <soc/iomap.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/pm.h>
  25 #include <soc/romstage.h>
  26 #include <soc/reg_access.h>
  27 #include <soc/storage_test.h>
  28
  29 asmlinkage void *car_stage_c_entry(void)
  30 {
  31         struct postcar_frame pcf;
  32         bool s3wake;
  33         uintptr_t top_of_ram;
  34         uintptr_t top_of_low_usable_memory;
  35
  36         post_code(0x20);
  37         console_init();
  38
  39         if (IS_ENABLED(CONFIG_STORAGE_TEST)) {
  40                 uint32_t bar;
  41                 pci_devfn_t dev;
  42                 uint32_t previous_bar;
  43                 uint16_t previous_command;
  44
  45                 /* Enable the SD/MMC controller and run the test.  Restore
  46                  * the BAR and command registers upon completion.
  47                  */
  48                 dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC);
  49                 bar = storage_test_init(dev, &previous_bar, &previous_command);
  50                 storage_test(bar, 1);
  51                 storage_test_complete(dev, previous_bar, previous_command);
  52         }
  53
  54         /* Initialize DRAM */
  55         s3wake = fill_power_state() == ACPI_S3;
  56         fsp_memory_init(s3wake);
  57
  58         /* Disable the ROM shadow 0x000e0000 - 0x000fffff */
  59         disable_rom_shadow();
  60
  61         /* Initialize the PCIe bridges */
  62         pcie_init();
  63
  64         if (postcar_frame_init(&pcf, 1*KiB))
  65                 die("Unable to initialize postcar frame.\n");
  66
  67         /* Locate the top of RAM */
  68         top_of_low_usable_memory = (uintptr_t) cbmem_top();
  69         top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
  70
  71         /* Cache postcar and ramstage */
  72         postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB,
  73                 MTRR_TYPE_WRBACK);
  74
  75         /* Cache RMU area */
  76         postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory,
  77                 0x10000, MTRR_TYPE_WRTHROUGH);
  78
  79         /* Cache ESRAM */
  80         postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
  81
  82         /* Cache SPI flash - Write protect not supported */
  83         postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH);
  84
  85         run_postcar_phase(&pcf);
  86         return NULL;
  87 }
  88
  89 static struct chipset_power_state power_state CAR_GLOBAL;
  90
  91 struct chipset_power_state *get_power_state(void)
  92 {
  93         return (struct chipset_power_state *)car_get_var_ptr(&power_state);
  94 }
  95
  96 int fill_power_state(void)
  97 {
  98         struct chipset_power_state *ps = get_power_state();
  99
 100         ps->prev_sleep_state = 0;
 101         printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state);
 102         return ps->prev_sleep_state;
 103 }
 104
 105 void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
 106 {
 107         FSPM_ARCH_UPD *aupd;
 108         const struct device *dev;
 109         const struct soc_intel_quark_config *config;
 110         void *rmu_data;
 111         size_t rmu_data_len;
 112         FSP_M_CONFIG *upd;
 113
 114         /* Clear SMI and wake events */
 115         clear_smi_and_wake_events();
 116
 117         /* Locate the RMU data file in flash */
 118         rmu_data = locate_rmu_file(&rmu_data_len);
 119         if (!rmu_data)
 120                 die("Microcode file (rmu.bin) not found.");
 121
 122         /* Locate the configuration data from devicetree.cb */
 123         dev = dev_find_slot(0, LPC_DEV_FUNC);
 124         if (!dev)
 125                 die("ERROR - LPC device not found!");
 126         config = dev->chip_info;
 127
 128         /* Update the architectural UPD values. */
 129         aupd = &fspm_upd->FspmArchUpd;
 130         aupd->BootLoaderTolumSize = cbmem_overhead_size();
 131         aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize);
 132         aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
 133
 134         /* Display the ESRAM layout */
 135         if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
 136                 printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
 137                 printk(BIOS_SPEW,
 138                         "+-------------------+ 0x80080000 - ESRAM end\n");
 139                 printk(BIOS_SPEW, "| FSP binary        |\n");
 140                 printk(BIOS_SPEW,
 141                         "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n",
 142                         CONFIG_FSP_ESRAM_LOC);
 143                 printk(BIOS_SPEW, "| FSP stack         |\n");
 144                 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
 145                         aupd->StackBase);
 146                 printk(BIOS_SPEW, "|                   |\n");
 147                 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
 148                         _car_relocatable_data_end);
 149                 printk(BIOS_SPEW, "| coreboot data     |\n");
 150                 printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
 151                         _car_stack_end);
 152                 printk(BIOS_SPEW, "| coreboot stack    |\n");
 153                 printk(BIOS_SPEW,
 154                         "+-------------------+ 0x80000000 - ESRAM start\n\n");
 155         }
 156
 157         /* Update the UPD data for MemoryInit */
 158         upd = &fspm_upd->FspmConfig;
 159         upd->AddrMode = config->AddrMode;
 160         upd->ChanMask = config->ChanMask;
 161         upd->ChanWidth = config->ChanWidth;
 162         upd->DramDensity = config->DramDensity;
 163         upd->DramRonVal = config->DramRonVal;
 164         upd->DramRttNomVal = config->DramRttNomVal;
 165         upd->DramRttWrVal = config->DramRttWrVal;
 166         upd->DramSpeed = config->DramSpeed;
 167         upd->DramType = config->DramType;
 168         upd->DramWidth = config->DramWidth;
 169         upd->EccScrubBlkSize = config->EccScrubBlkSize;
 170         upd->EccScrubInterval = config->EccScrubInterval;
 171         upd->Flags = config->Flags;
 172         upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
 173         upd->RankMask = config->RankMask;
 174         upd->RmuBaseAddress = (uintptr_t)rmu_data;
 175         upd->RmuLength = rmu_data_len;
 176         upd->SerialPortWriteChar = console_log_level(BIOS_SPEW)
 177                 ? (uintptr_t)fsp_write_line : 0;
 178         upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
 179                 config->SmmTsegSize : 0;
 180         upd->SocRdOdtVal = config->SocRdOdtVal;
 181         upd->SocWrRonVal = config->SocWrRonVal;
 182         upd->SocWrSlewRate = config->SocWrSlewRate;
 183         upd->SrInt = config->SrInt;
 184         upd->SrTemp = config->SrTemp;
 185         upd->tCL = config->tCL;
 186         upd->tFAW = config->tFAW;
 187         upd->tRAS = config->tRAS;
 188         upd->tRRD = config->tRRD;
 189         upd->tWTR = config->tWTR;
 190 }