src/mainboard/google/zoombini/variants/meowth/devicetree.cb

   1 chip soc/intel/cannonlake
   2
   3         # Deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "1"
   7         register "deep_s5_enable_dc" = "1"
   8
   9         # GPE configuration
  10         # Note that GPE events called out in ASL code rely on this
  11         # route. i.e. If this route changes then the affected GPE
  12         # offset bits also need to be changed.
  13         register "gpe0_dw0" = "PMC_GPP_A"
  14         register "gpe0_dw1" = "PMC_GPP_B"
  15         register "gpe0_dw2" = "PMC_GPP_C"
  16
  17         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  18         register "gen1_dec" = "0x00fc0801"
  19         register "gen2_dec" = "0x000c0201"
  20         # EC memory map range is 0x900-0x9ff
  21         register "gen3_dec" = "0x00fc0901"
  22
  23         device cpu_cluster 0 on
  24                 device lapic 0 on end
  25         end
  26
  27         # FSP configuration
  28         register "SaGv" = "3"
  29         register "FspSkipMpInit" = "1"
  30         register "SmbusEnable" = "1"
  31         register "ScsEmmcEnabled" = "1"
  32         register "ScsEmmcHs400Enabled" = "1"
  33         register "ScsSdCardEnabled" = "1"
  34
  35         # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
  36         # communication before memory is up.
  37         register "gspi[0]" = "{
  38                 .speed_mhz = 1,
  39                 .early_init = 1,
  40         }"
  41
  42         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
  43         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
  44         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
  45         register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  46         register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  47         register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  48         register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  49         register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  50         register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  51         register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
  52
  53         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
  54         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
  55         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
  56         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
  57         register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
  58         register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
  59
  60         device domain 0 on
  61                 device pci 00.0 on  end # Host Bridge
  62                 device pci 02.0 on  end # Integrated Graphics Device
  63                 device pci 04.0 on  end # SA Thermal device
  64                 device pci 12.0 on  end # Thermal Subsystem
  65                 device pci 12.5 off end # UFS SCS
  66                 device pci 12.6 off end # GSPI #2
  67                 device pci 14.0 on  end # USB xHCI
  68                 device pci 14.1 off end # USB xDCI (OTG)
  69                 device pci 14.5 off end # SDCard
  70                 device pci 15.0 on  end # I2C #0
  71                 device pci 15.1 on  end # I2C #1
  72                 device pci 15.2 off end # I2C #2
  73                 device pci 15.3 on  end # I2C #3
  74                 device pci 16.0 on  end # Management Engine Interface 1
  75                 device pci 16.1 off end # Management Engine Interface 2
  76                 device pci 16.2 off end # Management Engine IDE-R
  77                 device pci 16.3 off end # Management Engine KT Redirection
  78                 device pci 16.4 off end # Management Engine Interface 3
  79                 device pci 16.5 off end # Management Engine Interface 4
  80                 device pci 17.0 off end # SATA
  81                 device pci 19.0 on  end # I2C #4
  82                 device pci 19.1 on  end # I2C #5
  83                 device pci 19.2 on  end # UART #2
  84                 device pci 1a.0 on  end # eMMC
  85                 device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
  86                 device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
  87                 device pci 1c.5 off end # PCI Express Port 6
  88                 device pci 1c.6 off end # PCI Express Port 7
  89                 device pci 1c.7 off end # PCI Express Port 8
  90                 device pci 1d.0 off end # PCI Express Port 9
  91                 device pci 1d.1 off end # PCI Express Port 10
  92                 device pci 1d.2 off end # PCI Express Port 11
  93                 device pci 1d.3 off end # PCI Express Port 12
  94                 device pci 1d.4 off end # PCI Express Port 13
  95                 device pci 1d.5 off end # PCI Express Port 14
  96                 device pci 1d.6 off end # PCI Express Port 15
  97                 device pci 1d.7 off end # PCI Express Port 16
  98                 device pci 1e.0 on  end # UART #0
  99                 device pci 1e.1 off end # UART #1
 100                 device pci 1e.2 on
 101                         chip drivers/spi/acpi
 102                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 103                                 register "compat_string" = ""google,cr50""
 104                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)"
 105                                 device spi 0 on end
 106                         end
 107                 end # GSPI #0
 108                 device pci 1e.3 on
 109                         chip drivers/spi/acpi
 110                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 111                                 register "uid" = "1"
 112                                 register "compat_string" = ""google,cros-ec-spi""
 113                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
 114                                 device spi 0 on end
 115                         end
 116                 end # GSPI #1
 117                 device pci 1f.0 on
 118                         chip ec/google/chromeec
 119                                 device pnp 0c09.0 on end
 120                         end
 121                 end # LPC Interface
 122                 device pci 1f.1 on  end # P2SB
 123                 device pci 1f.2 on  end # Power Management Controller
 124                 device pci 1f.3 on  end # Intel HDA
 125                 device pci 1f.4 on  end # SMBus
 126                 device pci 1f.5 on  end # PCH SPI
 127                 device pci 1f.6 off end # GbE
 128         end
 129 end