src/mainboard/google/dedede/variants/baseboard/devicetree.cb

   1 chip soc/intel/jasperlake
   2         device cpu_cluster 0 on
   3                 device lapic 0 on end
   4         end
   5
   6         # GPE configuration
   7         # Note that GPE events called out in ASL code rely on this
   8         # route, i.e., if this route changes then the affected GPE
   9         # offset bits also need to be changed.
  10         # DW0 is used by:
  11         #   - GPP_B3 - TRACKPAD_INT_ODL
  12         #   - GPP_B4 - H1_AP_INT_ODL
  13         # DW1 is used by:
  14         #   - GPP_C12 - AP_PEN_DET_ODL
  15         # DW2 is used by:
  16         #   - GPP_D0 - WWAN_HOST_WAKE
  17         #   - GPP_D3 - WLAN_PCIE_WAKE_ODL
  18         # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
  19         register "pmc_gpe0_dw0" = "GPP_B"
  20         register "pmc_gpe0_dw1" = "GPP_C"
  21         register "pmc_gpe0_dw2" = "GPP_D"
  22
  23         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  24         register "gen1_dec" = "0x00fc0801"
  25         register "gen2_dec" = "0x000c0201"
  26         # EC memory map range is 0x900-0x9ff
  27         register "gen3_dec" = "0x00fc0901"
  28
  29         # USB Port Configuration
  30         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"     # Type-C Port C0
  31         register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"     # Type-C Port C1
  32         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A0
  33         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A Port A1
  34         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # Discrete Bluetooth
  35         register "usb2_ports[5]" = "USB2_PORT_EMPTY"            # Not Used
  36         register "usb2_ports[6]" = "USB2_PORT_EMPTY"            # Not Used
  37         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Integrated Bluetooth
  38
  39         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0
  40         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1
  41         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0
  42         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1
  43         register "usb3_ports[4]" = "USB3_PORT_EMPTY"            # Not Used
  44         register "usb3_ports[5]" = "USB3_PORT_EMPTY"            # Not Used
  45
  46         register "SerialIoI2cMode" = "{
  47                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
  48                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
  49                 [PchSerialIoIndexI2C2]  = PchSerialIoPci,
  50                 [PchSerialIoIndexI2C3]  = PchSerialIoPci,
  51                 [PchSerialIoIndexI2C4]  = PchSerialIoPci,
  52                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
  53         }"
  54
  55         register "SerialIoGSpiMode" = "{
  56                 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
  57                 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
  58                 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
  59         }"
  60
  61         register "SerialIoGSpiCsMode" = "{
  62                 [PchSerialIoIndexGSPI0] = 1,
  63                 [PchSerialIoIndexGSPI1] = 0,
  64                 [PchSerialIoIndexGSPI2] = 0,
  65         }"
  66
  67         register "SerialIoGSpiCsState" = "{
  68                 [PchSerialIoIndexGSPI0] = 0,
  69                 [PchSerialIoIndexGSPI1] = 0,
  70                 [PchSerialIoIndexGSPI2] = 0,
  71         }"
  72
  73         register "SerialIoUartMode" = "{
  74                 [PchSerialIoIndexUART0] = PchSerialIoDisabled,
  75                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
  76                 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
  77         }"
  78
  79         # PCIE Root Port Configuration
  80         register "PcieRpEnable[0]" = "0"
  81         register "PcieRpEnable[1]" = "0"
  82         register "PcieRpEnable[2]" = "0"
  83         register "PcieRpEnable[3]" = "0"
  84         register "PcieRpEnable[4]" = "0"
  85         register "PcieRpEnable[5]" = "0"
  86         register "PcieRpEnable[6]" = "0"
  87         # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN.
  88         register "PcieRpEnable[7]" = "1"
  89
  90         register "PcieClkSrcUsage[0]" = "0xff"
  91         register "PcieClkSrcUsage[1]" = "0xff"
  92         register "PcieClkSrcUsage[2]" = "0xff"
  93         # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7)
  94         register "PcieClkSrcUsage[3]" = "7"
  95         register "PcieClkSrcUsage[4]" = "0xff"
  96         register "PcieClkSrcUsage[5]" = "0xff"
  97
  98         # PCIE Clock Request to Clock Source Mapping
  99         register "PcieClkSrcClkReq[0]" = "0"
 100         register "PcieClkSrcClkReq[1]" = "1"
 101         register "PcieClkSrcClkReq[2]" = "2"
 102         register "PcieClkSrcClkReq[3]" = "3"
 103         register "PcieClkSrcClkReq[4]" = "4"
 104         register "PcieClkSrcClkReq[5]" = "5"
 105
 106         # Audio related configurations
 107         register "PchHdaDspEnable" = "1"
 108         register "PchHdaAudioLinkHdaEnable" = "1"
 109         register "PchHdaAudioLinkSspEnable[0]" = "1"
 110         register "PchHdaAudioLinkSspEnable[1]" = "1"
 111         register "PchHdaAudioLinkDmicEnable[0]" = "1"
 112         register "PchHdaAudioLinkDmicEnable[1]" = "1"
 113
 114         # Enable EMMC HS400 mode
 115         register "ScsEmmcHs400Enabled" = "1"
 116
 117         # GPIO for SD card detect
 118         register "sdcard_cd_gpio" = "VGPIO_39"
 119         # SD card power enable polarity
 120         register "SdCardPowerEnableActiveHigh" = "1"
 121
 122         # Enable S0ix support
 123         register "s0ix_enable" = "1"
 124
 125         # Display related UPDs
 126         # Select eDP for port A
 127         register "DdiPortAConfig" = "1"
 128
 129         # Disable PM to allow for shorter irq pulses
 130         register "gpio_override_pm" = "1"
 131         register "gpio_pm[0]" = "0"
 132         register "gpio_pm[1]" = "0"
 133         register "gpio_pm[2]" = "0"
 134         register "gpio_pm[3]" = "0"
 135         register "gpio_pm[4]" = "0"
 136
 137         # Enable HPD for DDI ports B/C
 138         register "DdiPortBHpd" = "1"
 139         register "DdiPortCHpd" = "1"
 140         # Enable DDC for DDI ports B/C
 141         register "DdiPortBDdc" = "1"
 142         register "DdiPortCDdc" = "1"
 143
 144         # Enable Speed Shift Technology support
 145         register "speed_shift_enable" = "1"
 146
 147         # Enable DPTF
 148         register "dptf_enable" = "1"
 149
 150         register "power_limits_config" = "{
 151                 .tdp_pl1_override = 6,
 152                 .tdp_pl2_override = 20,
 153         }"
 154
 155         # Enable processor thermal control
 156         register "Device4Enable" = "1"
 157
 158         register "tcc_offset" = "10"     # TCC of 90C
 159
 160         # chipset_lockdown configuration
 161         # Use below format to override value in overridetree.cb if required
 162         # format:
 163         # register "common_soc_config.<variable_name>" = "value"
 164         register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
 165
 166         # Skip the CPU repalcement check
 167         register "SkipCpuReplacementCheck" = "1"
 168
 169         # Set the minimum assertion width
 170         register "PchPmSlpS3MinAssert"  = "3"  # 50ms
 171         register "PchPmSlpS4MinAssert"  = "1"  # 1s
 172         register "PchPmSlpSusMinAssert" = "3"  # 1s
 173         register "PchPmSlpAMinAssert"   = "3"  # 98ms
 174
 175         # NOTE: Duration programmed in the below register should never be smaller than the
 176         # stretch duration programmed in the following registers -
 177         #       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
 178         #       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
 179         #       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
 180         #       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 181         register "PchPmPwrCycDur" = "1"       # 1s
 182
 183         device domain 0 on
 184                 device pci 00.0 on end # Host Bridge
 185                 device pci 02.0 on end # Integrated Graphics Device
 186                 device pci 04.0 on
 187                         chip drivers/intel/dptf
 188                                 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           90, 10000)"
 189                                 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)"
 190                                 register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)"
 191
 192                                 register "policies.critical[0]" = "DPTF_CRITICAL(CPU,           105, SHUTDOWN)"
 193                                 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)"
 194                                 register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)"
 195
 196                                 register "controls.power_limits.pl1" = "{
 197                                         .min_power = 3000,
 198                                         .max_power = 6000,
 199                                         .time_window_min = 1 * MSECS_PER_SEC,
 200                                         .time_window_max = 1 * MSECS_PER_SEC,
 201                                         .granularity = 200,}"
 202                                 register "controls.power_limits.pl2" = "{
 203                                         .min_power = 6000,
 204                                         .max_power = 20000,
 205                                         .time_window_min = 1 * MSECS_PER_SEC,
 206                                         .time_window_max = 1 * MSECS_PER_SEC,
 207                                         .granularity = 1000,}"
 208
 209                                 register "options.tsr[0].desc" = ""Memory""
 210                                 register "options.tsr[1].desc" = ""Ambient""
 211
 212                                 device generic 0 on end
 213                         end
 214                 end # SA Thermal device
 215                 device pci 05.0 off end # IPU
 216                 device pci 09.0 off end # Intel Trace Hub
 217                 device pci 12.6 off end # GSPI 2
 218                 device pci 14.0 on
 219                         chip drivers/usb/acpi
 220                                 register "desc" = ""Root Hub""
 221                                 register "type" = "UPC_TYPE_HUB"
 222                                 device usb 0.0 on
 223                                         chip drivers/usb/acpi
 224                                                 register "desc" = ""Left Type-C Port""
 225                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 226                                                 register "group" = "ACPI_PLD_GROUP(1, 1)"
 227                                                 device usb 2.0 on end
 228                                         end
 229                                         chip drivers/usb/acpi
 230                                                 register "desc" = ""Right Type-C Port""
 231                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 232                                                 register "group" = "ACPI_PLD_GROUP(2, 1)"
 233                                                 device usb 2.1 on end
 234                                         end
 235                                         chip drivers/usb/acpi
 236                                                 register "desc" = ""Left Type-A Port""
 237                                                 register "type" = "UPC_TYPE_A"
 238                                                 register "group" = "ACPI_PLD_GROUP(1, 2)"
 239                                                 device usb 2.2 on end
 240                                         end
 241                                         chip drivers/usb/acpi
 242                                                 register "desc" = ""Right Type-A Port""
 243                                                 register "type" = "UPC_TYPE_A"
 244                                                 register "group" = "ACPI_PLD_GROUP(2, 2)"
 245                                                 device usb 2.3 on end
 246                                         end
 247                                         chip drivers/usb/acpi
 248                                                 device usb 2.4 off end
 249                                         end
 250                                         chip drivers/usb/acpi
 251                                                 device usb 2.5 off end
 252                                         end
 253                                         chip drivers/usb/acpi
 254                                                 device usb 2.6 off end
 255                                         end
 256                                         chip drivers/usb/acpi
 257                                                 register "desc" = ""Bluetooth""
 258                                                 register "type" = "UPC_TYPE_INTERNAL"
 259                                                 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
 260                                                 device usb 2.7 on end
 261                                         end
 262                                         chip drivers/usb/acpi
 263                                                 register "desc" = ""Left Type-C Port""
 264                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 265                                                 register "group" = "ACPI_PLD_GROUP(1, 1)"
 266                                                 device usb 3.0 on end
 267                                         end
 268                                         chip drivers/usb/acpi
 269                                                 register "desc" = ""Right Type-C Port""
 270                                                 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
 271                                                 register "group" = "ACPI_PLD_GROUP(2, 1)"
 272                                                 device usb 3.1 on end
 273                                         end
 274                                         chip drivers/usb/acpi
 275                                                 register "desc" = ""Left Type-A Port""
 276                                                 register "type" = "UPC_TYPE_USB3_A"
 277                                                 register "group" = "ACPI_PLD_GROUP(1, 2)"
 278                                                 device usb 3.2 on end
 279                                         end
 280                                         chip drivers/usb/acpi
 281                                                 register "desc" = ""Right Type-A Port""
 282                                                 register "type" = "UPC_TYPE_USB3_A"
 283                                                 register "group" = "ACPI_PLD_GROUP(2, 2)"
 284                                                 device usb 3.3 on end
 285                                         end
 286                                 end
 287                         end
 288                 end # USB xHCI
 289                 device pci 14.1 off end # USB xDCI (OTG)
 290                 device pci 14.2 off end # PMC SRAM
 291                 chip drivers/intel/wifi
 292                         register "wake" = "GPE0_PME_B0"
 293                         device pci 14.3 on  end # CNVi wifi
 294                 end
 295                 device pci 14.5 on  end # SDCard
 296                 device pci 15.0 on  end # I2C 0
 297                 device pci 15.1 on  end # I2C 1
 298                 device pci 15.2 on  end # I2C 2
 299                 device pci 15.3 on  end # I2C 3
 300                 device pci 16.0 on  end # HECI 1
 301                 device pci 16.1 off end # HECI 2
 302                 device pci 16.4 off end # HECI 3
 303                 device pci 16.5 off end # HECI 4
 304                 device pci 17.0 off end # SATA
 305                 device pci 19.0 on  end # I2C 4
 306                 device pci 19.1 off end # I2C 5
 307                 device pci 19.2 on  end # UART 2
 308                 device pci 1a.0 on  end # eMMC
 309                 device pci 1c.0 off end # PCI Express Root Port 1
 310                 device pci 1c.1 off end # PCI Express Root Port 2
 311                 device pci 1c.2 off end # PCI Express Root Port 3
 312                 device pci 1c.3 off end # PCI Express Root Port 4
 313                 device pci 1c.4 off end # PCI Express Root Port 5
 314                 device pci 1c.5 off end # PCI Express Root Port 6
 315                 device pci 1c.6 off end # PCI Express Root Port 7
 316                 # External PCIe port 4 is mapped to PCIe Root port 8
 317                 device pci 1c.7 on  end # PCI Express Root Port 8 - WLAN
 318                 device pci 1e.0 off end # UART 0
 319                 device pci 1e.1 off end # UART 1
 320                 device pci 1e.2 on
 321                         chip drivers/spi/acpi
 322                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 323                                 register "compat_string" = ""google,cr50""
 324                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
 325                                 device spi 0 on end
 326                         end
 327                 end # GSPI 0
 328                 device pci 1e.3 off end # GSPI 1
 329                 device pci 1f.0 on
 330                         chip ec/google/chromeec
 331                                 device pnp 0c09.0 on end
 332                         end
 333                 end # eSPI Interface
 334                 device pci 1f.1 on  end # P2SB
 335                 device pci 1f.2 hidden end # Power Management Controller
 336                 device pci 1f.3 off end # Intel HDA/cAVS
 337                 device pci 1f.4 off end # SMBus
 338                 device pci 1f.5 on  end # PCH SPI
 339                 device pci 1f.7 off end # Intel Trace Hub
 340         end
 341 end