src/northbridge/intel/fsp_sandybridge/udelay.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <delay.h>
  17 #include <stdint.h>
  18 #include <cpu/x86/tsc.h>
  19 #include <cpu/x86/msr.h>
  20
  21 /**
  22  * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz
  23  */
  24
  25 void udelay(u32 us)
  26 {
  27         u32 dword;
  28         tsc_t tsc, tsc1, tscd;
  29         msr_t msr;
  30         u32 fsb = 100, divisor;
  31         u32 d;                  /* ticks per us */
  32
  33         msr = rdmsr(0xce);
  34         divisor = (msr.lo >> 8) & 0xff;
  35
  36         d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
  37         multiply_to_tsc(&tscd, us, d);
  38
  39         tsc1 = rdtsc();
  40         dword = tsc1.lo + tscd.lo;
  41         if ((dword < tsc1.lo) || (dword < tscd.lo)) {
  42                 tsc1.hi++;
  43         }
  44         tsc1.lo = dword;
  45         tsc1.hi += tscd.hi;
  46
  47         do {
  48                 tsc = rdtsc();
  49         } while ((tsc.hi < tsc1.hi)
  50                  || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
  51 }