src/northbridge/intel/fsp_sandybridge/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <string.h>
  18 #include <arch/io.h>
  19 #include <cbmem.h>
  20 #include <device/pci_def.h>
  21 #include "raminit.h"
  22 #include "northbridge.h"
  23
  24 static const char* ecc_decoder[] = {
  25         "inactive",
  26         "active on IO",
  27         "disabled on IO",
  28         "active"
  29 };
  30
  31 /*
  32  * Dump in the log memory controller configuration as read from the memory
  33  * controller registers.
  34  */
  35 void report_memory_config(void)
  36 {
  37         u32 addr_decoder_common, addr_decode_ch[2];
  38         int i;
  39
  40         addr_decoder_common = MCHBAR32(0x5000);
  41         addr_decode_ch[0] = MCHBAR32(0x5004);
  42         addr_decode_ch[1] = MCHBAR32(0x5008);
  43
  44         printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
  45                (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
  46         printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
  47                addr_decoder_common & 3,
  48                (addr_decoder_common >> 2) & 3,
  49                (addr_decoder_common >> 4) & 3);
  50
  51         for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
  52                 u32 ch_conf = addr_decode_ch[i];
  53                 printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
  54                        i, ch_conf);
  55                 printk(BIOS_DEBUG, "   ECC %s\n",
  56                        ecc_decoder[(ch_conf >> 24) & 3]);
  57                 printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
  58                        ((ch_conf >> 22) & 1) ? "on" : "off");
  59                 printk(BIOS_DEBUG, "   rank interleave %s\n",
  60                        ((ch_conf >> 21) & 1) ? "on" : "off");
  61                 printk(BIOS_DEBUG, "   DIMMA %d MB width x%d %s rank%s\n",
  62                        ((ch_conf >> 0) & 0xff) * 256,
  63                        ((ch_conf >> 19) & 1) ? 16 : 8,
  64                        ((ch_conf >> 17) & 1) ? "dual" : "single",
  65                        ((ch_conf >> 16) & 1) ? "" : ", selected");
  66                 printk(BIOS_DEBUG, "   DIMMB %d MB width x%d %s rank%s\n",
  67                        ((ch_conf >> 8) & 0xff) * 256,
  68                        ((ch_conf >> 20) & 1) ? 16 : 8,
  69                        ((ch_conf >> 18) & 1) ? "dual" : "single",
  70                        ((ch_conf >> 16) & 1) ? ", selected" : "");
  71         }
  72 }