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nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>
[coreboot.git] / src / northbridge / intel / fsp_sandybridge / northbridge.c
bloba565b8de3ed0ccaf877ca1d6643cfbed7fd018f3
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <console/console.h>
19 #include <arch/acpi.h>
20 #include <arch/io.h>
21 #include <stdint.h>
22 #include <delay.h>
23 #include <cpu/intel/fsp_model_206ax/model_206ax.h>
24 #include <cpu/x86/msr.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <stdlib.h>
29 #include <string.h>
30 #include <cpu/cpu.h>
31 #include <cbmem.h>
32 #include "chip.h"
33 #include "northbridge.h"
34 #include <fsp_util.h>
35 #include <cpu/intel/smm/gen1/smi.h>
36
37 static int bridge_revision_id = -1;
38
39 /* IGD UMA memory */
40 static uint64_t uma_memory_base = 0;
41 static uint64_t uma_memory_size = 0;
42
43 int bridge_silicon_revision(void)
44 {
45 if (bridge_revision_id < 0) {
46 uint8_t stepping = cpuid_eax(1) & 0xf;
47 uint8_t bridge_id = pci_read_config16(
48 dev_find_slot(0, PCI_DEVFN(0, 0)),
49 PCI_DEVICE_ID) & 0xf0;
50 bridge_revision_id = bridge_id | stepping;
51 }
52 return bridge_revision_id;
53 }
54
55 /* Reserve everything between A segment and 1MB:
56 *
57 * 0xa0000 - 0xbffff: legacy VGA
58 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
59 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
60 */
61 static const int legacy_hole_base_k = 0xa0000 / 1024;
62 static const int legacy_hole_size_k = 384;
63
64 static int get_pcie_bar(u32 *base)
65 {
66 device_t dev;
67 u32 pciexbar_reg;
68
69 *base = 0;
70
71 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
72 if (!dev)
73 return 0;
74
75 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
76
77 if (!(pciexbar_reg & (1 << 0)))
78 return 0;
79
80 switch ((pciexbar_reg >> 1) & 3) {
81 case 0: // 256MB
82 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
83 return 256;
84 case 1: // 128M
85 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
86 return 128;
87 case 2: // 64M
88 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
89 return 64;
90 }
91
92 return 0;
93 }
94
95 static void add_fixed_resources(struct device *dev, int index)
96 {
97 mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
98
99 mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
100 }
101
102 static void pci_domain_set_resources(device_t dev)
103 {
104 uint64_t tom, me_base, touud;
105 uint32_t tseg_base, uma_size, tolud;
106 uint16_t ggc;
107 unsigned long long tomk;
108
109 tomk = ggc = tseg_base = uma_size = tolud = tom = me_base = touud = 0;
110
111 /* Total Memory 2GB example:
112 *
113 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
114 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
115 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
116 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
117 * 7f200000 2034MB TOLUD
118 * 7f800000 2040MB MEBASE
119 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
120 * 80000000 2048MB TOM
121 * 100000000 4096MB-4102MB 6MB RAM (writeback)
122 *
123 * Total Memory 4GB example:
124 *
125 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
126 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
127 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
128 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
129 * afa00000 2810MB TOLUD
130 * ff800000 4088MB MEBASE
131 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
132 * 100000000 4096MB TOM
133 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
134 * 14fe00000 5368MB TOUUD
135 */
136
137 /* Top of Upper Usable DRAM, including remap */
138 touud = pci_read_config32(dev, TOUUD+4);
139 touud <<= 32;
140 touud |= pci_read_config32(dev, TOUUD) & ~(1UL << 0);
141
142 /* Top of Lower Usable DRAM */
143 tolud = pci_read_config32(dev, TOLUD) & ~(1UL << 0);
144
145 /* Top of Memory - does not account for any UMA */
146 tom = pci_read_config32(dev, 0xa4);
147 tom <<= 32;
148 tom |= pci_read_config32(dev, 0xa0) & ~(1UL << 0);
149
150 printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
151 touud, tolud, tom);
152
153 /* ME UMA needs excluding if total memory <4GB */
154 me_base = pci_read_config32(dev, 0x74);
155 me_base <<= 32;
156 me_base |= pci_read_config32(dev, 0x70);
157
158 printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);
159
160 tomk = tolud >> 10;
161 if (me_base == tolud) {
162 /* ME is from MEBASE-TOM */
163 uma_size = (tom - me_base) >> 10;
164 /* Increment TOLUD to account for ME as RAM */
165 tolud += uma_size << 10;
166 /* UMA starts at old TOLUD */
167 uma_memory_base = tomk * 1024ULL;
168 uma_memory_size = uma_size * 1024ULL;
169 printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
170 me_base, uma_size >> 10);
171 }
172
173 /* Graphics memory comes next */
174 ggc = pci_read_config16(dev, GGC);
175 if (!(ggc & 2)) {
176 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
177
178 /* Graphics memory */
179 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
180 printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
181 tomk -= uma_size;
182 uma_memory_base = tomk * 1024ULL;
183 uma_memory_size += uma_size * 1024ULL;
184
185 /* GTT Graphics Stolen Memory Size (GGMS) */
186 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
187 tomk -= uma_size;
188 uma_memory_base = tomk * 1024ULL;
189 uma_memory_size += uma_size * 1024ULL;
190 printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
191 }
192
193 /* Calculate TSEG size from its base which must be below GTT */
194 uma_memory_base = tomk * 1024ULL;
195 tseg_base = pci_read_config32(dev, 0xb8) & ~(1UL << 0);
196 uma_size = (uma_memory_base - tseg_base) >> 10;
197 tomk -= uma_size;
198 uma_memory_base = tomk * 1024ULL;
199 uma_memory_size += uma_size * 1024ULL;
200 printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n",
201 tseg_base, uma_size >> 10);
202
203 printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
204
205 /* Report the memory regions */
206 ram_resource(dev, 3, 0, legacy_hole_base_k);
207 ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
208 (tomk - (legacy_hole_base_k + legacy_hole_size_k)));
209
210 /*
211 * If >= 4GB installed then memory from TOLUD to 4GB
212 * is remapped above TOM, TOUUD will account for both
213 */
214 touud >>= 10; /* Convert to KB */
215 if (touud > 4096 * 1024) {
216 ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
217 printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
218 (touud >> 10) - 4096);
219 }
220
221 add_fixed_resources(dev, 6);
222
223 assign_resources(dev->link_list);
224 }
225
226 /* TODO We could determine how many PCIe busses we need in
227 * the bar. For now that number is hardcoded to a max of 64.
228 * See e7525/northbridge.c for an example.
229 */
230 static struct device_operations pci_domain_ops = {
231 .read_resources = pci_domain_read_resources,
232 .set_resources = pci_domain_set_resources,
233 .enable_resources = NULL,
234 .init = NULL,
235 .scan_bus = pci_domain_scan_bus,
236 .ops_pci_bus = pci_bus_default_ops,
237 };
238
239 static void mc_read_resources(device_t dev)
240 {
241 u32 pcie_config_base;
242 int buses;
243
244 pci_dev_read_resources(dev);
245
246 buses = get_pcie_bar(&pcie_config_base);
247 if (buses) {
248 struct resource *resource = new_resource(dev, PCIEXBAR);
249 mmconf_resource_init(resource, pcie_config_base, buses);
250 }
251 }
252
253 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
254 {
255 if (!vendor || !device) {
256 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
257 pci_read_config32(dev, PCI_VENDOR_ID));
258 } else {
259 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
260 ((device & 0xffff) << 16) | (vendor & 0xffff));
261 }
262 }
263
264 static void northbridge_init(struct device *dev)
265 {
266 u8 bios_reset_cpl;
267
268 /*
269 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
270 * that BIOS has initialized memory and power management
271 */
272 bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
273 bios_reset_cpl |= 1;
274 MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
275 printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
276 }
277
278 static u32 northbridge_get_base_reg(device_t dev, int reg)
279 {
280 u32 value;
281
282 value = pci_read_config32(dev, reg);
283 /* Base registers are at 1MiB granularity. */
284 value &= ~((1 << 20) - 1);
285 return value;
286 }
287
288 u32 northbridge_get_tseg_base(void)
289 {
290 const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
291
292 return northbridge_get_base_reg(dev, TSEG);
293 }
294
295 void northbridge_write_smram(u8 smram)
296 {
297 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
298 }
299
300 static struct pci_operations intel_pci_ops = {
301 .set_subsystem = intel_set_subsystem,
302 };
303
304 static struct device_operations mc_ops = {
305 .read_resources = mc_read_resources,
306 .set_resources = pci_dev_set_resources,
307 .enable_resources = pci_dev_enable_resources,
308 .init = northbridge_init,
309 .scan_bus = 0,
310 .ops_pci = &intel_pci_ops,
311 .acpi_fill_ssdt_generator = generate_cpu_entries,
312 };
313
314 static const struct pci_driver mc_driver_0100 __pci_driver = {
315 .ops = &mc_ops,
316 .vendor = PCI_VENDOR_ID_INTEL,
317 .device = 0x0100,
318 };
319
320 static const struct pci_driver mc_driver __pci_driver = {
321 .ops = &mc_ops,
322 .vendor = PCI_VENDOR_ID_INTEL,
323 .device = 0x0104, /* Sandy bridge */
324 };
325
326 static const struct pci_driver mc_driver_1 __pci_driver = {
327 .ops = &mc_ops,
328 .vendor = PCI_VENDOR_ID_INTEL,
329 .device = 0x0154, /* Ivy bridge */
330 };
331
332 static void cpu_bus_init(device_t dev)
333 {
334 initialize_cpus(dev->link_list);
335 }
336
337 static struct device_operations cpu_bus_ops = {
338 .read_resources = DEVICE_NOOP,
339 .set_resources = DEVICE_NOOP,
340 .enable_resources = DEVICE_NOOP,
341 .init = cpu_bus_init,
342 .scan_bus = 0,
343 };
344
345 static void enable_dev(device_t dev)
346 {
347 /* Set the operations if it is a special bus type */
348 if (dev->path.type == DEVICE_PATH_DOMAIN) {
349 dev->ops = &pci_domain_ops;
350 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
351 dev->ops = &cpu_bus_ops;
352 }
353 }
354
355 struct chip_operations northbridge_intel_fsp_sandybridge_ops = {
356 CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")
357 .enable_dev = enable_dev,
358 };
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