src/northbridge/intel/fsp_sandybridge/finalize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <stdlib.h>
  19 #include "northbridge.h"
  20
  21 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)
  22
  23 void intel_sandybridge_finalize_smm(void)
  24 {
  25         pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);     /* GGC */
  26         pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);     /* DPR */
  27         pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);    /* ME */
  28         pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);     /* REMAPBASE */
  29         pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);     /* REMAPLIMIT */
  30         pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);     /* TOM */
  31         pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);     /* TOUUD */
  32         pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);     /* BDSM */
  33         pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0);     /* BGSM */
  34         pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0);     /* TSEGMB */
  35         pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0);     /* TOLUD */
  36
  37         MCHBAR32_OR(0x5500, 1 << 0);    /* PAVP */
  38         MCHBAR32_OR(0x5f00, 1 << 31);   /* SA PM */
  39         MCHBAR32_OR(0x6020, 1 << 0);    /* UMA GFX */
  40         MCHBAR32_OR(0x63fc, 1 << 0);    /* VTDTRK */
  41         MCHBAR32_OR(0x6800, 1 << 31);
  42         MCHBAR32_OR(0x7000, 1 << 31);
  43         MCHBAR32_OR(0x77fc, 1 << 0);
  44
  45         /* Memory Controller Lockdown */
  46         MCHBAR8(0x50fc) = 0x8f;
  47
  48         /* Read+write the following */
  49         MCHBAR32(0x6030) = MCHBAR32(0x6030);
  50         MCHBAR32(0x6034) = MCHBAR32(0x6034);
  51         MCHBAR32(0x6008) = MCHBAR32(0x6008);
  52 }