src/mainboard/google/oak/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2015 MediaTek Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <boardid.h>
  17 #include <bootblock_common.h>
  18 #include <gpio.h>
  19 #include <device/mmio.h>
  20 #include <soc/gpio.h>
  21 #include <soc/i2c.h>
  22 #include <soc/mt6391.h>
  23 #include <soc/pericfg.h>
  24 #include <soc/spi.h>
  25
  26 #include "gpio.h"
  27
  28 static void i2c_set_gpio_pinmux(void)
  29 {
  30         gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1);
  31         gpio_set_mode(GPIO(SCL1), PAD_SCL1_FUNC_SCL1);
  32         gpio_set_mode(GPIO(SDA4), PAD_SDA4_FUNC_SDA4);
  33         gpio_set_mode(GPIO(SCL4), PAD_SCL4_FUNC_SCL4);
  34 }
  35
  36 static void nor_set_gpio_pinmux(void)
  37 {
  38         /* Set driving strength of EINT4~EINT9 to 8mA
  39          * 0: 2mA
  40          * 1: 4mA
  41          * 2: 8mA
  42          * 3: 16mA
  43          */
  44         /* EINT4: 0x10005B20[14:13] */
  45         clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
  46         /* EINT5~EINT9: 0x10005B30[2:1] */
  47         clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
  48
  49         gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  50         gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  51         gpio_set_pull(GPIO(EINT6), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  52         gpio_set_pull(GPIO(EINT7), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  53         gpio_set_pull(GPIO(EINT8), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  54         gpio_set_pull(GPIO(EINT9), GPIO_PULL_ENABLE, GPIO_PULL_UP);
  55
  56         gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SFWP_B);
  57         gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SFOUT);
  58         gpio_set_mode(GPIO(EINT6), PAD_EINT6_FUNC_SFCS0);
  59         gpio_set_mode(GPIO(EINT7), PAD_EINT7_FUNC_SFHOLD);
  60         gpio_set_mode(GPIO(EINT8), PAD_EINT8_FUNC_SFIN);
  61         gpio_set_mode(GPIO(EINT9), PAD_EINT9_FUNC_SFCK);
  62 }
  63
  64 void bootblock_mainboard_early_init(void)
  65 {
  66         /* Clear UART0 power down signal */
  67         clrbits32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN);
  68 }
  69
  70 void bootblock_mainboard_init(void)
  71 {
  72         /* adjust gpio params when external voltage is 1.8V */
  73         gpio_init(GPIO_EINT_1P8V);
  74
  75         /* set i2c related gpio */
  76         i2c_set_gpio_pinmux();
  77
  78         /* set nor related GPIO */
  79         nor_set_gpio_pinmux();
  80
  81         /* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
  82         if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
  83             board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
  84                 gpio_output(GPIO(SRCLKENAI2), 1);
  85
  86         /* Init i2c bus 2 Timing register for TPM */
  87         mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
  88
  89         if (CONFIG(OAK_HAS_TPM2))
  90                 gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
  91
  92         mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
  93                      0);
  94
  95         setup_chromeos_gpios();
  96
  97         if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 4)
  98                 mt6391_enable_reset_when_ap_resets();
  99 }