src/mainboard/google/nyan_big/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <device/mmio.h>
  17 #include <boot/coreboot_tables.h>
  18 #include <device/device.h>
  19 #include <gpio.h>
  20 #include <soc/addressmap.h>
  21 #include <soc/clk_rst.h>
  22 #include <soc/clock.h>
  23 #include <soc/mc.h>
  24 #include <soc/nvidia/tegra/i2c.h>
  25 #include <soc/pmc.h>
  26 #include <soc/spi.h>
  27 #include <soc/nvidia/tegra/usb.h>
  28 #include <symbols.h>
  29 #include <vendorcode/google/chromeos/chromeos.h>
  30
  31 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
  32
  33 static void set_clock_sources(void)
  34 {
  35         /*
  36          * The max98090 codec and the temperature sensor are on I2C1. These
  37          * can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
  38          */
  39         clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
  40
  41         /*
  42          * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
  43          * maximum speed (48MHz) so we can change SDCLK by second stage divisor
  44          * in payloads, without touching base clock.
  45          */
  46         clock_configure_source(sdmmc3, PLLP, 48000);
  47         clock_configure_source(sdmmc4, PLLP, 48000);
  48
  49         /* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
  50          * Note the source id of CLK_M for EXTPERIPH1 is 3. */
  51         clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
  52
  53         /*
  54          * We need 1.5MHz. So, we use CLK_M. CLK_DIVIDER macro returns a divisor
  55          * (0xe) a little bit off from the ideal value (0xd) but it's good
  56          * enough for beeps. The source id of CLK_M for I2S is 6.
  57          */
  58         clock_configure_irregular_source(i2s1, CLK_M, 1500, 6);
  59
  60         /* Note source id of PLLP for HOST1x is 4. */
  61         clock_configure_irregular_source(host1x, PLLP, 408000, 4);
  62
  63         /* Use PLLD_OUT0 as clock source for disp1 */
  64         clrsetbits32(&clk_rst->clk_src_disp1,
  65                      CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
  66                      2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
  67
  68 }
  69
  70 static void setup_pinmux(void)
  71 {
  72         // I2C1 clock.
  73         pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
  74                           PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
  75         // I2C1 data.
  76         pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
  77                           PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
  78         // I2C2 clock.
  79         pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
  80                           PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE |
  81                           PINMUX_OPEN_DRAIN);
  82         // I2C2 data.
  83         pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
  84                           PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE |
  85                           PINMUX_OPEN_DRAIN);
  86         // I2C4 (DDC) clock.
  87         pinmux_set_config(PINMUX_DDC_SCL_INDEX,
  88                           PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
  89         // I2C4 (DDC) data.
  90         pinmux_set_config(PINMUX_DDC_SDA_INDEX,
  91                           PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
  92
  93         // TODO(hungte) Revice pinmux setup, make nice little SoC functions for
  94         // every single logical thing instead of dumping a wall of code below.
  95         uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
  96                  pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
  97                  pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
  98
  99         // MMC3 (sdcard reader)
 100         pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
 101                           PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
 102         pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
 103                           PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
 104         pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
 105                           PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
 106         pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
 107                           PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
 108         pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
 109                           PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
 110         pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
 111                           PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
 112         pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
 113                           PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up);
 114         pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
 115                           PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
 116
 117         // MMC3 Card Detect pin.
 118         gpio_input_pullup(GPIO(V2));
 119         // Disable SD card reader power so it can be reset even on warm boot.
 120         // Payloads must enable power before accessing SD card slots.
 121         gpio_output(GPIO(R0), 0);
 122
 123         // MMC4 (eMMC)
 124         pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
 125                           PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
 126         pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
 127                           PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
 128         pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
 129                           PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
 130         pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
 131                           PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
 132         pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
 133                           PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
 134         pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
 135                           PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
 136         pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
 137                           PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
 138         pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
 139                           PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
 140         pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
 141                           PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
 142         pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
 143                           PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
 144
 145         /* We pull the USB VBUS signals up but keep them as inputs since the
 146          * voltage source likes to drive them low on overcurrent conditions */
 147         gpio_input_pullup(GPIO(N4));    /* USB VBUS EN0 */
 148         gpio_input_pullup(GPIO(N5));    /* USB VBUS EN1 */
 149
 150         /* Clock output 1 (for external peripheral) */
 151         pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
 152                           PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
 153
 154         /* I2S1 */
 155         pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
 156                           PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 157         pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
 158                           PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 159         pinmux_set_config(PINMUX_DAP2_FS_INDEX,
 160                           PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 161         pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
 162                           PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 163
 164         /* PWM1 */
 165         pinmux_set_config(PINMUX_GPIO_PH1_INDEX,
 166                           PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE);
 167
 168          /* DP HPD */
 169         pinmux_set_config(PINMUX_DP_HPD_INDEX,
 170                         PINMUX_DP_HPD_FUNC_DP | PINMUX_INPUT_ENABLE);
 171 }
 172
 173 static void setup_kernel_info(void)
 174 {
 175         // Setup required information for Linux kernel.
 176
 177         // pmc.odmdata: [18:19]: console type, [15:17]: UART id.
 178         // TODO(hungte) This should be done by filling BCT values, or derived
 179         // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
 180         // value defined in BCT.
 181         struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
 182         write32(&pmc->odmdata, 0x80080000);
 183
 184         // Not strictly info, but kernel graphics driver needs this region locked down
 185         struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
 186         write32(&mc->video_protect_bom, 0);
 187         write32(&mc->video_protect_size_mb, 0);
 188         write32(&mc->video_protect_reg_ctrl, 1);
 189 }
 190
 191 static void setup_ec_spi(void)
 192 {
 193         tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
 194 }
 195
 196 static void mainboard_init(struct device *dev)
 197 {
 198         set_clock_sources();
 199
 200         clock_external_output(1); /* For external MAX98090 audio codec. */
 201
 202         /*
 203          * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
 204          * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
 205          * of reset and clock-enabled, otherwise reading AHUB devices (In our
 206          * case, I2S/APBIF/AUDIO<XBAR>) will hang.
 207          */
 208         clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
 209                                  CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
 210                                  CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
 211                                  CLK_L_HOST1X | CLK_L_PWM,
 212
 213                                  CLK_H_EMC | CLK_H_I2C2 | CLK_H_PMC |
 214                                  CLK_H_MEM | CLK_H_USB3,
 215
 216                                  CLK_U_CSITE | CLK_U_SDMMC3,
 217
 218                                  CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
 219                                  CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
 220                                  CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
 221
 222                                  CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
 223
 224                                  CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
 225                                  CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
 226                                  CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
 227                                  CLK_X_AFC5);
 228
 229         usb_setup_utmip((void*)TEGRA_USBD_BASE);
 230         /* USB2 is the camera, we don't need it in firmware */
 231         usb_setup_utmip((void*)TEGRA_USB3_BASE);
 232
 233         setup_pinmux();
 234
 235         i2c_init(0);
 236         i2c_init(1);
 237         i2c_init(3);
 238
 239         setup_kernel_info();
 240         clock_init_arm_generic_timer();
 241         setup_ec_spi();
 242 }
 243
 244 static void mainboard_enable(struct device *dev)
 245 {
 246         dev->ops->init = &mainboard_init;
 247 }
 248
 249 struct chip_operations mainboard_ops = {
 250         .name   = "nyan_big",
 251         .enable_dev = mainboard_enable,
 252 };
 253
 254 void lb_board(struct lb_header *header)
 255 {
 256         struct lb_range *dma;
 257
 258         dma = (struct lb_range *)lb_new_record(header);
 259         dma->tag = LB_TAG_DMA;
 260         dma->size = sizeof(*dma);
 261         dma->range_start = (uintptr_t)_dma_coherent;
 262         dma->range_size = REGION_SIZE(dma_coherent);
 263 }