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AGESA: Drop unused AGESA_MEM_TABLE
[coreboot.git] / src / mainboard / supermicro / h8qgi / buildOpts.c
blob04e704c5a8348b3aa1dc3c97fced660fa39e067d
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20 #include <stdlib.h>
21
22 #include "AGESA.h"
23 #include "CommonReturns.h"
24 #include "AdvancedApi.h"
25 #include <PlatformMemoryConfiguration.h>
26 #include "Filecode.h"
27 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
28
29 /* AGESA will check the OEM configuration during preprocessing stage,
30 * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
31 */
32 /* MEMORY_BUS_SPEED */
33 #define DDR400_FREQUENCY 200 ///< DDR 400
34 #define DDR533_FREQUENCY 266 ///< DDR 533
35 #define DDR667_FREQUENCY 333 ///< DDR 667
36 #define DDR800_FREQUENCY 400 ///< DDR 800
37 #define DDR1066_FREQUENCY 533 ///< DDR 1066
38 #define DDR1333_FREQUENCY 667 ///< DDR 1333
39 #define DDR1600_FREQUENCY 800 ///< DDR 1600
40 #define DDR1866_FREQUENCY 933 ///< DDR 1866
41 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
42
43 /* QUANDRANK_TYPE*/
44 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
45 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
46
47 /* USER_MEMORY_TIMING_MODE */
48 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
49 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
50 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
51
52 /* POWER_DOWN_MODE */
53 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
54 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
55
56 /* User makes option selections here
57 * Comment out the items wanted to be included in the build.
58 * Uncomment those items you with to REMOVE from the build.
59 */
60 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
61 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
62 //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
63 //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
64 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
65 //#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
66 //#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
67 //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
68 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
69 //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
70 ////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
71 ////#define BLDOPT_REMOVE_SRAT TRUE
72 ////#define BLDOPT_REMOVE_SLIT TRUE
73 //#define BLDOPT_REMOVE_WHEA TRUE
74 //#define BLDOPT_REMOVE_DMI TRUE
75
76 /*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
77 #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
78
79 //#define BLDOPT_REMOVE_HT_ASSIST TRUE
80 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
81 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
82 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
83 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
84 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
85 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
86
87 /* Build configuration values here.
88 */
89 #define BLDCFG_VRM_CURRENT_LIMIT 120000
90 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
91 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
92 #define BLDCFG_PLAT_NUM_IO_APICS 3
93 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
94 #define BLDCFG_MEM_INIT_PSTATE 0
95 #define BLDCFG_AMD_PSTATE_CAP_VALUE 0
96
97 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
98
99 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
100 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
101 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
102 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
103 #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
104 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
105 #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
106 #define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
107 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
108 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
109 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
110 #define BLDCFG_MEMORY_POWER_DOWN FALSE
111 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
112 #define BLDCFG_ONLINE_SPARE FALSE
113 #define BLDCFG_BANK_SWIZZLE TRUE
114 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
115 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
116 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
117 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
118 #define BLDCFG_USE_BURST_MODE FALSE
119 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
120 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
121 #define BLDCFG_ECC_REDIRECTION FALSE
122 #define BLDCFG_SCRUB_IC_RATE 0
123 #define BLDCFG_ECC_SYNC_FLOOD TRUE
124 #define BLDCFG_ECC_SYMBOL_SIZE 4
125
126 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
127 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
128
129 /**
130 * Enable Message Based C1e CPU feature in multi-socket systems.
131 * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
132 * else the feature cannot be enabled.
133 */
134 #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
135 #define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
136 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
137 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
138
139 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
140 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
141 #define BLDCFG_1GB_ALIGN FALSE
142 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
143 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
144 //
145
146 // Select the platform control flow mode for performance tuning.
147 #define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
148
149 /**
150 * Enable the probe filtering performance tuning feature.
151 * The probe filter provides filtering of broadcast probes to
152 * improve link bandwidth and performance for multi- node systems.
153 *
154 * This feature may interact with other performance features.
155 * TRUE -Enable the feature (default) if supported by all processors,
156 * based on revision and presence of L3 cache.
157 * The feature is not enabled if there are no coherent HT links.
158 * FALSE -Do not enable the feature regardless of the configuration.
159 */
160 //TODO enable it,
161 //but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
162 //hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
163 #define BLDCFG_USE_HT_ASSIST FALSE
164
165 /**
166 * The socket and link match values are platform specific
167 */
168 CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
169 {
170 {
171 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
172 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
173
174 { //BUID Swap List
175 { //BUID Swaps
176 /* Each Non-coherent chain may have a list of device swaps,
177 * Each item specify a device will be swap from its current id to a new one
178 */
179 /* FromID 0x00 is the chain with the southbridge */
180 /* 'Move' device zero to device zero, All others are non applicable */
181 {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
182 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
183 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
184 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
185 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
186 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
187 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
188 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
189 },
190
191 { //The ordered final BUIDs
192 /* Specify the final BUID to be zero, All others are non applicable */
193 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
194 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
195 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
196 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
197 }
198 }
199 },
200
201 /* The 2nd element in the array merely terminates the list */
202 {
203 HT_LIST_TERMINAL,
204 }
205 };
206
207 #define HYPERTRANSPORT_V31_SUPPORT 1
208
209 #if HYPERTRANSPORT_V31_SUPPORT
210 /**
211 * The socket and link match values are platform specific
212 *
213 */
214 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
215 {
216 {
217 /* On the reference platform, these settings apply to all coherent links */
218 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
219
220 /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
221 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
222 },
223
224 /* The 2nd element in the array merely terminates the list */
225 {
226 HT_LIST_TERMINAL,
227 }
228 };
229
230 CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
231 {
232 {
233 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
234 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
235
236 /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
237 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
238 },
239
240 /* The 2nd element in the array merely terminates the list */
241 {
242 HT_LIST_TERMINAL,
243 }
244 };
245 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
246 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
247 {
248 {
249 /* On the reference platform, these settings apply to all coherent links */
250 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
251
252 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
253 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
254 },
255
256 /* The 2nd element in the array merely terminates the list */
257 {
258 HT_LIST_TERMINAL,
259 }
260 };
261
262 CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
263 {
264 {
265 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
266 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
267
268 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
269 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
270 },
271
272 /* The 2nd element in the array merely terminates the list */
273 {
274 HT_LIST_TERMINAL
275 }
276 };
277 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
278
279 /**
280 * HyperTransport links will typically require an equalization at high frequencies.
281 * This is called deemphasis.
282 *
283 * Deemphasis is specified as levels, for example, -3 db.
284 * There are two levels for each link, its receiver deemphasis level and its DCV level,
285 * which is based on the far side transmitter's deemphasis.
286 * For each link, different levels may be required at each link frequency.
287 *
288 * Coherent connections between processors should have an entry for the port on each processor.
289 * There should be one entry for the host root port of each non-coherent chain.
290 *
291 * AGESA initialization code does not set deemphasis on IO Devices.
292 * A default is provided for internal links of MCM processors, and
293 * those links will generally not need deemphasis structures.
294 */
295 CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
296 {
297 /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
298
299 /* Non-coherent link deemphasis. */
300 {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
301 {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
302 {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
303 {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
304 {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
305 {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
306
307 {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
308 {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
309 {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
310 {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
311 {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
312 {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
313
314 {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
315 {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
316 {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
317 {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
318 {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
319 {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
320
321 {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
322 {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
323 {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
324 {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
325 {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
326 {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
327
328 /* Coherent link deemphasis. */
329 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
330 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
331 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
332 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
333 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
334 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
335
336 /* End of the list */
337 {
338 HT_LIST_TERMINAL
339 }
340 };
341
342 /**
343 * For systems using socket infrastructure that permits strapping the SBI
344 * address for each socket, this should be used to provide a socket ID value.
345 * This is referred to as the hardware method for socket naming, and is the
346 * preferred solution.
347 */
348 /*
349 * I do NOT know howto config socket id in simnow,
350 * so use this software way to make HT works in simnow,
351 * real hardware do not need this Socket Map.
352 *
353 * A physical socket map for a 4 G34 Sockets MCM processors topology,
354 * reference the mainboard schemantic in detail.
355 *
356 */
357 CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
358 {
359 #define HT_SOCKET0 0
360 #define HT_SOCKET1 1
361 #define HT_SOCKET2 2
362 #define HT_SOCKET3 3
363
364 /**
365 * 0-3 are sublink 0, 4-7 are sublink 1
366 */
367 #define HT_LINK0A 0
368 #define HT_LINK1A 1
369 #define HT_LINK2A 2
370 #define HT_LINK3A 3
371 #define HT_LINK0B 4
372 #define HT_LINK1B 5
373 #define HT_LINK2B 6
374 #define HT_LINK3B 7
375
376 /* Source Socket, Link, Target Socket */
377 {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
378 {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
379 {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
380 {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
381 {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
382 {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
383
384 {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
385 {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
386 {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
387 {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
388 {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
389 {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
390
391 {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
392 {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
393 {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
394 {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
395 {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
396 {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
397
398 {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
399 {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
400 {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
401 {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
402 {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
403 {HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
404 };
405
406 CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
407 {
408 {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
409 {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
410 {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
411 {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000},
412 {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000},
413 {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000},
414 {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000},
415 {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818},
416 {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818},
417 {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818},
418 {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818},
419 {CPU_LIST_TERMINAL}
420 };
421
422 #define BLDCFG_BUID_SWAP_LIST &h8qgi_manual_swaplist
423 #define BLDCFG_HTFABRIC_LIMITS_LIST &h8qgi_cpu2cpu_limit_list
424 #define BLDCFG_HTCHAIN_LIMITS_LIST &h8qgi_io_limit_list
425 #define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8qgi_deemphasis_list
426 #define BLDCFG_AP_MTRR_SETTINGS_LIST &h8qgi_ap_mtrr_list
427 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8qgi_socket_map
428
429
430 /* Process the options...
431 * This file include MUST occur AFTER the user option selection settings
432 */
433 #define AGESA_ENTRY_INIT_RESET TRUE//FALSE
434 #define AGESA_ENTRY_INIT_RECOVERY FALSE
435 #define AGESA_ENTRY_INIT_EARLY TRUE
436 #define AGESA_ENTRY_INIT_POST TRUE
437 #define AGESA_ENTRY_INIT_ENV TRUE
438 #define AGESA_ENTRY_INIT_MID TRUE
439 #define AGESA_ENTRY_INIT_LATE TRUE
440 #define AGESA_ENTRY_INIT_S3SAVE TRUE
441 #define AGESA_ENTRY_INIT_RESUME TRUE
442 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
443 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
444
445 /*
446 #if CONFIG_CPU_AMD_AGESA_FAMILY15
447 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
448 #endif
449 #if CONFIG_CPU_AMD_AGESA_FAMILY10
450 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
451 #endif
452 */
453
454 #include "MaranelloInstall.h"
455
456 /*----------------------------------------------------------------------------------------
457 * CUSTOMER OVERIDES MEMORY TABLE
458 *----------------------------------------------------------------------------------------
459 */
460
461 //reference BKDG Table87: works
462 #define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
463 #define SEED_A 0x54
464 #define SEED_B 0x4D
465 #define SEED_C 0x45
466 #define SEED_D 0x40
467
468 #define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
469 //4B 41 51
470
471 /*
472 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
473 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
474 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
475 * use its default conservative settings.
476 */
477 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
478 //
479 // The following macros are supported (use comma to separate macros):
480 //
481 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
482 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
483 // AGESA will base on this value to disable unused MemClk to save power.
484 // Example:
485 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
486 // Bit AM3/S1g3 pin name
487 // 0 M[B,A]_CLK_H/L[0]
488 // 1 M[B,A]_CLK_H/L[1]
489 // 2 M[B,A]_CLK_H/L[2]
490 // 3 M[B,A]_CLK_H/L[3]
491 // 4 M[B,A]_CLK_H/L[4]
492 // 5 M[B,A]_CLK_H/L[5]
493 // 6 M[B,A]_CLK_H/L[6]
494 // 7 M[B,A]_CLK_H/L[7]
495 // And platform has the following routing:
496 // CS0 M[B,A]_CLK_H/L[4]
497 // CS1 M[B,A]_CLK_H/L[2]
498 // CS2 M[B,A]_CLK_H/L[3]
499 // CS3 M[B,A]_CLK_H/L[5]
500 // Then platform can specify the following macro:
501 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
502 //
503 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
504 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
505 // AGESA will base on this value to tristate unused CKE to save power.
506 //
507 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
508 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
509 // AGESA will base on this value to tristate unused ODT pins to save power.
510 //
511 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
512 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
513 // AGESA will base on this value to tristate unused Chip select to save power.
514 //
515 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
516 // Specifies the number of DIMM slots per channel.
517 //
518 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
519 // Specifies the number of Chip selects per channel.
520 //
521 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
522 // Specifies the number of channels per socket.
523 //
524 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
525 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
526 //
527 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
528 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
529 //
530 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
531 // Byte6Seed, Byte7Seed, ByteEccSeed)
532 // Specifies the write leveling seed for a channel of a socket.
533 //
534
535 /* Specifies the write leveling seed for a channel of a socket.
536 * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
537 * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
538 * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
539 * ByteEccSeed)
540 */
541 WRITE_LEVELING_SEED(
542 ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
543 F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
544 F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
545 F15_WL_SEED),
546
547 /* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
548 * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
549 * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
550 */
551 HW_RXEN_SEED(
552 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
553 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
554 SEED_A),
555 HW_RXEN_SEED(
556 ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
557 SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
558 SEED_B),
559 HW_RXEN_SEED(
560 ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
561 SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
562 SEED_C),
563 HW_RXEN_SEED(
564 ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
565 SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
566 SEED_D),
567
568 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
569 PSO_END
570 };
571
572 /*
573 * These tables are optional and may be used to adjust memory timing settings
574 */
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