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AGESA: Drop unused AGESA_MEM_TABLE
[coreboot.git] / src / mainboard / lippert / toucan-af / buildOpts.c
blob1ac4767c9487c149d5118bcc408cc2e0b1e71e85
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20 /**
21 * @file
22 *
23 * AMD User options selection for a Brazos platform solution system
24 *
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
27 *
28 * For Information about this file, see @ref platforminstall.
29 *
30 */
31
32 #include <stdlib.h>
33
34 #include "Filecode.h"
35 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
36
37
38 /* Select the cpu family. */
39 #define INSTALL_FAMILY_10_SUPPORT FALSE
40 #define INSTALL_FAMILY_12_SUPPORT FALSE
41 #define INSTALL_FAMILY_14_SUPPORT TRUE
42 #define INSTALL_FAMILY_15_SUPPORT FALSE
43
44 /* Select the cpu socket type. */
45 #define INSTALL_G34_SOCKET_SUPPORT FALSE
46 #define INSTALL_C32_SOCKET_SUPPORT FALSE
47 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
48 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
49 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
50 #define INSTALL_FS1_SOCKET_SUPPORT FALSE
51 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
52 #define INSTALL_FP1_SOCKET_SUPPORT FALSE
53 #define INSTALL_FT1_SOCKET_SUPPORT TRUE
54 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
55
56 /*
57 * Agesa optional capabilities selection.
58 * Uncomment and mark FALSE those features you wish to include in the build.
59 * Comment out or mark TRUE those features you want to REMOVE from the build.
60 */
61
62 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
63 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
64 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
65 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
66
67 #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
68 #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
69 #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
70 #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
71 #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
72 #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
73 #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
74 #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
75 #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
76 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
77
78 #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
79 #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
80 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
81 #define BLDOPT_REMOVE_ECC_SUPPORT FALSE
82 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
83 #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
84 #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
85 #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
86 #define BLDOPT_REMOVE_DQS_TRAINING FALSE
87 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
88 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
89 #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
90 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
91 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
92 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
93 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
94 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
95 #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
96 #define BLDOPT_REMOVE_SRAT FALSE
97 #define BLDOPT_REMOVE_SLIT FALSE
98 #define BLDOPT_REMOVE_WHEA FALSE
99 #define BLDOPT_REMOVE_DMI TRUE
100 #define BLDOPT_REMOVE_HT_ASSIST TRUE
101 #define BLDOPT_REMOVE_ATM_MODE TRUE
102 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
103 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
104 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
105 //#define BLDOPT_REMOVE_C6_STATE TRUE
106 #define BLDOPT_REMOVE_GFX_RECOVERY TRUE
107 #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
108
109 /*
110 * Agesa entry points used in this implementation.
111 */
112 #define AGESA_ENTRY_INIT_RESET TRUE
113 #define AGESA_ENTRY_INIT_RECOVERY FALSE
114 #define AGESA_ENTRY_INIT_EARLY TRUE
115 #define AGESA_ENTRY_INIT_POST TRUE
116 #define AGESA_ENTRY_INIT_ENV TRUE
117 #define AGESA_ENTRY_INIT_MID TRUE
118 #define AGESA_ENTRY_INIT_LATE TRUE
119 #define AGESA_ENTRY_INIT_S3SAVE TRUE
120 #define AGESA_ENTRY_INIT_RESUME TRUE
121 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
122 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
123
124 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
125 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
126
127 #define BLDCFG_VRM_CURRENT_LIMIT 24000
128 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
129 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
130 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
131 #define BLDCFG_VRM_SLEW_RATE 5000
132 //#define BLDCFG_VRM_NB_SLEW_RATE 5000
133 //#define BLDCFG_VRM_ADDITIONAL_DELAY 0
134 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
135 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
136 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
137 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
138 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
139
140 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
141 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
142 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
143 #define BLDCFG_PLAT_NUM_IO_APICS 3
144 //#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
145 //#define BLDCFG_PLATFORM_C1E_OPDATA 0
146 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
147 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
148 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
149 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
150 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
151 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
152 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
153 #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
154 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
155 //#define BLDCFG_STARTING_BUSNUM 0
156 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8
157 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20
158 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
159 //#define BLDCFG_BUID_SWAP_LIST 0
160 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
161 //#define BLDCFG_HTFABRIC_LIMITS_LIST 0
162 //#define BLDCFG_HTCHAIN_LIMITS_LIST 0
163 //#define BLDCFG_BUS_NUMBERS_LIST 0
164 //#define BLDCFG_IGNORE_LINK_LIST 0
165 //#define BLDCFG_LINK_SKIP_REGANG_LIST 0
166 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
167 //#define BLDCFG_USE_HT_ASSIST TRUE
168 //#define BLDCFG_USE_ATM_MODE TRUE
169 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
170 #define BLDCFG_S3_LATE_RESTORE TRUE
171 //#define BLDCFG_USE_32_BYTE_REFRESH FALSE
172 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
173 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
174 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
175 //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
176 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
177 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE
178 //#define BLDCFG_CFG_ABM_SUPPORT FALSE
179 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
180 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
181 //#define BLDCFG_MEM_INIT_PSTATE 0
182 //#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
183 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
184 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
185 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
186 //#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
187 #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
188 #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
189 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
190 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
191 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
192 #define BLDCFG_MEMORY_POWER_DOWN TRUE
193 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
194 //#define BLDCFG_ONLINE_SPARE FALSE
195 //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
196 #define BLDCFG_BANK_SWIZZLE TRUE
197 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
198 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
199 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
200 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
201 #define BLDCFG_USE_BURST_MODE FALSE
202 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
203 //#define BLDCFG_ENABLE_ECC_FEATURE TRUE
204 //#define BLDCFG_ECC_REDIRECTION FALSE
205 //#define BLDCFG_SCRUB_DRAM_RATE 0
206 //#define BLDCFG_SCRUB_L2_RATE 0
207 //#define BLDCFG_SCRUB_L3_RATE 0
208 //#define BLDCFG_SCRUB_IC_RATE 0
209 //#define BLDCFG_SCRUB_DC_RATE 0
210 //#define BLDCFG_ECC_SYNC_FLOOD 0
211 //#define BLDCFG_ECC_SYMBOL_SIZE 0
212 //#define BLDCFG_1GB_ALIGN FALSE
213 #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
214 #define BLDCFG_UMA_ALLOCATION_SIZE 0
215 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
216 #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
217 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
218 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
219
220 /*
221 * Agesa configuration values selection.
222 * Uncomment and specify the value for the configuration options
223 * needed by the system.
224 */
225 #include "AGESA.h"
226 #include "CommonReturns.h"
227
228 /* The fixed MTRR values to be set after memory initialization. */
229 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
230 {
231 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
232 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
233 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
234 { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
235 { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
236 { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
237 { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
238 { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
239 { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
240 { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
241 { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
242 { CPU_LIST_TERMINAL }
243 };
244
245 /* Include the files that instantiate the configuration definitions. */
246
247 #include "cpuRegisters.h"
248 #include "cpuFamRegisters.h"
249 #include "cpuFamilyTranslation.h"
250 #include "AdvancedApi.h"
251 #include "heapManager.h"
252 #include "CreateStruct.h"
253 #include "cpuFeatures.h"
254 #include "Table.h"
255 #include "cpuEarlyInit.h"
256 #include "cpuLateInit.h"
257 #include "GnbInterface.h"
258
259 /*****************************************************************************
260 * Define the RELEASE VERSION string
261 *
262 * The Release Version string should identify the next planned release.
263 * When a branch is made in preparation for a release, the release manager
264 * should change/confirm that the branch version of this file contains the
265 * string matching the desired version for the release. The trunk version of
266 * the file should always contain a trailing 'X'. This will make sure that a
267 * development build from trunk will not be confused for a released version.
268 * The release manager will need to remove the trailing 'X' and update the
269 * version string as appropriate for the release. The trunk copy of this file
270 * should also be updated/incremented for the next expected version, + trailing 'X'
271 ****************************************************************************/
272 // This is the delivery package title, "BrazosPI"
273 // This string MUST be exactly 8 characters long
274 #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
275
276 // This is the release version number of the AGESA component
277 // This string MUST be exactly 12 characters long
278 #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
279
280 /* MEMORY_BUS_SPEED */
281 #define DDR400_FREQUENCY 200 ///< DDR 400
282 #define DDR533_FREQUENCY 266 ///< DDR 533
283 #define DDR667_FREQUENCY 333 ///< DDR 667
284 #define DDR800_FREQUENCY 400 ///< DDR 800
285 #define DDR1066_FREQUENCY 533 ///< DDR 1066
286 #define DDR1333_FREQUENCY 667 ///< DDR 1333
287 #define DDR1600_FREQUENCY 800 ///< DDR 1600
288 #define DDR1866_FREQUENCY 933 ///< DDR 1866
289 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
290
291 /* QUANDRANK_TYPE*/
292 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
293 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
294
295 /* USER_MEMORY_TIMING_MODE */
296 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
297 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
298 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
299
300 /* POWER_DOWN_MODE */
301 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
302 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
303
304 // The following definitions specify the default values for various parameters in which there are
305 // no clearly defined defaults to be used in the common file. The values below are based on product
306 // and BKDG content, please consult the AGESA Memory team for consultation.
307 #define DFLT_SCRUB_DRAM_RATE (0)
308 #define DFLT_SCRUB_L2_RATE (0)
309 #define DFLT_SCRUB_L3_RATE (0)
310 #define DFLT_SCRUB_IC_RATE (0)
311 #define DFLT_SCRUB_DC_RATE (0)
312 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
313 #define DFLT_VRM_SLEW_RATE (5000)
314
315 // Instantiate all solution relevant data.
316 #include "PlatformInstall.h"
317
318 /*----------------------------------------------------------------------------------------
319 * CUSTOMER OVERIDES MEMORY TABLE
320 *----------------------------------------------------------------------------------------
321 */
322
323 /*
324 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
325 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
326 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
327 * use its default conservative settings.
328 */
329 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
330 //
331 // The following macros are supported (use comma to separate macros):
332 //
333 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
334 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
335 // AGESA will base on this value to disable unused MemClk to save power.
336 // Example:
337 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
338 // Bit AM3/S1g3 pin name
339 // 0 M[B,A]_CLK_H/L[0]
340 // 1 M[B,A]_CLK_H/L[1]
341 // 2 M[B,A]_CLK_H/L[2]
342 // 3 M[B,A]_CLK_H/L[3]
343 // 4 M[B,A]_CLK_H/L[4]
344 // 5 M[B,A]_CLK_H/L[5]
345 // 6 M[B,A]_CLK_H/L[6]
346 // 7 M[B,A]_CLK_H/L[7]
347 // And platform has the following routing:
348 // CS0 M[B,A]_CLK_H/L[4]
349 // CS1 M[B,A]_CLK_H/L[2]
350 // CS2 M[B,A]_CLK_H/L[3]
351 // CS3 M[B,A]_CLK_H/L[5]
352 // Then platform can specify the following macro:
353 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
354 //
355 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
356 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
357 // AGESA will base on this value to tristate unused CKE to save power.
358 //
359 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
360 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
361 // AGESA will base on this value to tristate unused ODT pins to save power.
362 //
363 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
364 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
365 // AGESA will base on this value to tristate unused Chip select to save power.
366 //
367 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
368 // Specifies the number of DIMM slots per channel.
369 //
370 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
371 // Specifies the number of Chip selects per channel.
372 //
373 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
374 // Specifies the number of channels per socket.
375 //
376 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
377 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
378 //
379 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
380 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
381 //
382 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
383 // Byte6Seed, Byte7Seed, ByteEccSeed)
384 // Specifies the write leveling seed for a channel of a socket.
385 //
386 HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
387 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
388 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
389 PSO_END
390 };
391
392 /*
393 * These tables are optional and may be used to adjust memory timing settings
394 */
395 #include "mm.h"
396 #include "mn.h"
397
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