src/mainboard/amd/torpedo/buildOpts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 /**
  21  * @file
  22  *
  23  * AMD User options selection for a Sabine/Lynx platform solution system
  24  *
  25  * This file is placed in the user's platform directory and contains the
  26  * build option selections desired for that platform.
  27  *
  28  * For Information about this file, see @ref platforminstall.
  29  *
  30  */
  31
  32 #include <stdlib.h>
  33 #include "AGESA.h"
  34 #include "CommonReturns.h"
  35 #include "Filecode.h"
  36 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
  37
  38
  39 /*  Select the cpu family.  */
  40 #define INSTALL_FAMILY_10_SUPPORT FALSE
  41 #define INSTALL_FAMILY_12_SUPPORT TRUE
  42 #define INSTALL_FAMILY_14_SUPPORT FALSE
  43 #define INSTALL_FAMILY_15_SUPPORT FALSE
  44
  45 /*  Select the cpu socket type.  */
  46 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
  47 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
  48 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
  49 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
  50 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
  51 #define INSTALL_FS1_SOCKET_SUPPORT  TRUE
  52 #define INSTALL_FM1_SOCKET_SUPPORT  FALSE
  53 #define INSTALL_FP1_SOCKET_SUPPORT  TRUE
  54 #define INSTALL_FT1_SOCKET_SUPPORT  FALSE
  55 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
  56
  57 /*
  58  * Agesa optional capabilities selection.
  59  * Uncomment and mark FALSE those features you wish to include in the build.
  60  * Comment out or mark TRUE those features you want to REMOVE from the build.
  61  */
  62
  63 #define BLDOPT_REMOVE_UDIMMS_SUPPORT           FALSE
  64 #define BLDOPT_REMOVE_RDIMMS_SUPPORT           FALSE
  65 #define BLDOPT_REMOVE_ECC_SUPPORT              FALSE
  66 #define BLDOPT_REMOVE_BANK_INTERLEAVE          FALSE
  67 #define BLDOPT_REMOVE_DCT_INTERLEAVE           FALSE
  68 #define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
  69 #define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
  70 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
  71 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      FALSE
  72 #define BLDOPT_REMOVE_DDR2_SUPPORT             TRUE
  73 #define BLDOPT_REMOVE_DDR3_SUPPORT             FALSE
  74 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
  75 #define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
  76 #define BLDOPT_REMOVE_SRAT                     TRUE
  77 #define BLDOPT_REMOVE_SLIT                     TRUE
  78 #define BLDOPT_REMOVE_WHEA                     TRUE
  79 #define BLDOPT_REMOVE_DMI                      FALSE
  80 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
  81 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC         FALSE
  82 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT         FALSE
  83 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD         FALSE
  84 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS         FALSE
  85 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS        FALSE
  86
  87 //For revision C single-link processors
  88 #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX  TRUE
  89
  90 /*
  91  * Agesa entry points used in this implementation.
  92  */
  93 #define AGESA_ENTRY_INIT_RESET                    TRUE
  94 #define AGESA_ENTRY_INIT_RECOVERY                 FALSE
  95 #define AGESA_ENTRY_INIT_EARLY                    TRUE
  96 #define AGESA_ENTRY_INIT_POST                     TRUE
  97 #define AGESA_ENTRY_INIT_ENV                      TRUE
  98 #define AGESA_ENTRY_INIT_MID                      TRUE
  99 #define AGESA_ENTRY_INIT_LATE                     TRUE
 100 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 101 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 102 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
 103 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 104
 105 /*****************************************************************************
 106  *   Define the RELEASE VERSION string
 107  *
 108  * The Release Version string should identify the next planned release.
 109  * When a branch is made in preparation for a release, the release manager
 110  * should change/confirm that the branch version of this file contains the
 111  * string matching the desired version for the release. The trunk version of
 112  * the file should always contain a trailing 'X'. This will make sure that a
 113  * development build from trunk will not be confused for a released version.
 114  * The release manager will need to remove the trailing 'X' and update the
 115  * version string as appropriate for the release. The trunk copy of this file
 116  * should also be updated/incremented for the next expected version, + trailing 'X'
 117  ****************************************************************************/
 118                   // This is the delivery package title, "LlanoPI "
 119                   // This string MUST be exactly 8 characters long
 120 #define AGESA_PACKAGE_STRING  {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
 121
 122                   // This is the release version number of the AGESA component
 123                   // This string MUST be exactly 12 characters long
 124 #define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
 125
 126 // The following definitions specify the default values for various parameters in which there are
 127 // no clearly defined defaults to be used in the common file.  The values below are based on product
 128 // and BKDG content, please consult the AGESA Memory team for consultation.
 129 #define DFLT_SCRUB_DRAM_RATE            (0)
 130 #define DFLT_SCRUB_L2_RATE              (0)
 131 #define DFLT_SCRUB_L3_RATE              (0)
 132 #define DFLT_SCRUB_IC_RATE              (0)
 133 #define DFLT_SCRUB_DC_RATE              (0)
 134 #define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
 135 #define DFLT_VRM_SLEW_RATE              (5000)
 136
 137 /* Build configuration values here.
 138  */
 139 #define BLDCFG_VRM_CURRENT_LIMIT                 65000  //240000 //120000
 140 #define BLDCFG_VRM_LOW_POWER_THRESHOLD           15000  // 0
 141 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
 142 #define BLDCFG_PLAT_NUM_IO_APICS                 3
 143 #define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
 144 #define BLDCFG_MEM_INIT_PSTATE                   0
 145
 146 #define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
 147
 148 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY //DDR1066_FREQUENCY
 149 #define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
 150 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
 151 #define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
 152 #define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
 153 #define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
 154 #define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
 155 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
 156 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
 157 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
 158 #define BLDCFG_MEMORY_POWER_DOWN                  TRUE
 159 #define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
 160 #define BLDCFG_ONLINE_SPARE                       FALSE
 161 #define BLDCFG_MEMORY_PARITY_ENABLE               FALSE
 162 #define BLDCFG_BANK_SWIZZLE                       TRUE
 163 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
 164 #define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
 165 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 166 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 167 #define BLDCFG_USE_BURST_MODE                     FALSE
 168 #define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
 169 #define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
 170 #define BLDCFG_ECC_REDIRECTION                    FALSE
 171 #define BLDCFG_SCRUB_DRAM_RATE                    0
 172 #define BLDCFG_SCRUB_L2_RATE                      0
 173 #define BLDCFG_SCRUB_L3_RATE                      0
 174 #define BLDCFG_SCRUB_IC_RATE                      0
 175 #define BLDCFG_SCRUB_DC_RATE                      0
 176 #define BLDCFG_ECC_SYNC_FLOOD                     FALSE
 177 #define BLDCFG_ECC_SYMBOL_SIZE                    4
 178 #define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
 179 #define BLDCFG_1GB_ALIGN                          FALSE
 180 #define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
 181 //#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
 182 //#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
 183
 184 //enable HW C1E
 185 #define BLDCFG_PLATFORM_C1E_MODE     0 //C1eModeHardware
 186 //#define BLDCFG_PLATFORM_C1E_OPDATA              0x415
 187 #define BLDCFG_PLATFORM_CSTATE_MODE     CStateModeC6 //0 //CStateModeC6
 188 //#define BLDCFG_PLATFORM_CSTATE_OPDATA   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
 189 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
 190
 191
 192 //#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Llano/Ontario
 193 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L.  Default is Zero.
 194 //#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime per BKDG.  Defaults to 5000, same as core VRM.  Cannot be zero.
 195 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Llano/Ontario
 196 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Llano/Ontario
 197 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Llano/Ontario
 198
 199 #define BLDCFG_UMA_ABOVE4G_SUPPORT              TRUE
 200 #define BLDCFG_STEREO_3D_PINOUT                 TRUE
 201
 202 /*  Process the options...
 203  * This file include MUST occur AFTER the user option selection settings
 204  */
 205 CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
 206 {
 207   { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
 208   { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
 209   { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
 210   { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
 211   { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
 212   { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
 213   { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
 214   { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
 215   { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
 216   { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
 217   { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
 218   { CPU_LIST_TERMINAL }
 219 };
 220
 221 #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
 222 //#define OPTION_NB_LCLK_DPM_INIT FALSE
 223 //#define OPTION_POWER_GATE       FALSE
 224 //#define OPTION_PCIE_POWER_GATE  FALSE
 225 //#define OPTION_ALIB             FALSE
 226 //#define OPTION_PCIe_MID_INIT  FALSE
 227 //#define OPTION_NB_MID_INIT    FALSE
 228
 229 #include "cpuRegisters.h"
 230 #include "cpuFamRegisters.h"
 231 #include "cpuFamilyTranslation.h"
 232 #include "AdvancedApi.h"
 233 #include "heapManager.h"
 234 #include "CreateStruct.h"
 235 #include "cpuFeatures.h"
 236 #include "Table.h"
 237 #include "CommonReturns.h"
 238 #include "cpuEarlyInit.h"
 239 #include "cpuLateInit.h"
 240 #include "GnbInterface.h"
 241 #include "PlatformInstall.h"
 242
 243 /*----------------------------------------------------------------------------------------
 244  *                        CUSTOMER OVERIDES MEMORY TABLE
 245  *----------------------------------------------------------------------------------------
 246  */
 247
 248 /*
 249  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 250  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 251  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 252  *  use its default conservative settings.
 253  */
 254 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 255   //
 256   // The following macros are supported (use comma to separate macros):
 257   //
 258   // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
 259   //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
 260   //      AGESA will base on this value to disable unused MemClk to save power.
 261   //      Example:
 262   //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
 263   //           Bit AM3/S1g3 pin name
 264   //           0   M[B,A]_CLK_H/L[0]
 265   //           1   M[B,A]_CLK_H/L[1]
 266   //           2   M[B,A]_CLK_H/L[2]
 267   //           3   M[B,A]_CLK_H/L[3]
 268   //           4   M[B,A]_CLK_H/L[4]
 269   //           5   M[B,A]_CLK_H/L[5]
 270   //           6   M[B,A]_CLK_H/L[6]
 271   //           7   M[B,A]_CLK_H/L[7]
 272   //      And platform has the following routing:
 273   //           CS0   M[B,A]_CLK_H/L[4]
 274   //           CS1   M[B,A]_CLK_H/L[2]
 275   //           CS2   M[B,A]_CLK_H/L[3]
 276   //           CS3   M[B,A]_CLK_H/L[5]
 277   //      Then platform can specify the following macro:
 278   //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
 279   //
 280   // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
 281   //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
 282   //      AGESA will base on this value to tristate unused CKE to save power.
 283   //
 284   // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
 285   //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
 286   //      AGESA will base on this value to tristate unused ODT pins to save power.
 287   //
 288   // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
 289   //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
 290   //      AGESA will base on this value to tristate unused Chip select to save power.
 291   //
 292   // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
 293   //      Specifies the number of DIMM slots per channel.
 294   //
 295   // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
 296   //      Specifies the number of Chip selects per channel.
 297   //
 298   // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
 299   //      Specifies the number of channels per socket.
 300   //
 301   // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
 302   //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
 303   //
 304   // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
 305   //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
 306   //
 307   // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
 308   //      Byte6Seed, Byte7Seed, ByteEccSeed)
 309   //      Specifies the write leveling seed for a channel of a socket.
 310   //
 311   NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
 312   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 313   PSO_END
 314 };
 315
 316 /*
 317  * These tables are optional and may be used to adjust memory timing settings
 318  */
 319 #include "mm.h"
 320 #include "mn.h"
 321