src/include/elog.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef ELOG_H_
   4 #define ELOG_H_
   5
   6 #include <stdint.h>
   7
   8 #define MAX_EVENT_SIZE                    0x7F
   9
  10 /* End of log */
  11 #define ELOG_TYPE_EOL                     0xFF
  12
  13 /*
  14  * Standard SMBIOS event log types below 0x80
  15  */
  16 #define ELOG_TYPE_UNDEFINED_EVENT         0x00
  17 #define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR  0x01
  18 #define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR   0x02
  19 #define ELOG_TYPE_MEM_PARITY_ERR          0x03
  20 #define ELOG_TYPE_BUS_TIMEOUT             0x04
  21 #define ELOG_TYPE_IO_CHECK                0x05
  22 #define ELOG_TYPE_SW_NMI                  0x06
  23 #define ELOG_TYPE_POST_MEM_RESIZE         0x07
  24 #define ELOG_TYPE_POST_ERR                0x08
  25 #define ELOG_TYPE_PCI_PERR                0x09
  26 #define ELOG_TYPE_PCI_SERR                0x0A
  27 #define ELOG_TYPE_CPU_FAIL                0x0B
  28 #define ELOG_TYPE_EISA_TIMEOUT            0x0C
  29 #define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS  0x0D
  30 #define ELOG_TYPE_LOG_DISABLED            0x0E
  31 #define ELOG_TYPE_UNDEFINED_EVENT2        0x0F
  32 #define ELOG_TYPE_SYS_LIMIT_EXCEED        0x10
  33 #define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED  0x11
  34 #define ELOG_TYPE_SYS_CONFIG_INFO         0x12
  35 #define ELOG_TYPE_HDD_INFO                0x13
  36 #define ELOG_TYPE_SYS_RECONFIG            0x14
  37 #define ELOG_TYPE_CPU_ERROR               0x15
  38 #define ELOG_TYPE_LOG_CLEAR               0x16
  39 #define ELOG_TYPE_BOOT                    0x17
  40
  41 /*
  42  * Extended defined OEM event types start at 0x80
  43  */
  44
  45 /* OS/kernel events */
  46 #define ELOG_TYPE_OS_EVENT                0x81
  47
  48 /* Last event from coreboot */
  49 #define ELOG_TYPE_OS_BOOT                 0x90
  50
  51 /* Embedded controller event */
  52 #define ELOG_TYPE_EC_EVENT                0x91
  53
  54 /* Power */
  55 #define ELOG_TYPE_POWER_FAIL              0x92
  56 #define ELOG_TYPE_SUS_POWER_FAIL          0x93
  57 #define ELOG_TYPE_PWROK_FAIL              0x94
  58 #define ELOG_TYPE_SYS_PWROK_FAIL          0x95
  59 #define ELOG_TYPE_POWER_ON                0x96
  60 #define ELOG_TYPE_POWER_BUTTON            0x97
  61 #define ELOG_TYPE_POWER_BUTTON_OVERRIDE   0x98
  62
  63 /* Reset */
  64 #define ELOG_TYPE_RESET_BUTTON            0x99
  65 #define ELOG_TYPE_SYSTEM_RESET            0x9a
  66 #define ELOG_TYPE_RTC_RESET               0x9b
  67 #define ELOG_TYPE_TCO_RESET               0x9c
  68
  69 /* Sleep/Wake */
  70 #define ELOG_TYPE_ACPI_ENTER              0x9d
  71 /*
  72  * Deep Sx wake variant is provided below - 0xad
  73  * Sleep/"wake pending" event log provided below - 0xb1 - 0x01/0x02
  74  */
  75
  76 #define ELOG_TYPE_ACPI_WAKE               0x9e
  77 #define ELOG_TYPE_WAKE_SOURCE             0x9f
  78 #define  ELOG_WAKE_SOURCE_PCIE             0x00
  79 #define  ELOG_WAKE_SOURCE_PME              0x01
  80 #define  ELOG_WAKE_SOURCE_PME_INTERNAL     0x02
  81 #define  ELOG_WAKE_SOURCE_RTC              0x03
  82 #define  ELOG_WAKE_SOURCE_GPE              0x04
  83 #define  ELOG_WAKE_SOURCE_SMBUS            0x05
  84 #define  ELOG_WAKE_SOURCE_PWRBTN           0x06
  85 #define  ELOG_WAKE_SOURCE_PME_HDA          0x07
  86 #define  ELOG_WAKE_SOURCE_PME_GBE          0x08
  87 #define  ELOG_WAKE_SOURCE_PME_EMMC         0x09
  88 #define  ELOG_WAKE_SOURCE_PME_SDCARD       0x0a
  89 #define  ELOG_WAKE_SOURCE_PME_PCIE1        0x0b
  90 #define  ELOG_WAKE_SOURCE_PME_PCIE2        0x0c
  91 #define  ELOG_WAKE_SOURCE_PME_PCIE3        0x0d
  92 #define  ELOG_WAKE_SOURCE_PME_PCIE4        0x0e
  93 #define  ELOG_WAKE_SOURCE_PME_PCIE5        0x0f
  94 #define  ELOG_WAKE_SOURCE_PME_PCIE6        0x10
  95 #define  ELOG_WAKE_SOURCE_PME_PCIE7        0x11
  96 #define  ELOG_WAKE_SOURCE_PME_PCIE8        0x12
  97 #define  ELOG_WAKE_SOURCE_PME_PCIE9        0x13
  98 #define  ELOG_WAKE_SOURCE_PME_PCIE10       0x14
  99 #define  ELOG_WAKE_SOURCE_PME_PCIE11       0x15
 100 #define  ELOG_WAKE_SOURCE_PME_PCIE12       0x16
 101 #define  ELOG_WAKE_SOURCE_PME_SATA         0x17
 102 #define  ELOG_WAKE_SOURCE_PME_CSE          0x18
 103 #define  ELOG_WAKE_SOURCE_PME_CSE2         0x19
 104 #define  ELOG_WAKE_SOURCE_PME_CSE3         0x1a
 105 #define  ELOG_WAKE_SOURCE_PME_XHCI         0x1b
 106 #define  ELOG_WAKE_SOURCE_PME_XDCI         0x1c
 107 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_2   0x1d
 108 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_3   0x1e
 109 #define  ELOG_WAKE_SOURCE_PME_WIFI         0x1f
 110 #define  ELOG_WAKE_SOURCE_PME_PCIE13       0x20
 111 #define  ELOG_WAKE_SOURCE_PME_PCIE14       0x21
 112 #define  ELOG_WAKE_SOURCE_PME_PCIE15       0x22
 113 #define  ELOG_WAKE_SOURCE_PME_PCIE16       0x23
 114 #define  ELOG_WAKE_SOURCE_PME_PCIE17       0x24
 115 #define  ELOG_WAKE_SOURCE_PME_PCIE18       0x25
 116 #define  ELOG_WAKE_SOURCE_PME_PCIE19       0x26
 117 #define  ELOG_WAKE_SOURCE_PME_PCIE20       0x27
 118 #define  ELOG_WAKE_SOURCE_PME_PCIE21       0x28
 119 #define  ELOG_WAKE_SOURCE_PME_PCIE22       0x29
 120 #define  ELOG_WAKE_SOURCE_PME_PCIE23       0x2a
 121 #define  ELOG_WAKE_SOURCE_PME_PCIE24       0x2b
 122 #define  ELOG_WAKE_SOURCE_GPIO             0x2c
 123 #define  ELOG_WAKE_SOURCE_PME_TBT          0x2d
 124 #define  ELOG_WAKE_SOURCE_PME_TCSS_XHCI    0x2e
 125 #define  ELOG_WAKE_SOURCE_PME_TCSS_XDCI    0x2f
 126 #define  ELOG_WAKE_SOURCE_PME_TCSS_DMA     0x30
 127
 128 struct elog_event_data_wake {
 129         u8 source;
 130         u32 instance;
 131 } __packed;
 132
 133 /* Chrome OS related events */
 134 #define ELOG_TYPE_CROS_DEVELOPER_MODE     0xa0
 135 #define ELOG_TYPE_CROS_RECOVERY_MODE      0xa1
 136 #define  ELOG_CROS_RECOVERY_MODE_BUTTON    0x02
 137
 138 /* Management Engine Events */
 139 #define ELOG_TYPE_MANAGEMENT_ENGINE       0xa2
 140 #define ELOG_TYPE_MANAGEMENT_ENGINE_EXT   0xa4
 141 struct elog_event_data_me_extended {
 142         u8 current_working_state;
 143         u8 operation_state;
 144         u8 operation_mode;
 145         u8 error_code;
 146         u8 progress_code;
 147         u8 current_pmevent;
 148         u8 current_state;
 149 } __packed;
 150
 151 /* Last post code from previous boot */
 152 #define ELOG_TYPE_LAST_POST_CODE          0xa3
 153 #define ELOG_TYPE_POST_EXTRA              0xa6
 154
 155 /* EC Shutdown Reason */
 156 #define ELOG_TYPE_EC_SHUTDOWN             0xa5
 157
 158 /* ARM/generic versions of sleep/wake - These came from another firmware
 159  * apparently, but not all the firmware sources were updated so that the
 160  * elog namespace was coherent. */
 161 #define ELOG_TYPE_SLEEP                   0xa7
 162 #define ELOG_TYPE_WAKE                    0xa8
 163 #define ELOG_TYPE_FW_WAKE                 0xa9
 164
 165 /* Memory Cache Update */
 166 #define ELOG_TYPE_MEM_CACHE_UPDATE        0xaa
 167 #define  ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL    0
 168 #define  ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY  1
 169 #define  ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE  2
 170 #define  ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
 171 #define  ELOG_MEM_CACHE_UPDATE_STATUS_FAIL    1
 172 struct elog_event_mem_cache_update {
 173         u8 slot;
 174         u8 status;
 175 } __packed;
 176
 177 /* CPU Thermal Trip */
 178 #define ELOG_TYPE_THERM_TRIP              0xab
 179
 180 /* Cr50 */
 181 #define ELOG_TYPE_CR50_UPDATE             0xac
 182
 183 /* Deep Sx wake variant */
 184 #define ELOG_TYPE_ACPI_DEEP_WAKE          0xad
 185
 186 /* EC Device Event */
 187 #define ELOG_TYPE_EC_DEVICE_EVENT         0xae
 188 #define ELOG_EC_DEVICE_EVENT_TRACKPAD       0x01
 189 #define ELOG_EC_DEVICE_EVENT_DSP            0x02
 190 #define ELOG_EC_DEVICE_EVENT_WIFI           0x03
 191
 192 /* S0ix sleep/wake */
 193 #define ELOG_TYPE_S0IX_ENTER              0xaf
 194 #define ELOG_TYPE_S0IX_EXIT               0xb0
 195
 196 /* Extended events */
 197 #define ELOG_TYPE_EXTENDED_EVENT          0xb1
 198 #define  ELOG_SLEEP_PENDING_PM1_WAKE       0x01
 199 #define  ELOG_SLEEP_PENDING_GPE0_WAKE      0x02
 200
 201 /* Cr50 reset to enable TPM */
 202 #define ELOG_TYPE_CR50_NEED_RESET         0xb2
 203
 204 /* CSME-Initiated Host Reset */
 205 #define ELOG_TYPE_MI_HRPD                 0xb3
 206 #define ELOG_TYPE_MI_HRPC                 0xb4
 207 #define ELOG_TYPE_MI_HR                   0xb5
 208
 209 struct elog_event_extended_event {
 210         u8 event_type;
 211         u32 event_complement;
 212 } __packed;
 213
 214 #if CONFIG(ELOG)
 215 /* Eventlog backing storage must be initialized before calling elog_init(). */
 216 extern int elog_init(void);
 217 extern int elog_clear(void);
 218 /* Event addition functions return < 0 on failure and 0 on success. */
 219 extern int elog_add_event_raw(u8 event_type, void *data, u8 data_size);
 220 extern int elog_add_event(u8 event_type);
 221 extern int elog_add_event_byte(u8 event_type, u8 data);
 222 extern int elog_add_event_word(u8 event_type, u16 data);
 223 extern int elog_add_event_dword(u8 event_type, u32 data);
 224 extern int elog_add_event_wake(u8 source, u32 instance);
 225 extern int elog_smbios_write_type15(unsigned long *current, int handle);
 226 extern int elog_add_extended_event(u8 type, u32 complement);
 227 #else
 228 /* Stubs to help avoid littering sources with #if CONFIG_ELOG */
 229 static inline int elog_init(void) { return -1; }
 230 static inline int elog_clear(void) { return -1; }
 231 static inline int elog_add_event_raw(u8 event_type, void *data,
 232                                         u8 data_size) { return 0; }
 233 static inline int elog_add_event(u8 event_type) { return 0; }
 234 static inline int elog_add_event_byte(u8 event_type, u8 data) { return 0; }
 235 static inline int elog_add_event_word(u8 event_type, u16 data) { return 0; }
 236 static inline int elog_add_event_dword(u8 event_type, u32 data) { return 0; }
 237 static inline int elog_add_event_wake(u8 source, u32 instance) { return 0; }
 238 static inline int elog_smbios_write_type15(unsigned long *current,
 239                                                 int handle) {
 240         return 0;
 241 }
 242 static inline int elog_add_extended_event(u8 type, u32 complement) { return 0; }
 243 #endif
 244
 245 #if CONFIG(ELOG_GSMI)
 246 #define elog_gsmi_add_event elog_add_event
 247 #define elog_gsmi_add_event_byte elog_add_event_byte
 248 #define elog_gsmi_add_event_word elog_add_event_word
 249 #else
 250 static inline int elog_gsmi_add_event(u8 event_type) { return 0; }
 251 static inline int elog_gsmi_add_event_byte(u8 event_type, u8 data) { return 0; }
 252 static inline int elog_gsmi_add_event_word(u8 event_type, u16 data) { return 0; }
 253 #endif
 254
 255 extern u32 gsmi_exec(u8 command, u32 *param);
 256
 257 #if CONFIG(ELOG_BOOT_COUNT)
 258 u32 boot_count_read(void);
 259 #else
 260 static inline u32 boot_count_read(void)
 261 {
 262         return 0;
 263 }
 264 #endif
 265 u32 boot_count_increment(void);
 266
 267 static inline void elog_boot_notify(int s3_resume)
 268 {
 269         if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume)
 270                 boot_count_increment();
 271 }
 272
 273 /*
 274  * Callback from GSMI handler to allow platform to log any wake source
 275  * information.
 276  */
 277 void elog_gsmi_cb_platform_log_wake_source(void);
 278
 279 /*
 280  * Callback from GSMI handler to allow mainboard to log any wake source
 281  * information.
 282  */
 283 void elog_gsmi_cb_mainboard_log_wake_source(void);
 284
 285 #endif /* ELOG_H_ */