src/drivers/intel/fsp1_1/romstage.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stddef.h>
   4 #include <acpi/acpi.h>
   5 #include <assert.h>
   6 #include <console/console.h>
   7 #include <cbmem.h>
   8 #include <cf9_reset.h>
   9 #include <cpu/intel/microcode.h>
  10 #include <ec/google/chromeec/ec.h>
  11 #include <ec/google/chromeec/ec_commands.h>
  12 #include <elog.h>
  13 #include <fsp/romstage.h>
  14 #include <mrc_cache.h>
  15 #include <program_loading.h>
  16 #include <romstage_handoff.h>
  17 #include <smbios.h>
  18 #include <stage_cache.h>
  19 #include <string.h>
  20 #include <timestamp.h>
  21 #include <vendorcode/google/chromeos/chromeos.h>
  22
  23 static void raminit_common(struct romstage_params *params)
  24 {
  25         bool s3wake;
  26         size_t mrc_size;
  27
  28         post_code(0x32);
  29
  30         timestamp_add_now(TS_BEFORE_INITRAM);
  31
  32         s3wake = params->power_state->prev_sleep_state == ACPI_S3;
  33
  34         elog_boot_notify(s3wake);
  35
  36         post_code(0x33);
  37
  38         /* Check recovery and MRC cache */
  39         params->saved_data_size = 0;
  40         params->saved_data = NULL;
  41         if (!params->disable_saved_data) {
  42                 /* Assume boot device is memory mapped. */
  43                 assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
  44
  45                 params->saved_data = NULL;
  46                 if (CONFIG(CACHE_MRC_SETTINGS))
  47                         params->saved_data =
  48                                 mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
  49                                                             params->fsp_version,
  50                                                             &mrc_size);
  51                 if (params->saved_data) {
  52                         /* MRC cache found */
  53                         params->saved_data_size = mrc_size;
  54
  55                 } else if (s3wake) {
  56                         /* Waking from S3 and no cache. */
  57                         printk(BIOS_DEBUG,
  58                                "No MRC cache "
  59                                "found in S3 resume path.\n");
  60                         post_code(POST_RESUME_FAILURE);
  61                         /* FIXME: A "system" reset is likely enough: */
  62                         full_reset();
  63                 } else {
  64                         printk(BIOS_DEBUG, "No MRC cache found.\n");
  65                 }
  66         }
  67
  68         /* Initialize RAM */
  69         raminit(params);
  70         timestamp_add_now(TS_AFTER_INITRAM);
  71
  72         /* Save MRC output */
  73         if (CONFIG(CACHE_MRC_SETTINGS)) {
  74                 printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n",
  75                         params->data_to_save, params->data_to_save_size);
  76                 if (!s3wake
  77                         && (params->data_to_save_size != 0)
  78                         && (params->data_to_save != NULL))
  79                         mrc_cache_stash_data(MRC_TRAINING_DATA,
  80                                 params->fsp_version,
  81                                 params->data_to_save,
  82                                 params->data_to_save_size);
  83         }
  84
  85         /* Save DIMM information */
  86         if (!s3wake)
  87                 mainboard_save_dimm_info(params);
  88
  89         /* Create romstage handof information */
  90         if (romstage_handoff_init(
  91                         params->power_state->prev_sleep_state == ACPI_S3) < 0)
  92                 /* FIXME: A "system" reset is likely enough: */
  93                 full_reset();
  94 }
  95
  96 void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
  97 {
  98         struct romstage_params params = {
  99                 .chipset_context = fih,
 100         };
 101
 102         post_code(0x30);
 103
 104         timestamp_add_now(TS_START_ROMSTAGE);
 105
 106         /* Load microcode before RAM init */
 107         if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
 108                 intel_update_microcode_from_cbfs();
 109
 110         /* Display parameters */
 111         if (!CONFIG(NO_MMCONF_SUPPORT))
 112                 printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
 113                         CONFIG_MMCONF_BASE_ADDRESS);
 114         printk(BIOS_INFO, "Using FSP 1.1\n");
 115
 116         /* Display FSP banner */
 117         print_fsp_info(fih);
 118
 119         /* Stash FSP version. */
 120         params.fsp_version = fsp_version(fih);
 121
 122         /* Get power state */
 123         params.power_state = fill_power_state();
 124
 125         /* Board initialization before and after RAM is enabled */
 126         mainboard_pre_raminit(&params);
 127
 128         post_code(0x31);
 129
 130         /* Initialize memory */
 131         raminit_common(&params);
 132
 133         soc_after_ram_init(&params);
 134         post_code(0x38);
 135 }
 136
 137 /* Board initialization before and after RAM is enabled */
 138 __weak void mainboard_pre_raminit(struct romstage_params *params)
 139 {
 140 }
 141
 142 /* Save the DIMM information for SMBIOS table 17 */
 143 __weak void mainboard_save_dimm_info(
 144         struct romstage_params *params)
 145 {
 146         int channel;
 147         CHANNEL_INFO *channel_info;
 148         int dimm;
 149         DIMM_INFO *dimm_info;
 150         int dimm_max;
 151         void *hob_list_ptr;
 152         EFI_HOB_GUID_TYPE *hob_ptr;
 153         int index;
 154         struct memory_info *mem_info;
 155         FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
 156         const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
 157
 158         /* Locate the memory info HOB, presence validated by raminit */
 159         hob_list_ptr = fsp_get_hob_list();
 160         hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr);
 161         memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
 162
 163         /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
 164         if (CONFIG(DISPLAY_HOBS)) {
 165                 printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
 166                 printk(BIOS_DEBUG, "    0x%02x: Revision\n",
 167                         memory_info_hob->Revision);
 168                 printk(BIOS_DEBUG, "    0x%02x: MemoryType\n",
 169                         memory_info_hob->MemoryType);
 170                 printk(BIOS_DEBUG, "    %d: MemoryFrequencyInMHz\n",
 171                         memory_info_hob->MemoryFrequencyInMHz);
 172                 printk(BIOS_DEBUG, "    %d: DataWidth in bits\n",
 173                         memory_info_hob->DataWidth);
 174                 printk(BIOS_DEBUG, "    0x%02x: ErrorCorrectionType\n",
 175                         memory_info_hob->ErrorCorrectionType);
 176                 printk(BIOS_DEBUG, "    0x%02x: ChannelCount\n",
 177                         memory_info_hob->ChannelCount);
 178                 for (channel = 0; channel < memory_info_hob->ChannelCount;
 179                         channel++) {
 180                         channel_info = &memory_info_hob->ChannelInfo[channel];
 181                         printk(BIOS_DEBUG, "  Channel %d\n", channel);
 182                         printk(BIOS_DEBUG, "      0x%02x: ChannelId\n",
 183                                 channel_info->ChannelId);
 184                         printk(BIOS_DEBUG, "      0x%02x: DimmCount\n",
 185                                 channel_info->DimmCount);
 186                         for (dimm = 0; dimm < channel_info->DimmCount;
 187                                 dimm++) {
 188                                 dimm_info = &channel_info->DimmInfo[dimm];
 189                                 printk(BIOS_DEBUG, "   DIMM %d\n", dimm);
 190                                 printk(BIOS_DEBUG, "      0x%02x: DimmId\n",
 191                                         dimm_info->DimmId);
 192                                 printk(BIOS_DEBUG, "      %d: SizeInMb\n",
 193                                         dimm_info->SizeInMb);
 194                         }
 195                 }
 196         }
 197
 198         /*
 199          * Allocate CBMEM area for DIMM information used to populate SMBIOS
 200          * table 17
 201          */
 202         mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
 203         printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info);
 204         if (mem_info == NULL)
 205                 return;
 206         memset(mem_info, 0, sizeof(*mem_info));
 207
 208         /* Describe the first N DIMMs in the system */
 209         index = 0;
 210         dimm_max = ARRAY_SIZE(mem_info->dimm);
 211         for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
 212                 if (index >= dimm_max)
 213                         break;
 214                 channel_info = &memory_info_hob->ChannelInfo[channel];
 215                 for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
 216                         if (index >= dimm_max)
 217                                 break;
 218                         dimm_info = &channel_info->DimmInfo[dimm];
 219
 220                         /* Populate the DIMM information */
 221                         if (dimm_info->SizeInMb) {
 222                                 mem_info->dimm[index].dimm_size =
 223                                         dimm_info->SizeInMb;
 224                                 mem_info->dimm[index].ddr_type =
 225                                         memory_info_hob->MemoryType;
 226                                 mem_info->dimm[index].ddr_frequency =
 227                                         memory_info_hob->MemoryFrequencyInMHz;
 228                                 mem_info->dimm[index].channel_num =
 229                                         channel_info->ChannelId;
 230                                 mem_info->dimm[index].dimm_num =
 231                                         dimm_info->DimmId;
 232                                 switch (memory_info_hob->DataWidth) {
 233                                 default:
 234                                 case 8:
 235                                         mem_info->dimm[index].bus_width =
 236                                                 MEMORY_BUS_WIDTH_8;
 237                                         break;
 238
 239                                 case 16:
 240                                         mem_info->dimm[index].bus_width =
 241                                                 MEMORY_BUS_WIDTH_16;
 242                                         break;
 243
 244                                 case 32:
 245                                         mem_info->dimm[index].bus_width =
 246                                                 MEMORY_BUS_WIDTH_32;
 247                                         break;
 248
 249                                 case 64:
 250                                         mem_info->dimm[index].bus_width =
 251                                                 MEMORY_BUS_WIDTH_64;
 252                                         break;
 253
 254                                 case 128:
 255                                         mem_info->dimm[index].bus_width =
 256                                                 MEMORY_BUS_WIDTH_128;
 257                                         break;
 258                                 }
 259                                 index++;
 260                         }
 261                 }
 262         }
 263         mem_info->dimm_cnt = index;
 264         printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 265 }