drivers/intel/fsp1_1: Drop empty weak functions
[coreboot.git] / src / drivers / intel / fsp1_1 / ramstage.c
blobdcb32c7907dfdc3b0e4f35a34fb55b8aa429a395
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootmode.h>
4 #include <bootsplash.h>
5 #include <acpi/acpi.h>
6 #include <console/console.h>
7 #include <fsp/ramstage.h>
8 #include <fsp/util.h>
9 #include <framebuffer_info.h>
10 #include <lib.h>
11 #include <stage_cache.h>
12 #include <string.h>
13 #include <timestamp.h>
14 #include <cbmem.h>
16 static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
18 const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
19 void *hob_list_ptr = get_hob_list();
21 /* Verify the HOBs */
22 if (hob_list_ptr == NULL) {
23 printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n");
24 return;
27 if (CONFIG(DISPLAY_HOBS))
28 print_hob_type_structure(0, hob_list_ptr);
31 * Verify that FSP is generating the required HOBs:
32 * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
33 * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
34 * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
35 * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
36 * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below,
37 * if the ImageAttribute bit is set
38 * FSP_SMBIOS_MEMORY_INFO HOB verified by raminit
40 if ((fsp_info_header->ImageAttribute & GRAPHICS_SUPPORT_BIT) &&
41 !get_next_guid_hob(&graphics_info_guid, hob_list_ptr) &&
42 CONFIG(DISPLAY_HOBS)) {
43 printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
44 printk(BIOS_ERR,
45 "ERROR - Missing one or more required FSP HOBs!\n");
49 static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
51 FSP_SILICON_INIT fsp_silicon_init;
52 SILICON_INIT_UPD *original_params;
53 SILICON_INIT_UPD silicon_init_params;
54 EFI_STATUS status;
55 UPD_DATA_REGION *upd_ptr;
56 VPD_DATA_REGION *vpd_ptr;
58 /* Display the FSP header */
59 if (fsp_info_header == NULL) {
60 printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
61 return;
63 print_fsp_info(fsp_info_header);
65 /* Initialize the UPD values */
66 vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
67 fsp_info_header->ImageBase);
68 printk(BIOS_DEBUG, "%p: VPD Data\n", vpd_ptr);
69 upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
70 fsp_info_header->ImageBase);
71 printk(BIOS_DEBUG, "%p: UPD Data\n", upd_ptr);
72 original_params = (void *)((u8 *)upd_ptr +
73 upd_ptr->SiliconInitUpdOffset);
74 memcpy(&silicon_init_params, original_params,
75 sizeof(silicon_init_params));
76 soc_silicon_init_params(&silicon_init_params);
78 /* Locate VBT and pass to FSP GOP */
79 if (CONFIG(RUN_FSP_GOP))
80 load_vbt(&silicon_init_params);
81 mainboard_silicon_init_params(&silicon_init_params);
83 if (CONFIG(BMP_LOGO))
84 bmp_load_logo(&silicon_init_params.PcdLogoPtr,
85 &silicon_init_params.PcdLogoSize);
87 /* Display the UPD data */
88 if (CONFIG(DISPLAY_UPD_DATA))
89 soc_display_silicon_init_params(original_params,
90 &silicon_init_params);
92 /* Perform silicon initialization after RAM is configured */
93 printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
94 fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
95 + fsp_info_header->FspSiliconInitEntryOffset);
96 timestamp_add_now(TS_FSP_SILICON_INIT_START);
97 printk(BIOS_DEBUG, "Calling FspSiliconInit(%p) at %p\n",
98 &silicon_init_params, fsp_silicon_init);
99 post_code(POST_FSP_SILICON_INIT);
100 status = fsp_silicon_init(&silicon_init_params);
101 timestamp_add_now(TS_FSP_SILICON_INIT_END);
102 printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
104 /* The logo_entry can be freed up now as it is not required any longer */
105 if (CONFIG(BMP_LOGO))
106 bmp_release_logo();
108 /* Mark graphics init done after SiliconInit if VBT was provided */
109 #if CONFIG(RUN_FSP_GOP)
110 /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
111 * to be #if'd out instead of using if (). */
112 if (silicon_init_params.GraphicsConfigPtr)
113 gfx_set_init_done(1);
114 #endif
116 if (CONFIG(RUN_FSP_GOP)) {
117 const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
118 u32 *vbt_hob;
120 void *hob_list_ptr = get_hob_list();
121 vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr);
122 if (vbt_hob == NULL) {
123 printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
124 } else {
125 EFI_PEI_GRAPHICS_INFO_HOB *gop;
127 printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
128 gop = GET_GUID_HOB_DATA(vbt_hob);
130 fb_add_framebuffer_info(gop->FrameBufferBase,
131 gop->GraphicsMode.HorizontalResolution,
132 gop->GraphicsMode.VerticalResolution,
133 gop->GraphicsMode.PixelsPerScanLine * 4,
134 32);
138 display_hob_info(fsp_info_header);
141 static void fsp_load(void)
143 struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
145 if (resume_from_stage_cache()) {
146 stage_cache_load_stage(STAGE_REFCODE, &fsp);
147 } else {
148 fsp_relocate(&fsp);
150 if (prog_entry(&fsp))
151 stage_cache_add(STAGE_REFCODE, &fsp);
154 /* FSP_INFO_HEADER is set as the program entry. */
155 fsp_update_fih(prog_entry(&fsp));
158 void intel_silicon_init(void)
160 fsp_load();
161 fsp_run_silicon_init(fsp_get_fih());
164 /* Initialize the UPD parameters for SiliconInit */
165 __weak void mainboard_silicon_init_params(
166 SILICON_INIT_UPD *params)