src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <delay.h>
   5 #include <gpio.h>
   6 #include <soc/gpio.h>
   7 #include <soc/smi.h>
   8 #include <stdlib.h>
   9 #include <boardid.h>
  10 #include <variant/gpio.h>
  11
  12 static const struct soc_amd_gpio gpio_set_stage_rom[] = {
  13         /* NVME_AUX_RESET_L */
  14         PAD_GPO(GPIO_40, HIGH),
  15         /* CLK_REQ0_L - WIFI */
  16         PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
  17         /* CLK_REQ1_L - SD Card */
  18         PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
  19         /* CLK_REQ4_L - SSD */
  20         PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
  21         /* SD_AUX_RESET_L */
  22         PAD_GPO(GPIO_142, HIGH),
  23 };
  24
  25 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
  26
  27         /* PWR_BTN_L */
  28         PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),
  29         /* SYS_RESET_L */
  30         PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
  31         /* PCIE_WAKE_L */
  32         PAD_NF(GPIO_2, WAKE_L, PULL_UP),
  33         /* PEN_DETECT_ODL */
  34         PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3),
  35         /* PEN_POWER_EN - Enabled*/
  36         PAD_GPO(GPIO_5, HIGH),
  37         /* FPMCU_INT_L */
  38         PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW),
  39         /* I2S_SDIN */
  40         PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
  41         /* I2S_LRCLK - Bit banged in depthcharge */
  42         PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
  43         /* TOUCHPAD_INT_ODL */
  44         PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
  45         /* S0iX SLP - (unused - goes to EC & FPMCU */
  46         PAD_GPI(GPIO_10, PULL_UP),
  47         /* FPMCU_RST_L */
  48         PAD_GPO(GPIO_11, HIGH),
  49         /* USI_INT_ODL */
  50         PAD_GPI(GPIO_12, PULL_UP),
  51         /* EN_PWR_TOUCHPAD_PS2 */
  52         PAD_GPO(GPIO_13, HIGH),
  53         /* BT_DISABLE */
  54         PAD_GPO(GPIO_14, LOW),
  55         /* USB_OC0_L - USB C0 + USB A0 */
  56         PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),
  57         /* USB_OC1_L - USB C1 + USB A1 */
  58         PAD_NF(GPIO_17, USB_OC1_L, PULL_UP),
  59         /* WIFI_DISABLE */
  60         PAD_GPO(GPIO_18, LOW),
  61         /* EMMC_CMD */
  62         PAD_NF(GPIO_21, EMMC_CMD, PULL_UP),
  63         /* EC_FCH_SCI_ODL */
  64         PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
  65         /* AC_PRES */
  66         PAD_NF(GPIO_23, AC_PRES, PULL_UP),
  67         /* EC_FCH_WAKE_L */
  68         PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
  69         /*  EC_AP_INT_ODL (Sensor Framesync) */
  70         PAD_GPI(GPIO_31, PULL_UP),
  71         /* EN_PWR_FP */
  72         PAD_GPO(GPIO_32, HIGH),
  73         /* DMIC SEL */
  74         /*
  75          * Make sure Ext ROM Sharing is disabled before using this GPIO.  Otherwise SPI flash
  76          * access will be very slow.
  77          */
  78         PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
  79         /* EMMC_RESET */
  80         PAD_GPO(GPIO_68, LOW),
  81         /* FPMCU_BOOT0 - TODO: Check this */
  82         PAD_GPO(GPIO_69, LOW),
  83         /* EMMC_CLK */
  84         PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE),
  85         /* EMMC_DATA4 */
  86         PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE),
  87         /* EMMC_DATA6 */
  88         PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE),
  89         /* EN_PWR_CAMERA */
  90         PAD_GPO(GPIO_76, HIGH),
  91         /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */
  92         PAD_GPO(GPIO_85, HIGH),
  93         /* EMMC_DATA7 */
  94         PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE),
  95         /* EMMC_DATA5 */
  96         PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE),
  97         /*  EN_DEV_BEEP_L */
  98         PAD_GPO(GPIO_89, HIGH),
  99         /* Testpoint */
 100         PAD_GPI(GPIO_90, PULL_UP),
 101         /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */
 102         PAD_GPO(GPIO_91, LOW),
 103         /* EMMC_DATA0 */
 104         PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE),
 105         /* EMMC_DATA1 */
 106         PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE),
 107         /* EMMC_DATA2 */
 108         PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE),
 109         /* EMMC_DATA3 */
 110         PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE),
 111         /* EMMC_DS */
 112         PAD_NF(GPIO_109, EMMC_DS, PULL_NONE),
 113         /* I2C2_SCL - USI/Touchpad */
 114         PAD_NF(GPIO_113, I2C2_SCL, PULL_UP),
 115         /* I2C2_SDA - USI/Touchpad */
 116         PAD_NF(GPIO_114, I2C2_SDA, PULL_UP),
 117         /* KBRST_L */
 118         PAD_NF(GPIO_129, KBRST_L, PULL_UP),
 119         /* EC_IN_RW_OD */
 120         PAD_GPI(GPIO_130, PULL_UP),
 121         /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
 122         PAD_GPI(GPIO_135, PULL_NONE),
 123         /* BIOS_FLASH_WP_ODL */
 124         PAD_GPI(GPIO_137, PULL_NONE),
 125         /* DEV_BEEP_BCLK */
 126         PAD_GPI(GPIO_139, PULL_NONE),
 127         /* USI_RESET */
 128         PAD_GPO(GPIO_140, HIGH),
 129         /* UART1_RXD - FPMCU */
 130         PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
 131         /* UART1_TXD - FPMCU */
 132         PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
 133         /* USI_REPORT_EN */
 134         /* TODO: Driver resets this later.  Do we want it high or low initially? */
 135         PAD_GPO(GPIO_144, HIGH),
 136 };
 137
 138 const __weak
 139 struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
 140 {
 141         *size = ARRAY_SIZE(gpio_set_stage_rom);
 142         return gpio_set_stage_rom;
 143 }
 144
 145 const __weak
 146 struct soc_amd_gpio *variant_base_gpio_table(size_t *size)
 147 {
 148         *size = ARRAY_SIZE(gpio_set_stage_ram);
 149         return gpio_set_stage_ram;
 150 }
 151
 152 /*
 153  * This function is still needed for boards that sets gevents above 23
 154  * that will generate SCI or SMI. Normally this function
 155  * points to a table of gevents and what needs to be set. The code that
 156  * calls it was modified so that when this function returns NULL then the
 157  * caller does nothing.
 158  */
 159 const __weak struct sci_source *variant_gpe_table(size_t *num)
 160 {
 161         return NULL;
 162 }
 163
 164 static void wifi_power_reset_configure_active_low_power(void)
 165 {
 166         /*
 167          * Configure WiFi GPIOs such that:
 168          * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device.
 169          * - Enable power to WiFi using EN_PWR_WIFI_L.
 170          * - Wait for 50ms after power to WiFi is enabled.
 171          * - Deassert WIFI_AUX_RESET_L.
 172          */
 173         static const struct soc_amd_gpio v3_wifi_table[] = {
 174                 /* WIFI_AUX_RESET_L */
 175                 PAD_GPO(GPIO_86, LOW),
 176                 /* EN_PWR_WIFI_L */
 177                 PAD_GPO(GPIO_42, LOW),
 178         };
 179         program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 180
 181         mdelay(50);
 182         gpio_set(GPIO_86, 1);
 183 }
 184
 185 static void wifi_power_reset_configure_active_high_power(void)
 186 {
 187         /*
 188          * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L
 189          * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be
 190          * set low before driving it high to trigger a WiFi power cycle to meet PCIe
 191          * requirements. Thus, configura GPIOs such that:
 192          * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device
 193          * - Disable power to WiFi.
 194          * - Wait 10ms for WiFi power to go low.
 195          * - Enable power to WiFi using EN_PWR_WIFI.
 196          * - Deassert WIFI_AUX_RESET_L.
 197          */
 198         static const struct soc_amd_gpio v3_wifi_table[] = {
 199                 /* WIFI_AUX_RESET_L */
 200                 PAD_GPO(GPIO_86, LOW),
 201                 /* EN_PWR_WIFI */
 202                 PAD_GPO(GPIO_42, LOW),
 203         };
 204         program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 205
 206         mdelay(10);
 207         gpio_set(GPIO_42, 1);
 208         mdelay(50);
 209         gpio_set(GPIO_86, 1);
 210 }
 211
 212 static void wifi_power_reset_configure_v3(void)
 213 {
 214         if (variant_has_active_low_wifi_power())
 215                 wifi_power_reset_configure_active_low_power();
 216         else
 217                 wifi_power_reset_configure_active_high_power();
 218 }
 219
 220 static void wifi_power_reset_configure_pre_v3(void)
 221 {
 222         /*
 223          * Configure WiFi GPIOs such that:
 224          * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device.
 225          * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET#
 226          *   deassertion causing WiFi to enter a bad state.
 227          * - Wait 10ms for WiFi power to go low.
 228          * - Enable power to WiFi using EN_PWR_WIFI.
 229          * - Wait for 50ms after power to WiFi is enabled.
 230          * - Deassert WIFI_AUX_RESET_L.
 231          */
 232         static const struct soc_amd_gpio pre_v3_wifi_table[] = {
 233                 /* WIFI_AUX_RESET_L */
 234                 PAD_GPO(GPIO_42, LOW),
 235                 /* EN_PWR_WIFI */
 236                 PAD_GPO(GPIO_29, LOW),
 237         };
 238         program_gpios(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
 239
 240         mdelay(10);
 241         gpio_set(GPIO_29, 1);
 242         mdelay(50);
 243         gpio_set(GPIO_42, 1);
 244 }
 245
 246 __weak void variant_pcie_power_reset_configure(void)
 247 {
 248         if (variant_uses_v3_schematics())
 249                 wifi_power_reset_configure_v3();
 250         else
 251                 wifi_power_reset_configure_pre_v3();
 252 }
 253
 254 static const struct soc_amd_gpio gpio_sleep_table[] = {
 255         /* NVME_AUX_RESET_L */
 256         PAD_GPO(GPIO_40, LOW),
 257         /* EN_PWR_CAMERA */
 258         PAD_GPO(GPIO_76, LOW),
 259 };
 260
 261 const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ)
 262 {
 263         *size = ARRAY_SIZE(gpio_sleep_table);
 264         return gpio_sleep_table;
 265 }