src/southbridge/intel/lynxpoint/me.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _INTEL_ME_H
  18 #define _INTEL_ME_H
  19
  20 #include <compiler.h>
  21
  22 #define ME_RETRY                100000  /* 1 second */
  23 #define ME_DELAY                10      /* 10 us */
  24
  25 /*
  26  * Management Engine PCI registers
  27  */
  28
  29 #define PCI_CPU_DEVICE          PCI_DEV(0,0,0)
  30 #define PCI_CPU_MEBASE_L        0x70    /* Set by MRC */
  31 #define PCI_CPU_MEBASE_H        0x74    /* Set by MRC */
  32
  33 #define PCI_ME_HFS              0x40
  34 #define  ME_HFS_CWS_RESET       0
  35 #define  ME_HFS_CWS_INIT        1
  36 #define  ME_HFS_CWS_REC         2
  37 #define  ME_HFS_CWS_NORMAL      5
  38 #define  ME_HFS_CWS_WAIT        6
  39 #define  ME_HFS_CWS_TRANS       7
  40 #define  ME_HFS_CWS_INVALID     8
  41 #define  ME_HFS_STATE_PREBOOT   0
  42 #define  ME_HFS_STATE_M0_UMA    1
  43 #define  ME_HFS_STATE_M3        4
  44 #define  ME_HFS_STATE_M0        5
  45 #define  ME_HFS_STATE_BRINGUP   6
  46 #define  ME_HFS_STATE_ERROR     7
  47 #define  ME_HFS_ERROR_NONE      0
  48 #define  ME_HFS_ERROR_UNCAT     1
  49 #define  ME_HFS_ERROR_IMAGE     3
  50 #define  ME_HFS_ERROR_DEBUG     4
  51 #define  ME_HFS_MODE_NORMAL     0
  52 #define  ME_HFS_MODE_DEBUG      2
  53 #define  ME_HFS_MODE_DIS        3
  54 #define  ME_HFS_MODE_OVER_JMPR  4
  55 #define  ME_HFS_MODE_OVER_MEI   5
  56 #define  ME_HFS_BIOS_DRAM_ACK   1
  57 #define  ME_HFS_ACK_NO_DID      0
  58 #define  ME_HFS_ACK_RESET       1
  59 #define  ME_HFS_ACK_PWR_CYCLE   2
  60 #define  ME_HFS_ACK_S3          3
  61 #define  ME_HFS_ACK_S4          4
  62 #define  ME_HFS_ACK_S5          5
  63 #define  ME_HFS_ACK_GBL_RESET   6
  64 #define  ME_HFS_ACK_CONTINUE    7
  65
  66 struct me_hfs {
  67         u32 working_state: 4;
  68         u32 mfg_mode: 1;
  69         u32 fpt_bad: 1;
  70         u32 operation_state: 3;
  71         u32 fw_init_complete: 1;
  72         u32 ft_bup_ld_flr: 1;
  73         u32 update_in_progress: 1;
  74         u32 error_code: 4;
  75         u32 operation_mode: 4;
  76         u32 reserved: 4;
  77         u32 boot_options_present: 1;
  78         u32 ack_data: 3;
  79         u32 bios_msg_ack: 4;
  80 } __packed;
  81
  82 #define PCI_ME_UMA              0x44
  83
  84 struct me_uma {
  85         u32 size: 6;
  86         u32 reserved_1: 10;
  87         u32 valid: 1;
  88         u32 reserved_0: 14;
  89         u32 set_to_one: 1;
  90 } __packed;
  91
  92 #define PCI_ME_H_GS             0x4c
  93 #define  ME_INIT_DONE           1
  94 #define  ME_INIT_STATUS_SUCCESS 0
  95 #define  ME_INIT_STATUS_NOMEM   1
  96 #define  ME_INIT_STATUS_ERROR   2
  97 #define  ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
  98
  99 struct me_did {
 100         u32 uma_base: 16;
 101         u32 reserved: 7;
 102         u32 rapid_start: 1;
 103         u32 status: 4;
 104         u32 init_done: 4;
 105 } __packed;
 106
 107 /*
 108  * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
 109  * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
 110  */
 111 #define PCI_ME_HFS2             0x48
 112 /* Infrastructure Progress Values */
 113 #define  ME_HFS2_PHASE_ROM              0
 114 #define  ME_HFS2_PHASE_BUP              1
 115 #define  ME_HFS2_PHASE_UKERNEL          2
 116 #define  ME_HFS2_PHASE_POLICY           3
 117 #define  ME_HFS2_PHASE_MODULE_LOAD      4
 118 #define  ME_HFS2_PHASE_UNKNOWN          5
 119 #define  ME_HFS2_PHASE_HOST_COMM        6
 120 /* Current State - Based on Infra Progress values. */
 121 /*       ROM State */
 122 #define  ME_HFS2_STATE_ROM_BEGIN 0
 123 #define  ME_HFS2_STATE_ROM_DISABLE 6
 124 /*       BUP State */
 125 #define  ME_HFS2_STATE_BUP_INIT 0
 126 #define  ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
 127 #define  ME_HFS2_STATE_BUP_FLOW_DET 4
 128 #define  ME_HFS2_STATE_BUP_VSCC_ERR 8
 129 #define  ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
 130 #define  ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
 131 #define  ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
 132 #define  ME_HFS2_STATE_BUP_M3 0x11
 133 #define  ME_HFS2_STATE_BUP_M0 0x12
 134 #define  ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
 135 #define  ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
 136 #define  ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
 137 #define  ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
 138 #define  ME_HFS2_STATE_BUP_T32_MISSING 0x1c
 139 #define  ME_HFS2_STATE_BUP_WAIT_DID 0x1f
 140 #define  ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
 141 #define  ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
 142 #define  ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
 143 #define  ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
 144 #define  ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
 145 #define  ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
 146 #define  ME_HFS2_STATE_BUP_M0_CLK 0x26
 147 #define  ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
 148 #define  ME_HFS2_STATE_BUP_TEMP_DIS 0x28
 149 #define  ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
 150 /*       Policy Module State */
 151 #define  ME_HFS2_STATE_POLICY_ENTRY 0
 152 #define  ME_HFS2_STATE_POLICY_RCVD_S3 3
 153 #define  ME_HFS2_STATE_POLICY_RCVD_S4 4
 154 #define  ME_HFS2_STATE_POLICY_RCVD_S5 5
 155 #define  ME_HFS2_STATE_POLICY_RCVD_UPD 6
 156 #define  ME_HFS2_STATE_POLICY_RCVD_PCR 7
 157 #define  ME_HFS2_STATE_POLICY_RCVD_NPCR 8
 158 #define  ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
 159 #define  ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
 160 #define  ME_HFS2_STATE_POLICY_RCVD_DID 0xb
 161 #define  ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
 162 #define  ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
 163 #define  ME_HFS2_STATE_POLICY_FPB_ERR 0xe
 164 #define  ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
 165 #define  ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
 166 /* Current PM Event Values */
 167 #define  ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
 168 #define  ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
 169 #define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
 170 #define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
 171 #define  ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
 172 #define  ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
 173 #define  ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
 174 #define  ME_HFS2_PMEVENT_S0MO_SXM3 7
 175 #define  ME_HFS2_PMEVENT_SXM3_S0M0 8
 176 #define  ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
 177 #define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
 178 #define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
 179 #define  ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
 180
 181 struct me_hfs2 {
 182         u32 bist_in_progress: 1;
 183         u32 reserved1: 2;
 184         u32 invoke_mebx: 1;
 185         u32 cpu_replaced_sts: 1;
 186         u32 mbp_rdy: 1;
 187         u32 mfs_failure: 1;
 188         u32 warm_reset_request: 1;
 189         u32 cpu_replaced_valid: 1;
 190         u32 reserved2: 4;
 191         u32 mbp_cleared: 1;
 192         u32 reserved3: 2;
 193         u32 current_state: 8;
 194         u32 current_pmevent: 4;
 195         u32 progress_code: 4;
 196 } __packed;
 197
 198 #define PCI_ME_H_GS2            0x70
 199 #define   PCI_ME_MBP_GIVE_UP    0x01
 200
 201 #define PCI_ME_HERES            0xbc
 202 #define  PCI_ME_EXT_SHA1        0x00
 203 #define  PCI_ME_EXT_SHA256      0x02
 204 #define PCI_ME_HER(x)           (0xc0+(4*(x)))
 205
 206 struct me_heres {
 207         u32 extend_reg_algorithm: 4;
 208         u32 reserved: 26;
 209         u32 extend_feature_present: 1;
 210         u32 extend_reg_valid: 1;
 211 } __packed;
 212
 213 /*
 214  * Management Engine MEI registers
 215  */
 216
 217 #define MEI_H_CB_WW             0x00
 218 #define MEI_H_CSR               0x04
 219 #define MEI_ME_CB_RW            0x08
 220 #define MEI_ME_CSR_HA           0x0c
 221
 222 struct mei_csr {
 223         u32 interrupt_enable: 1;
 224         u32 interrupt_status: 1;
 225         u32 interrupt_generate: 1;
 226         u32 ready: 1;
 227         u32 reset: 1;
 228         u32 reserved: 3;
 229         u32 buffer_read_ptr: 8;
 230         u32 buffer_write_ptr: 8;
 231         u32 buffer_depth: 8;
 232 } __packed;
 233
 234 #define MEI_ADDRESS_CORE        0x01
 235 #define MEI_ADDRESS_AMT         0x02
 236 #define MEI_ADDRESS_RESERVED    0x03
 237 #define MEI_ADDRESS_WDT         0x04
 238 #define MEI_ADDRESS_MKHI        0x07
 239 #define MEI_ADDRESS_ICC         0x08
 240 #define MEI_ADDRESS_THERMAL     0x09
 241
 242 #define MEI_HOST_ADDRESS        0
 243
 244 struct mei_header {
 245         u32 client_address: 8;
 246         u32 host_address: 8;
 247         u32 length: 9;
 248         u32 reserved: 6;
 249         u32 is_complete: 1;
 250 } __packed;
 251
 252 #define MKHI_GROUP_ID_CBM       0x00
 253 #define MKHI_GROUP_ID_FWCAPS    0x03
 254 #define MKHI_GROUP_ID_MDES      0x08
 255 #define MKHI_GROUP_ID_GEN       0xff
 256
 257 #define MKHI_GLOBAL_RESET       0x0b
 258
 259 #define MKHI_FWCAPS_GET_RULE    0x02
 260
 261 #define MKHI_MDES_ENABLE        0x09
 262
 263 #define MKHI_GET_FW_VERSION     0x02
 264 #define MKHI_END_OF_POST        0x0c
 265 #define MKHI_FEATURE_OVERRIDE   0x14
 266
 267 struct mkhi_header {
 268         u32 group_id: 8;
 269         u32 command: 7;
 270         u32 is_response: 1;
 271         u32 reserved: 8;
 272         u32 result: 8;
 273 } __packed;
 274
 275 struct me_fw_version {
 276         u16 code_minor;
 277         u16 code_major;
 278         u16 code_build_number;
 279         u16 code_hot_fix;
 280         u16 recovery_minor;
 281         u16 recovery_major;
 282         u16 recovery_build_number;
 283         u16 recovery_hot_fix;
 284 } __packed;
 285
 286 /* ICC Messages */
 287 #define ICC_SET_CLOCK_ENABLES           0x3
 288 #define ICC_API_VERSION_LYNXPOINT       0x00030000
 289
 290 struct icc_header {
 291         u32 api_version;
 292         u32 icc_command;
 293         u32 icc_status;
 294         u32 length;
 295         u32 reserved;
 296 } __packed;
 297
 298 struct icc_clock_enables_msg {
 299         u32 clock_enables;
 300         u32 clock_mask;
 301         u32 no_response: 1;
 302         u32 reserved: 31;
 303 } __packed;
 304
 305 #define HECI_EOP_STATUS_SUCCESS       0x0
 306 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
 307
 308 #define CBM_RR_GLOBAL_RESET     0x01
 309
 310 #define GLOBAL_RESET_BIOS_MRC   0x01
 311 #define GLOBAL_RESET_BIOS_POST  0x02
 312 #define GLOBAL_RESET_MEBX       0x03
 313
 314 struct me_global_reset {
 315         u8 request_origin;
 316         u8 reset_type;
 317 } __packed;
 318
 319 typedef enum {
 320         ME_NORMAL_BIOS_PATH,
 321         ME_S3WAKE_BIOS_PATH,
 322         ME_ERROR_BIOS_PATH,
 323         ME_RECOVERY_BIOS_PATH,
 324         ME_DISABLE_BIOS_PATH,
 325         ME_FIRMWARE_UPDATE_BIOS_PATH,
 326 } me_bios_path;
 327
 328 /* Defined in me_status.c for both romstage and ramstage */
 329 void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2);
 330
 331 #ifdef __PRE_RAM__
 332 void intel_early_me_status(void);
 333 int intel_early_me_init(void);
 334 int intel_early_me_uma_size(void);
 335 int intel_early_me_init_done(u8 status);
 336 #endif
 337
 338 #ifdef __SMM__
 339 void intel_me_finalize_smm(void);
 340 void intel_me8_finalize_smm(void);
 341 #endif
 342
 343 /*
 344  * ME to BIOS Payload Datastructures and definitions. The ordering of the
 345  * structures follows the ordering in the ME9 BWG.
 346  */
 347
 348 #define MBP_APPID_KERNEL 1
 349 #define MBP_APPID_INTEL_AT 3
 350 #define MBP_APPID_HWA 4
 351 #define MBP_APPID_ICC 5
 352 #define MBP_APPID_NFC 6
 353 /* Kernel items: */
 354 #define MBP_KERNEL_FW_VER_ITEM 1
 355 #define MBP_KERNEL_FW_CAP_ITEM 2
 356 #define MBP_KERNEL_ROM_BIST_ITEM 3
 357 #define MBP_KERNEL_PLAT_KEY_ITEM 4
 358 #define MBP_KERNEL_FW_TYPE_ITEM 5
 359 #define MBP_KERNEL_MFS_FAILURE_ITEM 6
 360 #define MBP_KERNEL_PLAT_TIME_ITEM 7
 361 /* Intel AT items: */
 362 #define MBP_INTEL_AT_STATE_ITEM 1
 363 /* ICC Items: */
 364 #define MBP_ICC_PROFILE_ITEM 1
 365 /* HWA Items: */
 366 #define MBP_HWA_REQUEST_ITEM 1
 367 /* NFC Items: */
 368 #define MBP_NFC_SUPPORT_DATA_ITEM 1
 369
 370 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
 371 #define MBP_IDENT(appid, item) \
 372         MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
 373
 374 typedef  struct {
 375         u32  mbp_size    : 8;
 376         u32  num_entries : 8;
 377         u32  rsvd        : 16;
 378 } __packed mbp_header;
 379
 380 typedef struct {
 381         u32  app_id  : 8;
 382         u32  item_id : 8;
 383         u32  length  : 8;
 384         u32  rsvd    : 8;
 385 }  __packed mbp_item_header;
 386
 387 typedef struct {
 388         u32       major_version  : 16;
 389         u32       minor_version  : 16;
 390         u32       hotfix_version : 16;
 391         u32       build_version  : 16;
 392 } __packed mbp_fw_version_name;
 393
 394 typedef struct {
 395         u32  full_net           : 1;
 396         u32  std_net            : 1;
 397         u32  manageability      : 1;
 398         u32  reserved_2         : 2;
 399         u32  intel_at           : 1;
 400         u32  intel_cls          : 1;
 401         u32  reserved           : 3;
 402         u32  intel_mpc          : 1;
 403         u32  icc_over_clocking  : 1;
 404         u32  pavp               : 1;
 405         u32  reserved_1         : 4;
 406         u32  ipv6               : 1;
 407         u32  kvm                : 1;
 408         u32  och                : 1;
 409         u32  vlan               : 1;
 410         u32  tls                : 1;
 411         u32  reserved_4         : 1;
 412         u32  wlan               : 1;
 413         u32  reserved_5         : 8;
 414 } __packed mbp_mefwcaps;
 415
 416 typedef struct {
 417         u16        device_id;
 418         u16        fuse_test_flags;
 419         u32        umchid[4];
 420 }  __packed mbp_rom_bist_data;
 421
 422 typedef struct {
 423         u32        key[8];
 424 } mbp_platform_key;
 425
 426 typedef struct {
 427         u32 mobile:             1;
 428         u32 desktop:            1;
 429         u32 server:             1;
 430         u32 workstation:        1;
 431         u32 corporate:          1;
 432         u32 consumer:           1;
 433         u32 regular_super_sku:  1;
 434         u32 rsvd:               1;
 435         u32 image_type:         4;
 436         u32 brand:              4;
 437         u32 rsvd1:              16;
 438 }  __packed mbp_me_firmware_type;
 439
 440 typedef struct {
 441         mbp_me_firmware_type rule_data;
 442         u8                   available;
 443 } mbp_plat_type;
 444
 445 typedef struct {
 446         u16 icc_start_address;
 447         u16 mask;
 448 } __packed icc_address_mask;
 449
 450 typedef struct {
 451         u8        num_icc_profiles;
 452         u8        icc_profile_soft_strap;
 453         u8        icc_profile_index;
 454         u8        reserved;
 455         u32       icc_reg_bundles;
 456         icc_address_mask icc_address_mask[0];
 457 } __packed mbp_icc_profile;
 458
 459 typedef struct {
 460         u16  lock_state              : 1;
 461         u16  authenticate_module     : 1;
 462         u16  s3authentication        : 1;
 463         u16  flash_wear_out          : 1;
 464         u16  flash_variable_security : 1;
 465         u16  reserved                : 11;
 466 } __packed tdt_state_flag;
 467
 468 typedef struct {
 469         u8           state;
 470         u8           last_theft_trigger;
 471         tdt_state_flag  flags;
 472 }  __packed mbp_at_state;
 473
 474 typedef struct {
 475         u32 wake_event_mrst_time_ms;
 476         u32 mrst_pltrst_time_ms;
 477         u32 pltrst_cpurst_time_ms;
 478 } __packed mbp_plat_time;
 479
 480 typedef struct {
 481         u32 device_type : 2;
 482         u32 reserved    : 30;
 483 } __packed mbp_nfc_data;
 484
 485 typedef struct {
 486         mbp_fw_version_name  *fw_version_name;
 487         mbp_mefwcaps         *fw_capabilities;
 488         mbp_rom_bist_data    *rom_bist_data;
 489         mbp_platform_key     *platform_key;
 490         mbp_plat_type        *fw_plat_type;
 491         mbp_icc_profile      *icc_profile;
 492         mbp_at_state         *at_state;
 493         u32                  *mfsintegrity;
 494         mbp_plat_time        *plat_time;
 495         mbp_nfc_data         *nfc_data;
 496 } me_bios_payload;
 497
 498 struct me_fwcaps {
 499         u32 id;
 500         u8 length;
 501         mbp_mefwcaps caps_sku;
 502         u8 reserved[3];
 503 } __packed;
 504
 505 #endif /* _INTEL_ME_H */