src/southbridge/intel/ibexpeak/me.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _INTEL_ME_H
  18 #define _INTEL_ME_H
  19
  20 #include <compiler.h>
  21
  22 #define ME_RETRY                100000  /* 1 second */
  23 #define ME_DELAY                10      /* 10 us */
  24
  25 /*
  26  * Management Engine PCI registers
  27  */
  28
  29 #define PCI_CPU_DEVICE          PCI_DEV(0,0,0)
  30 #define PCI_CPU_MEBASE_L        0x70    /* Set by MRC */
  31 #define PCI_CPU_MEBASE_H        0x74    /* Set by MRC */
  32
  33 #define PCI_ME_HFS              0x40
  34 #define  ME_HFS_CWS_RESET       0
  35 #define  ME_HFS_CWS_INIT        1
  36 #define  ME_HFS_CWS_REC         2
  37 #define  ME_HFS_CWS_NORMAL      5
  38 #define  ME_HFS_CWS_WAIT        6
  39 #define  ME_HFS_CWS_TRANS       7
  40 #define  ME_HFS_CWS_INVALID     8
  41 #define  ME_HFS_STATE_PREBOOT   0
  42 #define  ME_HFS_STATE_M0_UMA    1
  43 #define  ME_HFS_STATE_M3        4
  44 #define  ME_HFS_STATE_M0        5
  45 #define  ME_HFS_STATE_BRINGUP   6
  46 #define  ME_HFS_STATE_ERROR     7
  47 #define  ME_HFS_ERROR_NONE      0
  48 #define  ME_HFS_ERROR_UNCAT     1
  49 #define  ME_HFS_ERROR_IMAGE     3
  50 #define  ME_HFS_ERROR_DEBUG     4
  51 #define  ME_HFS_MODE_NORMAL     0
  52 #define  ME_HFS_MODE_DEBUG      2
  53 #define  ME_HFS_MODE_DIS        3
  54 #define  ME_HFS_MODE_OVER_JMPR  4
  55 #define  ME_HFS_MODE_OVER_MEI   5
  56 #define  ME_HFS_BIOS_DRAM_ACK   1
  57 #define  ME_HFS_ACK_NO_DID      0
  58 #define  ME_HFS_ACK_RESET       1
  59 #define  ME_HFS_ACK_PWR_CYCLE   2
  60 #define  ME_HFS_ACK_S3          3
  61 #define  ME_HFS_ACK_S4          4
  62 #define  ME_HFS_ACK_S5          5
  63 #define  ME_HFS_ACK_GBL_RESET   6
  64 #define  ME_HFS_ACK_CONTINUE    7
  65
  66 struct me_hfs {
  67         u32 working_state: 4;
  68         u32 mfg_mode: 1;
  69         u32 fpt_bad: 1;
  70         u32 operation_state: 3;
  71         u32 fw_init_complete: 1;
  72         u32 ft_bup_ld_flr: 1;
  73         u32 update_in_progress: 1;
  74         u32 error_code: 4;
  75         u32 operation_mode: 4;
  76         u32 reserved: 4;
  77         u32 boot_options_present: 1;
  78         u32 ack_data: 3;
  79         u32 bios_msg_ack: 4;
  80 } __packed;
  81
  82 #define PCI_ME_UMA              0x44
  83
  84 struct me_uma {
  85         u32 size: 6;
  86         u32 reserved_1: 10;
  87         u32 valid: 1;
  88         u32 reserved_0: 14;
  89         u32 set_to_one: 1;
  90 } __packed;
  91
  92 #define PCI_ME_H_GS             0x4c
  93 #define  ME_INIT_DONE           1
  94 #define  ME_INIT_STATUS_SUCCESS 0
  95 #define  ME_INIT_STATUS_NOMEM   1
  96 #define  ME_INIT_STATUS_ERROR   2
  97
  98 struct me_did {
  99         u32 uma_base: 16;
 100         u32 reserved: 8;
 101         u32 status: 4;
 102         u32 init_done: 4;
 103 } __packed;
 104
 105 #define PCI_ME_GMES             0x48
 106 #define  ME_GMES_PHASE_ROM      0
 107 #define  ME_GMES_PHASE_BUP      1
 108 #define  ME_GMES_PHASE_UKERNEL  2
 109 #define  ME_GMES_PHASE_POLICY   3
 110 #define  ME_GMES_PHASE_MODULE   4
 111 #define  ME_GMES_PHASE_UNKNOWN  5
 112 #define  ME_GMES_PHASE_HOST     6
 113
 114 struct me_gmes {
 115         u32 bist_in_prog : 1;
 116         u32 icc_prog_sts : 2;
 117         u32 invoke_mebx : 1;
 118         u32 cpu_replaced_sts : 1;
 119         u32 mbp_rdy : 1;
 120         u32 mfs_failure : 1;
 121         u32 warm_rst_req_for_df : 1;
 122         u32 cpu_replaced_valid : 1;
 123         u32 reserved_1 : 2;
 124         u32 fw_upd_ipu : 1;
 125         u32 reserved_2 : 4;
 126         u32 current_state: 8;
 127         u32 current_pmevent: 4;
 128         u32 progress_code: 4;
 129 } __packed;
 130
 131 #define PCI_ME_HERES            0xbc
 132 #define  PCI_ME_EXT_SHA1        0x00
 133 #define  PCI_ME_EXT_SHA256      0x02
 134 #define PCI_ME_HER(x)           (0xc0+(4*(x)))
 135
 136 struct me_heres {
 137         u32 extend_reg_algorithm: 4;
 138         u32 reserved: 26;
 139         u32 extend_feature_present: 1;
 140         u32 extend_reg_valid: 1;
 141 } __packed;
 142
 143 /*
 144  * Management Engine MEI registers
 145  */
 146
 147 #define MEI_H_CB_WW             0x00
 148 #define MEI_H_CSR               0x04
 149 #define MEI_ME_CB_RW            0x08
 150 #define MEI_ME_CSR_HA           0x0c
 151
 152 struct mei_csr {
 153         u32 interrupt_enable: 1;
 154         u32 interrupt_status: 1;
 155         u32 interrupt_generate: 1;
 156         u32 ready: 1;
 157         u32 reset: 1;
 158         u32 reserved: 3;
 159         u32 buffer_read_ptr: 8;
 160         u32 buffer_write_ptr: 8;
 161         u32 buffer_depth: 8;
 162 } __packed;
 163
 164 #define MEI_ADDRESS_CORE        0x01
 165 #define MEI_ADDRESS_AMT         0x02
 166 #define MEI_ADDRESS_RESERVED    0x03
 167 #define MEI_ADDRESS_WDT         0x04
 168 #define MEI_ADDRESS_MKHI        0x07
 169 #define MEI_ADDRESS_ICC         0x08
 170 #define MEI_ADDRESS_THERMAL     0x09
 171
 172 #define MEI_HOST_ADDRESS        0
 173
 174 struct mei_header {
 175         u32 client_address: 8;
 176         u32 host_address: 8;
 177         u32 length: 9;
 178         u32 reserved: 6;
 179         u32 is_complete: 1;
 180 } __packed;
 181
 182 #define MKHI_GROUP_ID_CBM       0x00
 183 #define MKHI_GROUP_ID_FWCAPS    0x03
 184 #define MKHI_GROUP_ID_MDES      0x08
 185 #define MKHI_GROUP_ID_GEN       0xff
 186
 187 #define MKHI_GLOBAL_RESET       0x0b
 188
 189 #define MKHI_FWCAPS_GET_RULE    0x02
 190
 191 #define MKHI_MDES_ENABLE        0x09
 192
 193 #define MKHI_GET_FW_VERSION     0x02
 194 #define MKHI_SET_UMA            0x08
 195 #define MKHI_END_OF_POST        0x0c
 196 #define MKHI_FEATURE_OVERRIDE   0x14
 197
 198 struct mkhi_header {
 199         u32 group_id: 8;
 200         u32 command: 7;
 201         u32 is_response: 1;
 202         u32 reserved: 8;
 203         u32 result: 8;
 204 } __packed;
 205
 206 struct me_fw_version {
 207         u16 code_minor;
 208         u16 code_major;
 209         u16 code_build_number;
 210         u16 code_hot_fix;
 211         u16 recovery_minor;
 212         u16 recovery_major;
 213         u16 recovery_build_number;
 214         u16 recovery_hot_fix;
 215 } __packed;
 216
 217
 218 #define HECI_EOP_STATUS_SUCCESS       0x0
 219 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
 220
 221 #define CBM_RR_GLOBAL_RESET     0x01
 222
 223 #define GLOBAL_RESET_BIOS_MRC   0x01
 224 #define GLOBAL_RESET_BIOS_POST  0x02
 225 #define GLOBAL_RESET_MEBX       0x03
 226
 227 struct me_global_reset {
 228         u8 request_origin;
 229         u8 reset_type;
 230 } __packed;
 231
 232 typedef enum {
 233         ME_NORMAL_BIOS_PATH,
 234         ME_S3WAKE_BIOS_PATH,
 235         ME_ERROR_BIOS_PATH,
 236         ME_RECOVERY_BIOS_PATH,
 237         ME_DISABLE_BIOS_PATH,
 238         ME_FIRMWARE_UPDATE_BIOS_PATH,
 239 } me_bios_path;
 240
 241 /* Defined in me_status.c for both romstage and ramstage */
 242 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 243
 244 #ifdef __PRE_RAM__
 245 void intel_early_me_status(void);
 246 int intel_early_me_init(void);
 247 int intel_early_me_uma_size(void);
 248 int intel_early_me_init_done(u8 status);
 249 #endif
 250
 251 #ifdef __SMM__
 252 void intel_me_finalize_smm(void);
 253 void intel_me8_finalize_smm(void);
 254 #endif
 255 typedef struct {
 256         u32       major_version  : 16;
 257         u32       minor_version  : 16;
 258         u32       hotfix_version : 16;
 259         u32       build_version  : 16;
 260 } __packed mbp_fw_version_name;
 261
 262 typedef struct {
 263         u8        num_icc_profiles;
 264         u8        icc_profile_soft_strap;
 265         u8        icc_profile_index;
 266         u8        reserved;
 267         u32       register_lock_mask[3];
 268 } __packed mbp_icc_profile;
 269
 270 typedef struct {
 271         u32  full_net           : 1;
 272         u32  std_net            : 1;
 273         u32  manageability      : 1;
 274         u32  small_business     : 1;
 275         u32  l3manageability    : 1;
 276         u32  intel_at           : 1;
 277         u32  intel_cls          : 1;
 278         u32  reserved           : 3;
 279         u32  intel_mpc          : 1;
 280         u32  icc_over_clocking  : 1;
 281         u32  pavp               : 1;
 282         u32  reserved_1         : 4;
 283         u32  ipv6               : 1;
 284         u32  kvm                : 1;
 285         u32  och                : 1;
 286         u32  vlan               : 1;
 287         u32  tls                : 1;
 288         u32  reserved_4         : 1;
 289         u32  wlan               : 1;
 290         u32  reserved_5         : 8;
 291 } __packed mefwcaps_sku;
 292
 293 typedef struct {
 294         u16  lock_state              : 1;
 295         u16  authenticate_module     : 1;
 296         u16  s3authentication        : 1;
 297         u16  flash_wear_out          : 1;
 298         u16  flash_variable_security : 1;
 299         u16  wwan3gpresent           : 1;
 300         u16  wwan3goob               : 1;
 301         u16  reserved                : 9;
 302 } __packed tdt_state_flag;
 303
 304 typedef struct {
 305         u8           state;
 306         u8           last_theft_trigger;
 307         tdt_state_flag  flags;
 308 }  __packed tdt_state_info;
 309
 310 typedef struct {
 311         u32  platform_target_usage_type  : 4;
 312         u32  platform_target_market_type : 2;
 313         u32  super_sku                   : 1;
 314         u32  reserved                    : 1;
 315         u32  intel_me_fw_image_type      : 4;
 316         u32  platform_brand              : 4;
 317         u32  reserved_1                  : 16;
 318 }  __packed platform_type_rule_data;
 319
 320 typedef struct {
 321         mefwcaps_sku fw_capabilities;
 322         u8      available;
 323 } mbp_fw_caps;
 324
 325 typedef struct {
 326         u16        device_id;
 327         u16        fuse_test_flags;
 328         u32        umchid[4];
 329 }  __packed mbp_rom_bist_data;
 330
 331 typedef struct {
 332         u32        key[8];
 333 } mbp_platform_key;
 334
 335 typedef struct {
 336         platform_type_rule_data rule_data;
 337         u8                available;
 338 } mbp_plat_type;
 339
 340 typedef struct {
 341         mbp_fw_version_name fw_version_name;
 342         mbp_fw_caps         fw_caps_sku;
 343         mbp_rom_bist_data   rom_bist_data;
 344         mbp_platform_key    platform_key;
 345         mbp_plat_type       fw_plat_type;
 346         mbp_icc_profile     icc_profile;
 347         tdt_state_info      at_state;
 348         u32                 mfsintegrity;
 349 } me_bios_payload;
 350
 351 typedef  struct {
 352         u32  mbp_size    : 8;
 353         u32  num_entries : 8;
 354         u32  rsvd        : 16;
 355 } __packed mbp_header;
 356
 357 typedef struct {
 358         u32  app_id  : 8;
 359         u32  item_id : 8;
 360         u32  length  : 8;
 361         u32  rsvd    : 8;
 362 }  __packed mbp_item_header;
 363
 364 struct me_fwcaps {
 365         u32 id;
 366         u8 length;
 367         mefwcaps_sku caps_sku;
 368         u8 reserved[3];
 369 } __packed;
 370
 371 #endif /* _INTEL_ME_H */