src/southbridge/intel/fsp_rangeley/gpio.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef INTEL_RANGELEY_GPIO_H
  18 #define INTEL_RANGELEY_GPIO_H
  19
  20 #include <compiler.h>
  21
  22 #define GPIO_MODE_NATIVE        0
  23 #define GPIO_MODE_GPIO          1
  24 #define GPIO_MODE_NONE          1
  25
  26 #define GPIO_DIR_OUTPUT         0
  27 #define GPIO_DIR_INPUT          1
  28
  29 #define GPIO_LEVEL_LOW          0
  30 #define GPIO_LEVEL_HIGH         1
  31
  32 #define GPIO_TPE_DISABLE                0
  33 #define GPIO_TPE_ENABLE         1
  34
  35 #define GPIO_TNE_DISABLE                0
  36 #define GPIO_TNE_ENABLE         1
  37
  38 #define GPIO_TS_DISABLE         0
  39 #define GPIO_TS_ENABLE          1
  40
  41 #define GPIO_WE_DISABLE         0
  42 #define GPIO_WE_ENABLE          1
  43
  44 struct soc_gpio {
  45         u32 gpio0 : 1;
  46         u32 gpio1 : 1;
  47         u32 gpio2 : 1;
  48         u32 gpio3 : 1;
  49         u32 gpio4 : 1;
  50         u32 gpio5 : 1;
  51         u32 gpio6 : 1;
  52         u32 gpio7 : 1;
  53         u32 gpio8 : 1;
  54         u32 gpio9 : 1;
  55         u32 gpio10 : 1;
  56         u32 gpio11 : 1;
  57         u32 gpio12 : 1;
  58         u32 gpio13 : 1;
  59         u32 gpio14 : 1;
  60         u32 gpio15 : 1;
  61         u32 gpio16 : 1;
  62         u32 gpio17 : 1;
  63         u32 gpio18 : 1;
  64         u32 gpio19 : 1;
  65         u32 gpio20 : 1;
  66         u32 gpio21 : 1;
  67         u32 gpio22 : 1;
  68         u32 gpio23 : 1;
  69         u32 gpio24 : 1;
  70         u32 gpio25 : 1;
  71         u32 gpio26 : 1;
  72         u32 gpio27 : 1;
  73         u32 gpio28 : 1;
  74         u32 gpio29 : 1;
  75         u32 gpio30 : 1;
  76         u32 gpio31 : 1;
  77 } __packed;
  78
  79 struct soc_cfio {
  80         u32 pad_conf_0;
  81         u32 pad_conf_1;
  82         u32 pad_val;
  83         u32 pad_dft;
  84 } __packed;
  85
  86 struct soc_gpio_map {
  87         /* GPIO core */
  88         struct {
  89                 const struct soc_gpio *mode;
  90                 const struct soc_gpio *direction;
  91                 const struct soc_gpio *level;
  92                 const struct soc_gpio *tpe;
  93                 const struct soc_gpio *tne;
  94                 const struct soc_gpio *ts;
  95                 const struct soc_cfio *cfio_init;
  96                 const u32 cfio_entrynum;
  97         }core;
  98
  99         /* GPIO SUS */
 100         struct {
 101                 const struct soc_gpio *mode;
 102                 const struct soc_gpio *direction;
 103                 const struct soc_gpio *level;
 104                 const struct soc_gpio *tpe;
 105                 const struct soc_gpio *tne;
 106                 const struct soc_gpio *ts;
 107                 const struct soc_gpio *we;
 108                 const struct soc_cfio *cfio_init;
 109                 const u32 cfio_entrynum;
 110         }sus;
 111
 112
 113 };
 114
 115 /* Configure GPIOs with mainboard provided settings */
 116 void setup_soc_gpios(const struct soc_gpio_map *gpio);
 117
 118 /* Get GPIO pin value */
 119 int get_gpio(int gpio_num);
 120 /*
 121  * Get a number comprised of multiple GPIO values. gpio_num_array points to
 122  * the array of GPIO pin numbers to scan, terminated by -1.
 123  */
 124 unsigned get_gpios(const int *gpio_num_array);
 125
 126 #endif