src/soc/qualcomm/ipq806x/lcc.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above
  10  *       copyright notice, this list of conditions and the following
  11  *       disclaimer in the documentation and/or other materials provided
  12  *       with the distribution.
  13  *     * Neither the name of The Linux Foundation nor the names of its
  14  *       contributors may be used to endorse or promote products derived
  15  *       from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  18  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  24  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  26  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  27  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #include <stdlib.h>
  31 #include <stdint.h>
  32 #include <compiler.h>
  33 #include <delay.h>
  34 #include <console/console.h>
  35 #include <soc/clock.h>
  36 #include <soc/lcc-reg.h>
  37 #include <arch/io.h>
  38
  39 typedef struct {
  40         void *gcc_apcs_regs;
  41         void *lcc_pll0_regs;
  42         void *lcc_ahbix_regs;
  43         void *lcc_mi2s_regs;
  44         void *lcc_pll_regs;
  45 } Ipq806xLccClocks;
  46
  47 typedef struct __packed {
  48         uint32_t apcs;
  49 } Ipq806xLccGccRegs;
  50
  51 typedef struct __packed {
  52         uint32_t mode;
  53         uint32_t l_val;
  54         uint32_t m_val;
  55         uint32_t n_val;
  56         uint32_t UNUSED;
  57         uint32_t config;
  58         uint32_t status;
  59 } Ipq806xLccPll0Regs;
  60
  61 typedef struct __packed {
  62         uint32_t ns;
  63         uint32_t md;
  64         uint32_t UNUSED;
  65         uint32_t status;
  66 } Ipq806xLccAhbixRegs;
  67
  68 typedef struct __packed {
  69         uint32_t ns;
  70         uint32_t md;
  71         uint32_t status;
  72 } Ipq806xLccMi2sRegs;
  73
  74 typedef struct __packed {
  75         uint32_t pri;
  76         uint32_t sec;
  77 } Ipq806xLccPllRegs;
  78
  79 struct lcc_freq_tbl {
  80         unsigned freq;
  81         unsigned pd;
  82         unsigned m;
  83         unsigned n;
  84         unsigned d;
  85 };
  86
  87 static const struct lcc_freq_tbl lcc_mi2s_freq_tbl[] = {
  88         {  1024000, 4,  1,  96, 8 },
  89         {  1411200, 4,  2, 139, 8 },
  90         {  1536000, 4,  1,  64, 8 },
  91         {  2048000, 4,  1,  48, 8 },
  92         {  2116800, 4,  2,  93, 8 },
  93         {  2304000, 4,  2,  85, 8 },
  94         {  2822400, 4,  6, 209, 8 },
  95         {  3072000, 4,  1,  32, 8 },
  96         {  3175200, 4,  1,  31, 8 },
  97         {  4096000, 4,  1,  24, 8 },
  98         {  4233600, 4,  9, 209, 8 },
  99         {  4608000, 4,  3,  64, 8 },
 100         {  5644800, 4, 12, 209, 8 },
 101         {  6144000, 4,  1,  16, 8 },
 102         {  6350400, 4,  2,  31, 8 },
 103         {  8192000, 4,  1,  12, 8 },
 104         {  8467200, 4, 18, 209, 8 },
 105         {  9216000, 4,  3,  32, 8 },
 106         { 11289600, 4, 24, 209, 8 },
 107         { 12288000, 4,  1,   8, 8 },
 108         { 12700800, 4, 27, 209, 8 },
 109         { 13824000, 4,  9,  64, 8 },
 110         { 16384000, 4,  1,   6, 8 },
 111         { 16934400, 4, 41, 238, 8 },
 112         { 18432000, 4,  3,  16, 8 },
 113         { 22579200, 2, 24, 209, 8 },
 114         { 24576000, 4,  1,   4, 8 },
 115         { 27648000, 4,  9,  32, 8 },
 116         { 33868800, 4, 41, 119, 8 },
 117         { 36864000, 4,  3,   8, 8 },
 118         { 45158400, 1, 24, 209, 8 },
 119         { 49152000, 4,  1,   2, 8 },
 120         { 50803200, 1, 27, 209, 8 },
 121         { }
 122 };
 123
 124 static int lcc_init_enable_pll0(Ipq806xLccClocks *bus)
 125 {
 126         Ipq806xLccGccRegs *gcc_regs = bus->gcc_apcs_regs;
 127         Ipq806xLccPll0Regs *pll0_regs = bus->lcc_pll0_regs;
 128         Ipq806xLccPllRegs *pll_regs = bus->lcc_pll_regs;
 129         uint32_t regval;
 130
 131         regval = 0;
 132         regval = 15 << LCC_PLL0_L_SHIFT & LCC_PLL0_L_MASK;
 133         write32(&pll0_regs->l_val, regval);
 134
 135         regval = 0;
 136         regval = 145 << LCC_PLL0_M_SHIFT & LCC_PLL0_M_MASK;
 137         write32(&pll0_regs->m_val, regval);
 138
 139         regval = 0;
 140         regval = 199 << LCC_PLL0_N_SHIFT & LCC_PLL0_N_MASK;
 141         write32(&pll0_regs->n_val, regval);
 142
 143         regval = 0;
 144         regval |= LCC_PLL0_CFG_LV_MAIN_ENABLE;
 145         regval |= LCC_PLL0_CFG_FRAC_ENABLE;
 146         write32(&pll0_regs->config, regval);
 147
 148         regval = 0;
 149         regval |= LCC_PLL_PCLK_SRC_PRI;
 150         write32(&pll_regs->pri, regval);
 151
 152         regval = 0;
 153         regval |= 1 << LCC_PLL0_MODE_BIAS_CNT_SHIFT &
 154                         LCC_PLL0_MODE_BIAS_CNT_MASK;
 155         regval |= 8 << LCC_PLL0_MODE_LOCK_CNT_SHIFT &
 156                         LCC_PLL0_MODE_LOCK_CNT_MASK;
 157         write32(&pll0_regs->mode, regval);
 158
 159         regval = read32(&gcc_regs->apcs);
 160         regval |= GCC_PLL_APCS_PLL4_ENABLE;
 161         write32(&gcc_regs->apcs, regval);
 162
 163         regval = read32(&pll0_regs->mode);
 164         regval |= LCC_PLL0_MODE_FSM_VOTE_ENABLE;
 165         write32(&pll0_regs->mode, regval);
 166
 167         mdelay(1);
 168
 169         regval = read32(&pll0_regs->status);
 170         if (regval & LCC_PLL0_STAT_ACTIVE_MASK)
 171                 return 0;
 172
 173         printk(BIOS_ERR, "%s: error enabling PLL4 clock\n", __func__);
 174         return 1;
 175 }
 176
 177 static int lcc_init_enable_ahbix(Ipq806xLccClocks *bus)
 178 {
 179         Ipq806xLccAhbixRegs *ahbix_regs = bus->lcc_ahbix_regs;
 180         uint32_t regval;
 181
 182         regval = 0;
 183         regval |= 1 << LCC_AHBIX_MD_M_VAL_SHIFT & LCC_AHBIX_MD_M_VAL_MASK;
 184         regval |= 252 << LCC_AHBIX_MD_NOT_2D_VAL_SHIFT &
 185                         LCC_AHBIX_MD_NOT_2D_VAL_MASK;
 186         write32(&ahbix_regs->md, regval);
 187
 188         regval = 0;
 189         regval |= 253 << LCC_AHBIX_NS_N_VAL_SHIFT & LCC_AHBIX_NS_N_VAL_MASK;
 190         regval |= LCC_AHBIX_NS_CRC_ENABLE;
 191         regval |= LCC_AHBIX_NS_GFM_SEL_MNC;
 192         regval |= LCC_AHBIX_NS_MNC_CLK_ENABLE;
 193         regval |= LCC_AHBIX_NS_MNC_ENABLE;
 194         regval |= LCC_AHBIX_NS_MNC_MODE_DUAL;
 195         regval |= LCC_AHBIX_NS_PREDIV_BYPASS;
 196         regval |= LCC_AHBIX_NS_MN_SRC_LPA;
 197         write32(&ahbix_regs->ns, regval);
 198
 199         mdelay(1);
 200
 201         regval = read32(&ahbix_regs->status);
 202         if (regval & LCC_AHBIX_STAT_AIF_CLK_MASK)
 203                 return 0;
 204
 205         printk(BIOS_ERR, "%s: error enabling AHBIX clock\n", __func__);
 206         return 1;
 207 }
 208
 209 static int lcc_init_mi2s(Ipq806xLccClocks *bus, unsigned freq)
 210 {
 211         Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs;
 212         uint32_t regval;
 213         uint8_t pd, m, n, d;
 214         unsigned i;
 215
 216         i = 0;
 217         while (lcc_mi2s_freq_tbl[i].freq != 0) {
 218                 if (lcc_mi2s_freq_tbl[i].freq == freq)
 219                         break;
 220                 ++i;
 221         }
 222         if (lcc_mi2s_freq_tbl[i].freq == 0) {
 223                 printk(BIOS_ERR, "%s: invalid frequency given: %u\n",
 224                        __func__, freq);
 225                 return 1;
 226         }
 227
 228         switch (lcc_mi2s_freq_tbl[i].pd) {
 229         case 1:
 230                 pd = LCC_MI2S_NS_PREDIV_BYPASS;
 231                 break;
 232         case 2:
 233                 pd = LCC_MI2S_NS_PREDIV_DIV2;
 234                 break;
 235         case 4:
 236                 pd = LCC_MI2S_NS_PREDIV_DIV4;
 237                 break;
 238         default:
 239                 printk(BIOS_ERR, "%s: invalid prediv found: %u\n", __func__,
 240                                 lcc_mi2s_freq_tbl[i].pd);
 241                 return 1;
 242         }
 243
 244         m = lcc_mi2s_freq_tbl[i].m;
 245         n = ~(lcc_mi2s_freq_tbl[i].n - m);
 246         d = ~(lcc_mi2s_freq_tbl[i].d * 2);
 247
 248         regval = 0;
 249         regval |= m << LCC_MI2S_MD_M_VAL_SHIFT & LCC_MI2S_MD_M_VAL_MASK;
 250         regval |= d << LCC_MI2S_MD_NOT_2D_VAL_SHIFT &
 251                         LCC_MI2S_MD_NOT_2D_VAL_MASK;
 252         write32(&mi2s_regs->md, regval);
 253
 254         regval = 0;
 255         regval |= n << LCC_MI2S_NS_N_VAL_SHIFT & LCC_MI2S_NS_N_VAL_MASK;
 256         regval |= LCC_MI2S_NS_BIT_DIV_DIV4;
 257         regval |= LCC_MI2S_NS_MNC_CLK_ENABLE;
 258         regval |= LCC_MI2S_NS_MNC_ENABLE;
 259         regval |= LCC_MI2S_NS_MNC_MODE_DUAL;
 260         regval |= pd;
 261         regval |= LCC_MI2S_NS_MN_SRC_LPA;
 262         write32(&mi2s_regs->ns, regval);
 263
 264         return 0;
 265 }
 266
 267 static int lcc_enable_mi2s(Ipq806xLccClocks *bus)
 268 {
 269         Ipq806xLccMi2sRegs *mi2s_regs = bus->lcc_mi2s_regs;
 270         uint32_t regval;
 271
 272         regval = read32(&mi2s_regs->ns);
 273         regval |= LCC_MI2S_NS_OSR_CXC_ENABLE;
 274         regval |= LCC_MI2S_NS_BIT_CXC_ENABLE;
 275         write32(&mi2s_regs->ns, regval);
 276
 277         udelay(10);
 278
 279         regval = read32(&mi2s_regs->status);
 280         if (regval & LCC_MI2S_STAT_OSR_CLK_MASK)
 281                 if (regval & LCC_MI2S_STAT_BIT_CLK_MASK)
 282                         return 0;
 283
 284         printk(BIOS_ERR, "%s: error enabling MI2S clocks: %u\n",
 285                __func__, regval);
 286         return 1;
 287 }
 288
 289 int audio_clock_config(unsigned frequency)
 290 {
 291         Ipq806xLccClocks *bus = malloc(sizeof(*bus));
 292
 293         if (!bus) {
 294                 printk(BIOS_ERR, "%s: failed to allocate bus structure\n",
 295                        __func__);
 296                 return 1;
 297         }
 298
 299         bus->gcc_apcs_regs = (void *)(MSM_GCC_BASE + GCC_PLL_APCS_REG);
 300         bus->lcc_pll0_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL0_MODE_REG);
 301         bus->lcc_ahbix_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_AHBIX_NS_REG);
 302         bus->lcc_mi2s_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_MI2S_NS_REG);
 303         bus->lcc_pll_regs = (void *)(MSM_LPASS_LCC_BASE + LCC_PLL_PCLK_REG);
 304
 305
 306         if (lcc_init_enable_pll0(bus))
 307                 return 1;
 308         if (lcc_init_enable_ahbix(bus))
 309                 return 1;
 310         if (lcc_init_mi2s(bus, frequency))
 311                 return 1;
 312
 313         if (lcc_enable_mi2s(bus))
 314                 return 1;
 315
 316         return 0;
 317 }