src/soc/intel/sch/nvs.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef SOC_INTEL_SCH_NVS_H
  17 #define SOC_INTEL_SCH_NVS_H
  18
  19 #include <compiler.h>
  20 typedef struct {
  21         /* Miscellaneous */
  22         u16     osys; /* 0x00 - Operating System */
  23         u8      smif; /* 0x02 - SMI function call ("TRAP") */
  24         u8      prm0; /* 0x03 - SMI function call parameter */
  25         u8      prm1; /* 0x04 - SMI function call parameter */
  26         u8      scif; /* 0x05 - SCI function call (via _L00) */
  27         u8      prm2; /* 0x06 - SCI function call parameter */
  28         u8      prm3; /* 0x07 - SCI function call parameter */
  29         u8      lckf; /* 0x08 - Global Lock function for EC */
  30         u8      prm4; /* 0x09 - Lock function parameter */
  31         u8      prm5; /* 0x0a - Lock function parameter */
  32         u32     p80d; /* 0x0b - Debug port (IO 0x80) value */
  33         u8      lids; /* 0x0f - LID state (open = 1) */
  34         u8      pwrs; /* 0x10 - Power state (AC = 1) */
  35         u8      dbgs; /* 0x11 - Debug state */
  36         u8      linx; /* 0x12 - Linux OS */
  37         u8      dckn; /* 0x13 - PCIe docking state */
  38         /* Thermal policy */
  39         u8      actt; /* 0x14 - active trip point */
  40         u8      psvt; /* 0x15 - passive trip point */
  41         u8      tc1v; /* 0x16 - passive trip point TC1 */
  42         u8      tc2v; /* 0x17 - passive trip point TC2 */
  43         u8      tspv; /* 0x18 - passive trip point TSP */
  44         u8      crtt; /* 0x19 - critical trip point */
  45         u8      dtse; /* 0x1a - Digital Thermal Sensor enable */
  46         u8      dts1; /* 0x1b - DT sensor 1 */
  47         u8      dts2; /* 0x1c - DT sensor 2 */
  48         u8      rsvd2;
  49         /* Battery Support */
  50         u8      bnum; /* 0x1e - number of batteries */
  51         u8      b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
  52         u8      b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
  53         u8      rsvd3[3];
  54         /* Processor Identification */
  55         u8      apic; /* 0x28 - APIC enabled */
  56         u8      mpen; /* 0x29 - MP capable/enabled */
  57         u8      pcp0; /* 0x2a - PDC CPU/CORE 0 */
  58         u8      pcp1; /* 0x2b - PDC CPU/CORE 1 */
  59         u8      ppcm; /* 0x2c - Max. PPC state */
  60         u8      rsvd4[5];
  61         /* Super I/O & CMOS config */
  62         u8      natp; /* 0x32 - SIO type */
  63         u8      cmap; /* 0x33 - */
  64         u8      cmbp; /* 0x34 - */
  65         u8      lptp; /* 0x35 - LPT port */
  66         u8      fdcp; /* 0x36 - Floppy Disk Controller */
  67         u8      rfdv; /* 0x37 - */
  68         u8      hotk; /* 0x38 - Hot Key */
  69         u8      rtcf;
  70         u8      util;
  71         u8      acin;
  72         /* Integrated Graphics Device */
  73         u8      igds; /* 0x3c - IGD state */
  74         u8      tlst; /* 0x3d - Display Toggle List Pointer */
  75         u8      cadl; /* 0x3e - currently attached devices */
  76         u8      padl; /* 0x3f - previously attached devices */
  77         u16     cste; /* 0x40 - current display state */
  78         u16     nste; /* 0x42 - next display state */
  79         u16     sste; /* 0x44 - set display state */
  80         u8      ndid; /* 0x46 - number of device ids */
  81         u32     did[5]; /* 0x47 - 5b device id 1..5 */
  82         u8      rsvd5[0x9];
  83         /* Backlight Control */
  84         u8      blcs; /* 0x64 - Backlight Control possible */
  85         u8      brtl;
  86         u8      odds;
  87         u8      rsvd6[0x7];
  88         /* Ambient Light Sensors*/
  89         u8      alse; /* 0x6e - ALS enable */
  90         u8      alaf;
  91         u8      llow;
  92         u8      lhih;
  93         u8      rsvd7[0x6];
  94         /* EMA */
  95         u8      emae; /* 0x78 - EMA enable */
  96         u16     emap;
  97         u16     emal;
  98         u8      rsvd8[0x5];
  99         /* MEF */
 100         u8      mefe; /* 0x82 - MEF enable */
 101         u8      rsvd9[0x9];
 102         /* TPM support */
 103         u8      tpmp; /* 0x8c - TPM */
 104         u8      tpme;
 105         u8      rsvd10[8];
 106         /* SATA */
 107         u8      gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
 108         u8      gtf1[7];
 109         u8      gtf2[7];
 110         u8      idem;
 111         u8      idet;
 112         u8      rsvd11[7];
 113         /* IGD OpRegion (not implemented yet) */
 114         u32     aslb; /* 0xb4 - IGD OpRegion Base Address */
 115         u8      ibtt;
 116         u8      ipat;
 117         u8      itvf;
 118         u8      itvm;
 119         u8      ipsc;
 120         u8      iblc;
 121         u8      ibia;
 122         u8      issc;
 123         u8      i409;
 124         u8      i509;
 125         u8      i609;
 126         u8      i709;
 127         u8      idmm;
 128         u8      idms;
 129         u8      if1e;
 130         u8      hvco;
 131         u32     nxd[8];
 132         u8      rsvd12[8];
 133         /* Mainboard specific */
 134         u8      dock; /* 0xf0 - Docking Status */
 135         u8      bten;
 136         u8      rsvd13[14];
 137 } __packed global_nvs_t;
 138
 139 void acpi_create_gnvs(global_nvs_t * gnvs);
 140
 141 #endif /* SOC_INTEL_SCH_NVS_H */