src/soc/intel/fsp_baytrail/spi.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
   4  * Copyright (C) 2016 Siemens AG
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but without any warranty; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /* This file is derived from the flashrom project. */
  18 #include <stdint.h>
  19 #include <compiler.h>
  20 #include <stdlib.h>
  21 #include <string.h>
  22 #include <commonlib/helpers.h>
  23 #include <delay.h>
  24 #include <arch/io.h>
  25 #include <console/console.h>
  26 #include <device/pci_ids.h>
  27 #include <spi_flash.h>
  28 #include <spi-generic.h>
  29
  30 #include <soc/lpc.h>
  31 #include <soc/pci_devs.h>
  32
  33 #ifdef __SMM__
  34 #define pci_read_config_byte(dev, reg, targ)\
  35         *(targ) = pci_read_config8(dev, reg)
  36 #define pci_read_config_word(dev, reg, targ)\
  37         *(targ) = pci_read_config16(dev, reg)
  38 #define pci_read_config_dword(dev, reg, targ)\
  39         *(targ) = pci_read_config32(dev, reg)
  40 #define pci_write_config_byte(dev, reg, val)\
  41         pci_write_config8(dev, reg, val)
  42 #define pci_write_config_word(dev, reg, val)\
  43         pci_write_config16(dev, reg, val)
  44 #define pci_write_config_dword(dev, reg, val)\
  45         pci_write_config32(dev, reg, val)
  46 #else /* !__SMM__ */
  47 #include <device/device.h>
  48 #include <device/pci.h>
  49 #define pci_read_config_byte(dev, reg, targ)\
  50         *(targ) = pci_read_config8(dev, reg)
  51 #define pci_read_config_word(dev, reg, targ)\
  52         *(targ) = pci_read_config16(dev, reg)
  53 #define pci_read_config_dword(dev, reg, targ)\
  54         *(targ) = pci_read_config32(dev, reg)
  55 #define pci_write_config_byte(dev, reg, val)\
  56         pci_write_config8(dev, reg, val)
  57 #define pci_write_config_word(dev, reg, val)\
  58         pci_write_config16(dev, reg, val)
  59 #define pci_write_config_dword(dev, reg, val)\
  60         pci_write_config32(dev, reg, val)
  61 #endif /* !__SMM__ */
  62
  63 typedef struct spi_slave ich_spi_slave;
  64
  65 static int ichspi_lock = 0;
  66
  67 typedef struct ich9_spi_regs {
  68         uint32_t bfpr;
  69         uint16_t hsfs;
  70         uint16_t hsfc;
  71         uint32_t faddr;
  72         uint32_t _reserved0;
  73         uint32_t fdata[16];
  74         uint32_t frap;
  75         uint32_t freg[5];
  76         uint32_t _reserved1[3];
  77         uint32_t pr[5];
  78         uint32_t _reserved2[2];
  79         uint8_t ssfs;
  80         uint8_t ssfc[3];
  81         uint16_t preop;
  82         uint16_t optype;
  83         uint8_t opmenu[8];
  84         uint8_t _reserved3[16];
  85         uint32_t fdoc;
  86         uint32_t fdod;
  87         uint8_t _reserved4[8];
  88         uint32_t afc;
  89         uint32_t lvscc;
  90         uint32_t uvscc;
  91         uint8_t _reserved5[4];
  92         uint32_t fpb;
  93         uint8_t _reserved6[28];
  94         uint32_t srdl;
  95         uint32_t srdc;
  96         uint32_t srd;
  97 } __packed ich9_spi_regs;
  98
  99 typedef struct ich_spi_controller {
 100         int locked;
 101
 102         uint8_t *opmenu;
 103         int menubytes;
 104         uint16_t *preop;
 105         uint16_t *optype;
 106         uint32_t *addr;
 107         uint8_t *data;
 108         unsigned databytes;
 109         uint8_t *status;
 110         uint16_t *control;
 111 } ich_spi_controller;
 112
 113 static ich_spi_controller cntlr;
 114
 115 enum {
 116         SPIS_SCIP =             0x0001,
 117         SPIS_GRANT =            0x0002,
 118         SPIS_CDS =              0x0004,
 119         SPIS_FCERR =            0x0008,
 120         SSFS_AEL =              0x0010,
 121         SPIS_LOCK =             0x8000,
 122         SPIS_RESERVED_MASK =    0x7ff0,
 123         SSFS_RESERVED_MASK =    0x7fe2
 124 };
 125
 126 enum {
 127         SPIC_SCGO =             0x000002,
 128         SPIC_ACS =              0x000004,
 129         SPIC_SPOP =             0x000008,
 130         SPIC_DBC =              0x003f00,
 131         SPIC_DS =               0x004000,
 132         SPIC_SME =              0x008000,
 133         SSFC_SCF_MASK =         0x070000,
 134         SSFC_RESERVED =         0xf80000
 135 };
 136
 137 enum {
 138         HSFS_FDONE =            0x0001,
 139         HSFS_FCERR =            0x0002,
 140         HSFS_AEL =              0x0004,
 141         HSFS_BERASE_MASK =      0x0018,
 142         HSFS_BERASE_SHIFT =     3,
 143         HSFS_SCIP =             0x0020,
 144         HSFS_FDOPSS =           0x2000,
 145         HSFS_FDV =              0x4000,
 146         HSFS_FLOCKDN =          0x8000
 147 };
 148
 149 enum {
 150         HSFC_FGO =              0x0001,
 151         HSFC_FCYCLE_MASK =      0x0006,
 152         HSFC_FCYCLE_SHIFT =     1,
 153         HSFC_FDBC_MASK =        0x3f00,
 154         HSFC_FDBC_SHIFT =       8,
 155         HSFC_FSMIE =            0x8000
 156 };
 157
 158 enum {
 159         SPI_OPCODE_TYPE_READ_NO_ADDRESS =       0,
 160         SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =      1,
 161         SPI_OPCODE_TYPE_READ_WITH_ADDRESS =     2,
 162         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =    3
 163 };
 164
 165 #define SPI_OFFSET_MASK         0x3ff
 166
 167 static uint8_t readb_(const void *addr)
 168 {
 169         uint8_t v = read8(addr);
 170         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 171                 printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n",
 172                                 v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 173         }
 174         return v;
 175 }
 176
 177 static uint16_t readw_(const void *addr)
 178 {
 179         uint16_t v = read16(addr);
 180         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 181                 printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n",
 182                                 v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 183         }
 184         return v;
 185 }
 186
 187 static uint32_t readl_(const void *addr)
 188 {
 189         uint32_t v = read32(addr);
 190         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 191                 printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n",
 192                                 v, (((uint32_t) addr) & SPI_OFFSET_MASK));
 193         }
 194         return v;
 195 }
 196
 197 static void writeb_(uint8_t b, void *addr)
 198 {
 199         write8(addr, b);
 200         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 201                 printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n",
 202                                 b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 203         }
 204 }
 205
 206 static void writew_(uint16_t b, void *addr)
 207 {
 208         write16(addr, b);
 209         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 210                 printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n",
 211                                 b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 212         }
 213 }
 214
 215 static void writel_(uint32_t b, void *addr)
 216 {
 217         write32(addr, b);
 218         if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) {
 219                 printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n",
 220                                 b, (((uint32_t) addr) & SPI_OFFSET_MASK));
 221         }
 222 }
 223
 224 static void write_reg(const void *value, void *dest, uint32_t size)
 225 {
 226         const uint8_t *bvalue = value;
 227         uint8_t *bdest = dest;
 228
 229         while (size >= 4) {
 230                 writel_(*(const uint32_t *)bvalue, bdest);
 231                 bdest += 4; bvalue += 4; size -= 4;
 232         }
 233         while (size) {
 234                 writeb_(*bvalue, bdest);
 235                 bdest++; bvalue++; size--;
 236         }
 237 }
 238
 239 static void read_reg(const void *src, void *value, uint32_t size)
 240 {
 241         const uint8_t *bsrc = src;
 242         uint8_t *bvalue = value;
 243
 244         while (size >= 4) {
 245                 *(uint32_t *)bvalue = readl_(bsrc);
 246                 bsrc += 4; bvalue += 4; size -= 4;
 247         }
 248         while (size) {
 249                 *bvalue = readb_(bsrc);
 250                 bsrc++; bvalue++; size--;
 251         }
 252 }
 253
 254 static ich9_spi_regs *spi_regs(void)
 255 {
 256         uint32_t sbase;
 257
 258 #ifdef __SMM__
 259         pci_devfn_t dev;
 260         dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
 261 #else
 262         device_t dev;
 263         dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 264 #endif
 265         pci_read_config_dword(dev, SBASE, &sbase);
 266         sbase &= ~0x1ff;
 267
 268         return (void *)sbase;
 269 }
 270
 271 void spi_init(void)
 272 {
 273         ich9_spi_regs *ich9_spi = spi_regs();
 274
 275         ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
 276         cntlr.opmenu = ich9_spi->opmenu;
 277         cntlr.menubytes = sizeof(ich9_spi->opmenu);
 278         cntlr.optype = &ich9_spi->optype;
 279         cntlr.addr = &ich9_spi->faddr;
 280         cntlr.data = (uint8_t *)ich9_spi->fdata;
 281         cntlr.databytes = sizeof(ich9_spi->fdata);
 282         cntlr.status = &ich9_spi->ssfs;
 283         cntlr.control = (uint16_t *)ich9_spi->ssfc;
 284         cntlr.preop = &ich9_spi->preop;
 285 }
 286
 287 typedef struct spi_transaction {
 288         const uint8_t *out;
 289         uint32_t bytesout;
 290         uint8_t *in;
 291         uint32_t bytesin;
 292         uint8_t type;
 293         uint8_t opcode;
 294         uint32_t offset;
 295 } spi_transaction;
 296
 297 static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
 298 {
 299         trans->out += bytes;
 300         trans->bytesout -= bytes;
 301 }
 302
 303 static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
 304 {
 305         trans->in += bytes;
 306         trans->bytesin -= bytes;
 307 }
 308
 309 static void spi_setup_type(spi_transaction *trans)
 310 {
 311         trans->type = 0xFF;
 312
 313         /* Try to guess spi type from read/write sizes. */
 314         if (trans->bytesin == 0) {
 315                 if (trans->bytesout > 4)
 316                         /*
 317                          * If bytesin = 0 and bytesout > 4, we presume this is
 318                          * a write data operation, which is accompanied by an
 319                          * address.
 320                          */
 321                         trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
 322                 else
 323                         trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
 324                 return;
 325         }
 326
 327         if (trans->bytesout == 1) { /* and bytesin is > 0 */
 328                 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
 329                 return;
 330         }
 331
 332         if (trans->bytesout == 4) { /* and bytesin is > 0 */
 333                 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
 334         }
 335
 336         /* Fast read command is called with 5 bytes instead of 4 */
 337         if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
 338                 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
 339                 --trans->bytesout;
 340         }
 341 }
 342
 343 static int spi_setup_opcode(spi_transaction *trans)
 344 {
 345         uint16_t optypes;
 346         uint8_t opmenu[cntlr.menubytes];
 347
 348         trans->opcode = trans->out[0];
 349         spi_use_out(trans, 1);
 350         if (!ichspi_lock) {
 351                 /* The lock is off, so just use index 0. */
 352                 writeb_(trans->opcode, cntlr.opmenu);
 353                 optypes = readw_(cntlr.optype);
 354                 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
 355                 writew_(optypes, cntlr.optype);
 356                 return 0;
 357         } else {
 358                 /* The lock is on. See if what we need is on the menu. */
 359                 uint8_t optype;
 360                 uint16_t opcode_index;
 361
 362                 /* Write Enable is handled as atomic prefix */
 363                 if (trans->opcode == SPI_OPCODE_WREN)
 364                         return 0;
 365
 366                 read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
 367                 for (opcode_index = 0; opcode_index < cntlr.menubytes;
 368                                 opcode_index++) {
 369                         if (opmenu[opcode_index] == trans->opcode)
 370                                 break;
 371                 }
 372
 373                 if (opcode_index == cntlr.menubytes) {
 374                         printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
 375                                 trans->opcode);
 376                         return -1;
 377                 }
 378
 379                 optypes = readw_(cntlr.optype);
 380                 optype = (optypes >> (opcode_index * 2)) & 0x3;
 381                 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
 382                         optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
 383                         trans->bytesout >= 3) {
 384                         /* We guessed wrong earlier. Fix it up. */
 385                         trans->type = optype;
 386                 }
 387                 if (optype != trans->type) {
 388                         printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
 389                                 optype);
 390                         return -1;
 391                 }
 392                 return opcode_index;
 393         }
 394 }
 395
 396 static int spi_setup_offset(spi_transaction *trans)
 397 {
 398         /* Separate the SPI address and data. */
 399         switch (trans->type) {
 400         case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
 401         case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
 402                 return 0;
 403         case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
 404         case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
 405                 trans->offset = ((uint32_t)trans->out[0] << 16) |
 406                                 ((uint32_t)trans->out[1] << 8) |
 407                                 ((uint32_t)trans->out[2] << 0);
 408                 spi_use_out(trans, 3);
 409                 return 1;
 410         default:
 411                 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
 412                 return -1;
 413         }
 414 }
 415
 416 /*
 417  * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set
 418  * below is True) or 0. In case the wait was for the bit(s) to set - write
 419  * those bits back, which would cause resetting them.
 420  *
 421  * Return the last read status value on success or -1 on failure.
 422  */
 423 static int ich_status_poll(uint16_t bitmask, int wait_til_set)
 424 {
 425         int timeout = 40000; /* This will result in 400 ms */
 426         uint16_t status = 0;
 427
 428         while (timeout--) {
 429                 status = readw_(cntlr.status);
 430                 if (wait_til_set ^ ((status & bitmask) == 0)) {
 431                         if (wait_til_set)
 432                                 writew_((status & bitmask), cntlr.status);
 433                         return status;
 434                 }
 435                 udelay(10);
 436         }
 437
 438         printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n",
 439                 status, bitmask);
 440         return -1;
 441 }
 442
 443 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 444                     size_t bytesout, void *din, size_t bytesin)
 445 {
 446         uint16_t control;
 447         int16_t opcode_index;
 448         int with_address;
 449         int status;
 450
 451         spi_transaction trans = {
 452                 dout, bytesout,
 453                 din, bytesin,
 454                 0xff, 0xff, 0
 455         };
 456
 457         /* There has to always at least be an opcode. */
 458         if (!bytesout || !dout) {
 459                 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
 460                 return -1;
 461         }
 462         /* Make sure if we read something we have a place to put it. */
 463         if (bytesin != 0 && !din) {
 464                 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
 465                 return -1;
 466         }
 467
 468         if (ich_status_poll(SPIS_SCIP, 0) == -1)
 469                 return -1;
 470
 471         writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
 472
 473         spi_setup_type(&trans);
 474         if ((opcode_index = spi_setup_opcode(&trans)) < 0)
 475                 return -1;
 476         if ((with_address = spi_setup_offset(&trans)) < 0)
 477                 return -1;
 478
 479         if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) {
 480                 /*
 481                  * Treat Write Enable as Atomic Pre-Op if possible
 482                  * in order to prevent the Management Engine from
 483                  * issuing a transaction between WREN and DATA.
 484                  */
 485                 writew_(trans.opcode, cntlr.preop);
 486                 return 0;
 487         }
 488
 489         /* Preset control fields */
 490         control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
 491
 492         /* Issue atomic preop cycle if needed */
 493         if (readw_(cntlr.preop))
 494                 control |= SPIC_ACS;
 495
 496         if (!trans.bytesout && !trans.bytesin) {
 497                 /* SPI addresses are 24 bit only */
 498                 if (with_address)
 499                         writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 500
 501                 /*
 502                  * This is a 'no data' command (like Write Enable), its
 503                  * bytesout size was 1, decremented to zero while executing
 504                  * spi_setup_opcode() above. Tell the chip to send the
 505                  * command.
 506                  */
 507                 writew_(control, cntlr.control);
 508
 509                 /* wait for the result */
 510                 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
 511                 if (status == -1)
 512                         return -1;
 513
 514                 if (status & SPIS_FCERR) {
 515                         printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
 516                         return -1;
 517                 }
 518
 519                 goto spi_xfer_exit;
 520         }
 521
 522         /*
 523          * Check if this is a write command attempting to transfer more bytes
 524          * than the controller can handle. Iterations for writes are not
 525          * supported here because each SPI write command needs to be preceded
 526          * and followed by other SPI commands, and this sequence is controlled
 527          * by the SPI chip driver.
 528          */
 529         if (trans.bytesout > cntlr.databytes) {
 530                 printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
 531                      " spi_crop_chunk()?\n");
 532                 return -1;
 533         }
 534
 535         /*
 536          * Read or write up to databytes bytes at a time until everything has
 537          * been sent.
 538          */
 539         while (trans.bytesout || trans.bytesin) {
 540                 uint32_t data_length;
 541
 542                 /* SPI addresses are 24 bit only */
 543                 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 544
 545                 if (trans.bytesout)
 546                         data_length = min(trans.bytesout, cntlr.databytes);
 547                 else
 548                         data_length = min(trans.bytesin, cntlr.databytes);
 549
 550                 /* Program data into FDATA0 to N */
 551                 if (trans.bytesout) {
 552                         write_reg(trans.out, cntlr.data, data_length);
 553                         spi_use_out(&trans, data_length);
 554                         if (with_address)
 555                                 trans.offset += data_length;
 556                 }
 557
 558                 /* Add proper control fields' values */
 559                 control &= ~((cntlr.databytes - 1) << 8);
 560                 control |= SPIC_DS;
 561                 control |= (data_length - 1) << 8;
 562
 563                 /* write it */
 564                 writew_(control, cntlr.control);
 565
 566                 /* Wait for Cycle Done Status or Flash Cycle Error. */
 567                 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
 568                 if (status == -1)
 569                         return -1;
 570
 571                 if (status & SPIS_FCERR) {
 572                         printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
 573                         return -1;
 574                 }
 575
 576                 if (trans.bytesin) {
 577                         read_reg(cntlr.data, trans.in, data_length);
 578                         spi_use_in(&trans, data_length);
 579                         if (with_address)
 580                                 trans.offset += data_length;
 581                 }
 582         }
 583
 584 spi_xfer_exit:
 585         /* Clear atomic preop now that xfer is done */
 586         writew_(0, cntlr.preop);
 587
 588         return 0;
 589 }
 590
 591 static const struct spi_ctrlr spi_ctrlr = {
 592         .xfer = spi_ctrlr_xfer,
 593         .xfer_vector = spi_xfer_two_vectors,
 594         .max_xfer_size = member_size(ich9_spi_regs, fdata),
 595 };
 596
 597 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 598         {
 599                 .ctrlr = &spi_ctrlr,
 600                 .bus_start = 0,
 601                 .bus_end = 0,
 602         },
 603 };
 604
 605 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);