src/soc/intel/fsp_baytrail/include/soc/nvs.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2011 Google Inc
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _BAYTRAIL_NVS_H_
  18 #define _BAYTRAIL_NVS_H_
  19
  20 #include <compiler.h>
  21 #include <soc/device_nvs.h>
  22
  23 typedef struct {
  24         /* Miscellaneous */
  25         u16     osys; /* 0x00 - Operating System */
  26         u8      smif; /* 0x02 - SMI function call ("TRAP") */
  27         u8      prm0; /* 0x03 - SMI function call parameter */
  28         u8      prm1; /* 0x04 - SMI function call parameter */
  29         u8      scif; /* 0x05 - SCI function call (via _L00) */
  30         u8      prm2; /* 0x06 - SCI function call parameter */
  31         u8      prm3; /* 0x07 - SCI function call parameter */
  32         u8      lckf; /* 0x08 - Global Lock function for EC */
  33         u8      prm4; /* 0x09 - Lock function parameter */
  34         u8      prm5; /* 0x0a - Lock function parameter */
  35         u32     p80d; /* 0x0b - Debug port (IO 0x80) value */
  36         u8      lids; /* 0x0f - LID state (open = 1) */
  37         u8      pwrs; /* 0x10 - Power state (AC = 1) */
  38         u8      pcnt; /* 0x11 - Processor Count */
  39         u8      tpmp; /* 0x12 - TPM Present and Enabled */
  40         u8      tlvl; /* 0x13 - Throttle Level */
  41         u8      ppcm; /* 0x14 - Maximum P-state usable by OS */
  42         u8      rsvd1[11];
  43
  44         /* Device Config */
  45         u8      s5u0; /* 0x20 - Enable USB0 in S5 */
  46         u8      s5u1; /* 0x21 - Enable USB1 in S5 */
  47         u8      s3u0; /* 0x22 - Enable USB0 in S3 */
  48         u8      s3u1; /* 0x23 - Enable USB1 in S3 */
  49         u8      tact; /* 0x24 - Thermal Active trip point */
  50         u8      tpsv; /* 0x25 - Thermal Passive trip point */
  51         u8      tcrt; /* 0x26 - Thermal Critical trip point */
  52         u8      dpte; /* 0x27 - Enable DPTF */
  53         u8      rsvd2[8];
  54
  55         /* Base Addresses */
  56         u32     obsolete_cmem; /* 0x30 - CBMEM TOC */
  57         u32     tolm; /* 0x34 - Top of Low Memory */
  58         u32     cbmc; /* 0x38 - coreboot memconsole */
  59         u8      rsvd3[196];
  60
  61         /* Pad 0x0100-0x0fff */
  62         u8      rsvd4[3840];
  63
  64         /* Baytrail LPSS (0x1000) */
  65         device_nvs_t dev;
  66 } __packed global_nvs_t;
  67
  68 void acpi_create_gnvs(global_nvs_t *gnvs);
  69 #ifdef __SMM__
  70 /* Used in SMM to find the ACPI GNVS address */
  71 global_nvs_t *smm_get_gnvs(void);
  72 #endif
  73
  74 #endif /* _BAYTRAIL_NVS_H_ */