src/northbridge/intel/i945/raminit.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef RAMINIT_H
  17 #define RAMINIT_H
  18
  19 #include <compiler.h>
  20
  21 #define DIMM_SOCKETS 2
  22
  23 #define DIMM_TCO_BASE 0x30
  24
  25 /* Burst length is always 8 */
  26 #define BURSTLENGTH      8
  27
  28 struct sys_info {
  29         u16 memory_frequency;   /* 400, 533 or 667 */
  30         u16 fsb_frequency;      /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */
  31
  32         u8 trp;                 /* calculated by sdram_detect_smallest_tRP() */
  33         u8 trcd;                /* calculated by sdram_detect_smallest_tRCD() */
  34         u8 tras;                /* calculated by sdram_detect_smallest_tRAS() */
  35         u8 trfc;                /* calculated by sdram_detect_smallest_tRFC() */
  36         u8 twr;                 /* calculated by sdram_detect_smallest_tWR() */
  37
  38         u8 cas;                 /* 3, 4 or 5 */
  39         u8 refresh;             /* 0 = 15.6us, 1 = 7.8us */
  40
  41         u8 dual_channel;        /* 0 or 1 */
  42         u8 interleaved;
  43
  44         u8 mvco4x;              /* 0 (8x) or 1 (4x) */
  45         u8 clkcfg_bit7;
  46         u8 boot_path;
  47 #define BOOT_PATH_NORMAL        0
  48 #define BOOT_PATH_RESET         1
  49 #define BOOT_PATH_RESUME        2
  50
  51         u8 package;             /* 0 = planar, 1 = stacked */
  52 #define SYSINFO_PACKAGE_PLANAR          0x00
  53 #define SYSINFO_PACKAGE_STACKED         0x01
  54         u8 dimm[2 * DIMM_SOCKETS];
  55 #define SYSINFO_DIMM_X16DS              0x00
  56 #define SYSINFO_DIMM_X8DS               0x01
  57 #define SYSINFO_DIMM_X16SS              0x02
  58 #define SYSINFO_DIMM_X8DDS              0x03
  59 #define SYSINFO_DIMM_NOT_POPULATED      0x04
  60
  61         u8 banks[2 * DIMM_SOCKETS];
  62
  63         u8 banksize[2 * 2 * DIMM_SOCKETS];
  64         const u8 *spd_addresses;
  65
  66 } __packed;
  67
  68 void receive_enable_adjust(struct sys_info *sysinfo);
  69 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
  70 int fixup_i945_errata(void);
  71 void udelay(u32 us);
  72
  73 #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
  74 void sdram_dump_mchbar_registers(void);
  75 #endif
  76 #endif                          /* RAMINIT_H */