src/mainboard/siemens/sitemp_g1p1/acpi_tables.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2010 Siemens AG, Inc.
   6  * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <compiler.h>
  19 #include <console/console.h>
  20 #include <string.h>
  21 #include <arch/acpi.h>
  22 #include <arch/ioapic.h>
  23 #include <arch/smp/mpspec.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <cpu/amd/amdk8_sysconf.h>
  27 #include <../../../northbridge/amd/amdk8/acpi.h>
  28 #include <arch/cpu.h>
  29 #include <cpu/amd/powernow.h>
  30 #include <southbridge/amd/rs690/rs690.h>
  31 #include "mainboard.h"
  32 #include <cbmem.h>
  33
  34 #define GLOBAL_VARS_SIZE 0x100
  35
  36 typedef struct {
  37         /* Miscellaneous */
  38         u16 osys;
  39         u16 linx;
  40         u32     pcba;
  41         u8  mpen;
  42         u8 reserv[247];
  43 } __packed global_vars_t;
  44
  45 static void acpi_write_gvars(global_vars_t *gvars)
  46 {
  47         device_t dev;
  48         struct resource *res;
  49
  50         memset((void *)gvars, 0, GLOBAL_VARS_SIZE);
  51
  52         gvars->pcba = EXT_CONF_BASE_ADDRESS;
  53         dev = dev_find_slot(0, PCI_DEVFN(0,0));
  54         res = probe_resource(dev, 0x1C);
  55         if( res )
  56                 gvars->pcba = res->base;
  57
  58         gvars->mpen = 1;
  59 }
  60
  61 unsigned long acpi_fill_madt(unsigned long current)
  62 {
  63         /* create all subtables for processors */
  64         current = acpi_create_madt_lapics(current);
  65
  66         /* Write SB600 IOAPIC, only one */
  67         current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
  68                                            IO_APIC_ADDR, 0);
  69 #if !IS_ENABLED(CONFIG_LINT01_CONVERSION)
  70         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  71                                                 current, 0, 0, 2, 0);
  72
  73         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  74                                                 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
  75 #else
  76                                                 /* 0: mean bus 0--->ISA */
  77         /* 0: PIC 0 */
  78         /* 2: APIC 2 */
  79         /* 5 mean: 0101 --> Edge-triggered, Active high */
  80
  81         /* create all subtables for processors */
  82         current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
  83         /* 1: LINT1 connect to NMI */
  84         set_nbcfg_enable_bits(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x68, 1 << 16, 1 << 16); // Local Interrupt Conversion Enable
  85 #endif
  86         return current;
  87 }
  88
  89 void mainboard_inject_dsdt(device_t device)
  90 {
  91         global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE);
  92
  93         if (gnvs) {
  94                 memset(gnvs, 0, sizeof(*gnvs));
  95                 acpi_write_gvars(gnvs);
  96
  97                 /* Add it to SSDT.  */
  98                 acpigen_write_scope("\\");
  99                 acpigen_write_name_dword("NVSA", (u32) gnvs);
 100                 acpigen_pop_len();
 101         }
 102 }