src/cpu/ti/am335x/clock.h

   1 /*
   2  * Copyright (C) 2013 Google Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __CPU_TI_AM335X_CLOCK_H__
  16 #define __CPU_TI_AM335X_CLOCK_H__
  17
  18 #include <stdint.h>
  19 #include <compiler.h>
  20
  21 enum {
  22         CM_ST_NO_SLEEP = 0x0,
  23         CM_ST_SW_SLEEP = 0x1,
  24         CM_ST_SW_WKUP = 0x2
  25 };
  26
  27 enum {
  28         CM_MODULEMODE_DISABLED = 0x0,
  29         CM_MODULEMODE_ENABLED = 0x2
  30 };
  31
  32 enum {
  33         CM_FCLK_DIS = 0x0 << 18,
  34         CM_FCLK_EN = 0x1 << 18
  35 };
  36
  37 /* Clock module peripheral registers */
  38 struct am335x_cm_per_regs {
  39         uint32_t l4ls_st;               // 0x0
  40         uint32_t l3s_st;                // 0x4
  41         uint8_t _rsv0[4];               // 0x8-0xb
  42         uint32_t l3_st;                 // 0xc
  43         uint8_t _rsv1[4];               // 0x10-0x13
  44         uint32_t cpgmac0;               // 0x14
  45         uint32_t lcdc;                  // 0x18
  46         uint32_t usb0;                  // 0x1c
  47         uint8_t _rsv2[4];               // 0x20-0x23
  48         uint32_t tptc0;                 // 0x24
  49         uint32_t emif;                  // 0x28
  50         uint32_t ocmcram;               // 0x2c
  51         uint32_t gpmc;                  // 0x30
  52         uint32_t mcasp0;                // 0x34
  53         uint32_t uart5;                 // 0x38
  54         uint32_t mmc0;                  // 0x3c
  55         uint32_t elm;                   // 0x40
  56         uint32_t i2c2;                  // 0x44
  57         uint32_t i2c1;                  // 0x48
  58         uint32_t spi0;                  // 0x4c
  59         uint32_t spi1;                  // 0x50
  60         uint8_t _rsv3[0xc];             // 0x54-0x5f
  61         uint32_t l4ls;                  // 0x60
  62         uint8_t _rsv4[4];               // 0x64-0x67
  63         uint32_t mcasp1;                // 0x68
  64         uint32_t uart1;                 // 0x6c
  65         uint32_t uart2;                 // 0x70
  66         uint32_t uart3;                 // 0x74
  67         uint32_t uart4;                 // 0x78
  68         uint32_t timer7;                // 0x7c
  69         uint32_t timer2;                // 0x80
  70         uint32_t timer3;                // 0x84
  71         uint32_t timer4;                // 0x88
  72         uint8_t _rsv5[0x20];            // 0x90-0xab
  73         uint32_t gpio1;                 // 0xac
  74         uint32_t gpio2;                 // 0xb0
  75         uint32_t gpio3;                 // 0xb4
  76         uint8_t _rsv6[4];               // 0xb8-0xbb
  77         uint32_t tpcc;                  // 0xbc
  78         uint32_t dcan0;                 // 0xc0
  79         uint32_t dcan1;                 // 0xc4
  80         uint8_t _rsv7[4];               // 0xc8-0xcb
  81         uint32_t epwmss1;               // 0xcc
  82         uint8_t _rsv8[4];               // 0xd0-0xd3
  83         uint32_t epwmss0;               // 0xd4
  84         uint32_t epwmss2;               // 0xd8
  85         uint32_t l3_instr;              // 0xdc
  86         uint32_t l3;                    // 0xe0
  87         uint32_t ieee5000;              // 0xe4
  88         uint32_t pru_icss;              // 0xe8
  89         uint32_t timer5;                // 0xec
  90         uint32_t timer6;                // 0xf0
  91         uint32_t mmc1;                  // 0xf4
  92         uint32_t mmc2;                  // 0xf8
  93         uint32_t tptc1;                 // 0xfc
  94         uint32_t tptc2;                 // 0x100
  95         uint8_t _rsv9[8];               // 0x104-0x10b
  96         uint32_t spinlock;              // 0x10c
  97         uint32_t mailbox0;              // 0x110
  98         uint8_t _rsv10[8];              // 0x114-0x11b
  99         uint32_t l4hs_st;               // 0x11c
 100         uint32_t l4hs;                  // 0x120
 101         uint8_t _rsv11[8];              // 0x124-0x12b
 102         uint32_t ocpwp_l3_st;           // 0x12c
 103         uint32_t ocpwp;                 // 0x130
 104         uint8_t _rsv12[0xb];            // 0x134-0x13f
 105         uint32_t pru_icss_st;           // 0x140
 106         uint32_t cpsw_st;               // 0x144
 107         uint32_t lcdc_st;               // 0x148
 108         uint32_t clkdiv32k;             // 0x14c
 109         uint32_t clk_24mhz_st;          // 0x150
 110 } __packed;
 111 static struct am335x_cm_per_regs * const am335x_cm_per = (void *)0x44e00000;
 112
 113 /* Clock module wakeup registers */
 114 struct am335x_cm_wkup_regs {
 115         uint32_t wkup_st;               // 0x0
 116         uint32_t wkup_control;          // 0x4
 117         uint32_t wkup_gpio0;            // 0x8
 118         uint32_t wkup_l4wkup;           // 0xc
 119         uint32_t wkup_timer0;           // 0x10
 120         uint32_t wkup_debugss;          // 0x14
 121         uint32_t l3_aon_st;             // 0x18
 122         uint32_t autoidle_dpll_mpu;     // 0x1c
 123         uint32_t idlest_dpll_mpu;       // 0x20
 124         uint32_t ssc_deltamstep_dpll_mpu;       // 0x24
 125         uint32_t ssc_modfreqdiv_dpll_mpu;       // 0x28
 126         uint32_t clksel_dpll_mpu;       // 0x2c
 127         uint32_t autoidle_dpll_ddr;     // 0x30
 128         uint32_t idlest_dpll_ddr;       // 0x34
 129         uint32_t ssc_deltamstep_dpll_ddr;       // 0x38
 130         uint32_t ssc_modfreqdiv_dpll_ddr;       // 0x3c
 131         uint32_t clksel_dpll_ddr;       // 0x40
 132         uint32_t autoidle_dpll_disp;    // 0x44
 133         uint32_t idlest_dpll_disp;      // 0x48
 134         uint32_t ssc_deltamstep_dpll_disp;      // 0x4c
 135         uint32_t ssc_modfreqdiv_dpll_disp;      // 0x50
 136         uint32_t clksel_dpll_disp;      // 0x54
 137         uint32_t autoidle_dpll_core;    // 0x58
 138         uint32_t idlest_dpll_core;      // 0x5c
 139         uint32_t ssc_deltamstep_dpll_core;      // 0x60
 140         uint32_t ssc_modfreqdiv_dpll_core;      // 0x64
 141         uint32_t clksel_dpll_core;      // 0x68
 142         uint32_t autoidle_dpll_per;     // 0x6c
 143         uint32_t idlest_dpll_per;       // 0x70
 144         uint32_t ssc_deltamstep_dpll_per;       // 0x74
 145         uint32_t ssc_modfreqdiv_dpll_per;       // 0x78
 146         uint32_t clkdcoldo_dpll_per;    // 0x7c
 147         uint32_t div_m4_dpll_core;      // 0x80
 148         uint32_t div_m5_dpll_core;      // 0x84
 149         uint32_t clkmode_dpll_mpu;      // 0x88
 150         uint32_t clkmode_dpll_per;      // 0x8c
 151         uint32_t clkmode_dpll_core;     // 0x90
 152         uint32_t clkmode_dpll_ddr;      // 0x94
 153         uint32_t clkmode_dpll_disp;     // 0x98
 154         uint32_t clksel_dpll_periph;    // 0x9c
 155         uint32_t div_m2_dpll_ddr;       // 0xa0
 156         uint32_t div_m2_dpll_disp;      // 0xa4
 157         uint32_t div_m2_dpll_mpu;       // 0xa8
 158         uint32_t div_m2_dpll_per;       // 0xac
 159         uint32_t wkup_wkup_m3;          // 0xb0
 160         uint32_t wkup_uart0;            // 0xb4
 161         uint32_t wkup_i2c0;             // 0xb8
 162         uint32_t wkup_adc_tsc;          // 0xbc
 163         uint32_t wkup_smartreflex0;     // 0xc0
 164         uint32_t wkup_timer1;           // 0xc4
 165         uint32_t wkup_smartreflex1;     // 0xc8
 166         uint32_t l4_wkup_aon_st;        // 0xcc
 167         uint8_t _rsv0[4];               // 0xd0-0xd3
 168         uint32_t wkup_wdt1;             // 0xd4
 169         uint32_t div_m6_dpll_core;      // 0xd8
 170 } __packed;
 171 static struct am335x_cm_wkup_regs * const am335x_cm_wkup = (void *)0x44e00400;
 172
 173 /* Clock module pll registers */
 174 struct am335x_cm_dpll_regs {
 175         uint8_t _rsv0[4];               // 0x0-0x3
 176         uint32_t clksel_timer7_clk;     // 0x4
 177         uint32_t clksel_timer2_clk;     // 0x8
 178         uint32_t clksel_timer3_clk;     // 0xc
 179         uint32_t clksel_timer4_clk;     // 0x10
 180         uint32_t cm_mac_clksel;         // 0x14
 181         uint32_t clksel_timer5_clk;     // 0x18
 182         uint32_t clksel_timer6_clk;     // 0x1c
 183         uint32_t cm_cpts_rft_clksel;    // 0x20
 184         uint8_t _rsv1[4];               // 0x24-0x27
 185         uint32_t clksel_timer1ms_clk;   // 0x28
 186         uint32_t clksel_gfx_fclk;       // 0x2c
 187         uint32_t clksel_pru_icss_ocp_clk;       // 0x30
 188         uint32_t clksel_lcdc_pixel_clk; // 0x34
 189         uint32_t clksel_wdt1_clk;       // 0x38
 190         uint32_t clksel_gpio0_dbclk;    // 0x3c
 191 } __packed;
 192 static struct am335x_cm_dpll_regs * const am335x_cm_dpll = (void *)0x44e00500;
 193
 194 /* Clock module mpu registers */
 195 struct am335x_cm_mpu_regs {
 196         uint32_t st;                    // 0x0
 197         uint32_t mpu;                   // 0x4
 198 } __packed;
 199 static struct am335x_cm_mpu_regs * const am335x_cm_mpu = (void *)0x44e00600;
 200
 201 /* Clock module device registers */
 202 struct am335x_cm_device_regs {
 203         uint32_t cm_clkout_ctrl;        // 0x0
 204 } __packed;
 205 static struct am335x_cm_device_regs * const am335x_cm_device =
 206                 (void *)0x44e00700;
 207
 208 /* Clock module RTC registers */
 209 struct am335x_cm_rtc_regs {
 210         uint32_t rtc;                   // 0x0
 211         uint32_t st;                    // 0x4
 212 } __packed;
 213 static struct am335x_cm_rtc_regs * const am335x_cm_rtc = (void *)0x44e00800;
 214
 215 /* Clock module graphics controller registers */
 216 struct am335x_cm_gfx_regs {
 217         uint32_t l3_st;                 // 0x0
 218         uint32_t gfx;                   // 0x4
 219         uint8_t _rsv0[4];               // 0x8-0xb
 220         uint32_t l4ls_gfx_st;           // 0xc
 221         uint32_t mmucfg;                // 0x10
 222         uint32_t mmudata;               // 0x14
 223 } __packed;
 224 static struct am335x_cm_gfx_regs * const am335x_cm_gfx = (void *)0x44e00900;
 225
 226 /* Clock module efuse registers */
 227 struct am335x_cm_cefuse_regs {
 228         uint32_t st;                    // 0x0
 229         uint8_t _rsv0[0x1c];            // 0x4-0x1f
 230         uint32_t cefuse;                // 0x20
 231 } __packed;
 232 static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse =
 233                 (void *)0x44e00a00;
 234
 235 #endif  /* __CPU_TI_AM335X_CLOCK_H__ */