src/northbridge/intel/haswell/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <types.h>
  19 #include <string.h>
  20 #include <console/console.h>
  21 #include <arch/io.h>
  22 #include <arch/acpi.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include "haswell.h"
  27 #include <cbmem.h>
  28 #include <arch/acpigen.h>
  29 #include <cpu/cpu.h>
  30
  31 unsigned long acpi_fill_mcfg(unsigned long current)
  32 {
  33         device_t dev;
  34         u32 pciexbar = 0;
  35         u32 pciexbar_reg;
  36         int max_buses;
  37
  38         dev = dev_find_slot(0, PCI_DEVFN(0, 0));
  39         if (!dev)
  40                 return current;
  41
  42         pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
  43
  44         // MMCFG not supported or not enabled.
  45         if (!(pciexbar_reg & (1 << 0)))
  46                 return current;
  47
  48         switch ((pciexbar_reg >> 1) & 3) {
  49         case 0: // 256MB
  50                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
  51                 max_buses = 256;
  52                 break;
  53         case 1: // 128M
  54                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  55                 max_buses = 128;
  56                 break;
  57         case 2: // 64M
  58                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
  59                 max_buses = 64;
  60                 break;
  61         default: // RSVD
  62                 return current;
  63         }
  64
  65         if (!pciexbar)
  66                 return current;
  67
  68         current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
  69                         pciexbar, 0x0, 0x0, max_buses - 1);
  70
  71         return current;
  72 }
  73
  74 static void *get_intel_vbios(void)
  75 {
  76         /* This should probably be looking at CBFS or we should always
  77          * deploy the VBIOS on Intel systems, even if we don't run it
  78          * in coreboot (e.g. SeaBIOS only scenarios).
  79          */
  80         u8 *vbios = (u8 *)0xc0000;
  81
  82         optionrom_header_t *oprom = (optionrom_header_t *)vbios;
  83         optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
  84                                                 oprom->pcir_offset);
  85
  86
  87         printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
  88                 oprom->signature, pcir->vendor, pcir->classcode[0],
  89                 pcir->classcode[1], pcir->classcode[2]);
  90
  91
  92         if ((oprom->signature == OPROM_SIGNATURE) &&
  93                 (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
  94                 (pcir->classcode[0] == 0x00) &&
  95                 (pcir->classcode[1] == 0x00) &&
  96                 (pcir->classcode[2] == 0x03))
  97                 return (void *)vbios;
  98
  99         return NULL;
 100 }
 101
 102 static int init_opregion_vbt(igd_opregion_t *opregion)
 103 {
 104         void *vbios;
 105         vbios = get_intel_vbios();
 106         if (!vbios) {
 107                 printk(BIOS_DEBUG, "VBIOS not found.\n");
 108                 return 1;
 109         }
 110
 111         printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
 112         optionrom_header_t *oprom = (optionrom_header_t *)vbios;
 113         optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
 114                                                 oprom->vbt_offset);
 115
 116         if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
 117                 printk(BIOS_DEBUG, "VBT not found!\n");
 118                 return 1;
 119         }
 120
 121         memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
 122         memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
 123                                                 vbt->hdr_vbt_size : 7168);
 124
 125         return 0;
 126 }
 127
 128
 129 /* Initialize IGD OpRegion, called from ACPI code */
 130 int init_igd_opregion(igd_opregion_t *opregion)
 131 {
 132         device_t igd;
 133         u16 reg16;
 134
 135         memset((void *)opregion, 0, sizeof(igd_opregion_t));
 136
 137         // FIXME if IGD is disabled, we should exit here.
 138
 139         memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
 140                 sizeof(opregion->header.signature));
 141
 142         /* 8kb */
 143         opregion->header.size = sizeof(igd_opregion_t) / 1024;
 144         opregion->header.version = IGD_OPREGION_VERSION;
 145
 146         // FIXME We just assume we're mobile for now
 147         opregion->header.mailboxes = MAILBOXES_MOBILE;
 148
 149         // TODO Initialize Mailbox 1
 150
 151         // TODO Initialize Mailbox 3
 152         opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
 153         opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
 154         opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
 155         opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
 156         opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
 157         opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
 158         opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
 159         opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
 160         opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
 161         opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
 162         opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
 163         opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
 164         opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
 165         opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
 166         opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
 167
 168         init_opregion_vbt(opregion);
 169
 170         /* TODO This needs to happen in S3 resume, too.
 171          * Maybe it should move to the finalize handler
 172          */
 173         igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
 174
 175         pci_write_config32(igd, ASLS, (u32)opregion);
 176         reg16 = pci_read_config16(igd, SWSCI);
 177         reg16 &= ~(1 << 0);
 178         reg16 |= (1 << 15);
 179         pci_write_config16(igd, SWSCI, reg16);
 180
 181         /* clear dmisci status */
 182         reg16 = inw(get_pmbase() + TCO1_STS);
 183         reg16 |= DMISCI_STS; // reference code does an &=
 184         outw(get_pmbase() + TCO1_STS, reg16);
 185
 186         /* clear and enable ACPI TCO SCI */
 187         enable_tco_sci();
 188
 189         return 0;
 190 }