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soc/amd/common: Create AcpiMmio functionality from stoneyridge
[coreboot.git] / src / soc / amd / stoneyridge / southbridge.c
blobbf8787c1fcac7fc21e209f04525d3bd8421df979
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010-2017 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <console/console.h>
17
18 #include <device/mmio.h>
19 #include <bootstate.h>
20 #include <cpu/x86/smm.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <cbmem.h>
26 #include <elog.h>
27 #include <amdblocks/amd_pci_util.h>
28 #include <amdblocks/agesawrapper.h>
29 #include <amdblocks/reset.h>
30 #include <amdblocks/acpimmio.h>
31 #include <soc/southbridge.h>
32 #include <soc/smbus.h>
33 #include <soc/smi.h>
34 #include <soc/amd_pci_int_defs.h>
35 #include <delay.h>
36 #include <soc/pci_devs.h>
37 #include <agesa_headers.h>
38 #include <soc/nvs.h>
39
40 /*
41 * Table of devices that need their AOAC registers enabled and waited
42 * upon (usually about .55 milliseconds). Instead of individual delays
43 * waiting for each device to become available, a single delay will be
44 * executed.
45 */
46 const static struct stoneyridge_aoac aoac_devs[] = {
47 { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
48 (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) },
49 { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA },
50 { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 },
51 { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 },
52 { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 },
53 { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }
54 };
55
56 static int is_sata_config(void)
57 {
58 return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE)
59 || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE));
60 }
61
62 static inline int sb_sata_enable(void)
63 {
64 /* True if IDE or AHCI. */
65 return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
66 (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE);
67 }
68
69 static inline int sb_ide_enable(void)
70 {
71 /* True if IDE or LEGACY IDE. */
72 return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) ||
73 (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE);
74 }
75
76 void SetFchResetParams(FCH_RESET_INTERFACE *params)
77 {
78 const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
79 params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE);
80 if (dev && dev->enabled) {
81 params->SataEnable = sb_sata_enable();
82 params->IdeEnable = sb_ide_enable();
83 } else {
84 params->SataEnable = FALSE;
85 params->IdeEnable = FALSE;
86 }
87 }
88
89 void SetFchEnvParams(FCH_INTERFACE *params)
90 {
91 const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
92 params->AzaliaController = AzEnable;
93 params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
94 if (dev && dev->enabled) {
95 params->SataEnable = is_sata_config();
96 params->IdeEnable = !params->SataEnable;
97 params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE ==
98 SataLegacyIde);
99 } else {
100 params->SataEnable = FALSE;
101 params->IdeEnable = FALSE;
102 params->SataIdeMode = FALSE;
103 }
104 }
105
106 void SetFchMidParams(FCH_INTERFACE *params)
107 {
108 SetFchEnvParams(params);
109 }
110
111 /*
112 * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
113 * provides a visible association with the index, therefore helping
114 * maintainability of table. If a new index/name is defined in
115 * amd_pci_int_defs.h, just add the pair at the end of this table.
116 * Order is not important.
117 */
118 const static struct irq_idx_name irq_association[] = {
119 { PIRQ_A, "INTA#" },
120 { PIRQ_B, "INTB#" },
121 { PIRQ_C, "INTC#" },
122 { PIRQ_D, "INTD#" },
123 { PIRQ_E, "INTE#" },
124 { PIRQ_F, "INTF#" },
125 { PIRQ_G, "INTG#" },
126 { PIRQ_H, "INTH#" },
127 { PIRQ_MISC, "Misc" },
128 { PIRQ_MISC0, "Misc0" },
129 { PIRQ_MISC1, "Misc1" },
130 { PIRQ_MISC2, "Misc2" },
131 { PIRQ_SIRQA, "Ser IRQ INTA" },
132 { PIRQ_SIRQB, "Ser IRQ INTB" },
133 { PIRQ_SIRQC, "Ser IRQ INTC" },
134 { PIRQ_SIRQD, "Ser IRQ INTD" },
135 { PIRQ_SCI, "SCI" },
136 { PIRQ_SMBUS, "SMBUS" },
137 { PIRQ_ASF, "ASF" },
138 { PIRQ_HDA, "HDA" },
139 { PIRQ_FC, "FC" },
140 { PIRQ_PMON, "PerMon" },
141 { PIRQ_SD, "SD" },
142 { PIRQ_SDIO, "SDIOt" },
143 { PIRQ_EHCI, "EHCI" },
144 { PIRQ_XHCI, "XHCI" },
145 { PIRQ_SATA, "SATA" },
146 { PIRQ_GPIO, "GPIO" },
147 { PIRQ_I2C0, "I2C0" },
148 { PIRQ_I2C1, "I2C1" },
149 { PIRQ_I2C2, "I2C2" },
150 { PIRQ_I2C3, "I2C3" },
151 { PIRQ_UART0, "UART0" },
152 { PIRQ_UART1, "UART1" },
153 };
154
155 /*
156 * Structure to simplify code obtaining the total of used wide IO
157 * registers and the size assigned to each.
158 */
159 static struct wide_io_ioport_and_bits {
160 uint32_t enable;
161 uint16_t port;
162 uint8_t alt;
163 } wio_io_en[TOTAL_WIDEIO_PORTS] = {
164 {
165 LPC_WIDEIO0_ENABLE,
166 LPC_WIDEIO_GENERIC_PORT,
167 LPC_ALT_WIDEIO0_ENABLE
168 },
169 {
170 LPC_WIDEIO1_ENABLE,
171 LPC_WIDEIO1_GENERIC_PORT,
172 LPC_ALT_WIDEIO1_ENABLE
173 },
174 {
175 LPC_WIDEIO2_ENABLE,
176 LPC_WIDEIO2_GENERIC_PORT,
177 LPC_ALT_WIDEIO2_ENABLE
178 }
179 };
180
181 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
182 {
183 *size = ARRAY_SIZE(irq_association);
184 return irq_association;
185 }
186
187 /**
188 * @brief Find the size of a particular wide IO
189 *
190 * @param index = index of desired wide IO
191 *
192 * @return size of desired wide IO
193 */
194 uint16_t sb_wideio_size(int index)
195 {
196 uint32_t enable_register;
197 uint16_t size = 0;
198 uint8_t alternate_register;
199
200 if (index >= TOTAL_WIDEIO_PORTS)
201 return size;
202 enable_register = pci_read_config32(SOC_LPC_DEV,
203 LPC_IO_OR_MEM_DECODE_ENABLE);
204 alternate_register = pci_read_config8(SOC_LPC_DEV,
205 LPC_ALT_WIDEIO_RANGE_ENABLE);
206 if (enable_register & wio_io_en[index].enable)
207 size = (alternate_register & wio_io_en[index].alt) ?
208 16 : 512;
209 return size;
210 }
211
212 /**
213 * @brief Identify if any LPC wide IO is covering the IO range
214 *
215 * @param start = start of IO range
216 * @param size = size of IO range
217 *
218 * @return Index of wide IO covering the range or error
219 */
220 int sb_find_wideio_range(uint16_t start, uint16_t size)
221 {
222 int i, index = WIDEIO_RANGE_ERROR;
223 uint16_t end, current_size, start_wideio, end_wideio;
224
225 end = start + size;
226 for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) {
227 current_size = sb_wideio_size(i);
228 if (current_size == 0)
229 continue;
230 start_wideio = pci_read_config16(SOC_LPC_DEV,
231 wio_io_en[i].port);
232 end_wideio = start_wideio + current_size;
233 if ((start >= start_wideio) && (end <= end_wideio)) {
234 index = i;
235 break;
236 }
237 }
238 return index;
239 }
240
241 /**
242 * @brief Program a LPC wide IO to support an IO range
243 *
244 * @param start = start of range to be routed through wide IO
245 * @param size = size of range to be routed through wide IO
246 *
247 * @return Index of wide IO register used or error
248 */
249 int sb_set_wideio_range(uint16_t start, uint16_t size)
250 {
251 int i, index = WIDEIO_RANGE_ERROR;
252 uint32_t enable_register;
253 uint8_t alternate_register;
254
255 enable_register = pci_read_config32(SOC_LPC_DEV,
256 LPC_IO_OR_MEM_DECODE_ENABLE);
257 alternate_register = pci_read_config8(SOC_LPC_DEV,
258 LPC_ALT_WIDEIO_RANGE_ENABLE);
259 for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) {
260 if (enable_register & wio_io_en[i].enable)
261 continue;
262 index = i;
263 pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start);
264 enable_register |= wio_io_en[i].enable;
265 pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE,
266 enable_register);
267 if (size <= 16)
268 alternate_register |= wio_io_en[i].alt;
269 else
270 alternate_register &= ~wio_io_en[i].alt;
271 pci_write_config8(SOC_LPC_DEV,
272 LPC_ALT_WIDEIO_RANGE_ENABLE,
273 alternate_register);
274 break;
275 }
276 return index;
277 }
278
279 static void power_on_aoac_device(int aoac_device_control_register)
280 {
281 uint8_t byte;
282
283 /* Power on the UART and AMBA devices */
284 byte = aoac_read8(aoac_device_control_register);
285 byte |= FCH_AOAC_PWR_ON_DEV;
286 aoac_write8(aoac_device_control_register, byte);
287 }
288
289 static bool is_aoac_device_enabled(int aoac_device_status_register)
290 {
291 uint8_t byte;
292
293 byte = aoac_read8(aoac_device_status_register);
294 byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
295 if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
296 return true;
297 else
298 return false;
299 }
300
301 void enable_aoac_devices(void)
302 {
303 bool status;
304 int i;
305
306 for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
307 power_on_aoac_device(aoac_devs[i].enable);
308
309 /* Wait for AOAC devices to indicate power and clock OK */
310 do {
311 udelay(100);
312 status = true;
313 for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
314 status &= is_aoac_device_enabled(aoac_devs[i].status);
315 } while (!status);
316 }
317
318 void sb_pci_port80(void)
319 {
320 u8 byte;
321
322 byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
323 byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */
324 pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
325 }
326
327 void sb_lpc_port80(void)
328 {
329 u8 byte;
330
331 /* Enable LPC controller */
332 byte = pm_io_read8(PM_LPC_GATING);
333 byte |= PM_LPC_ENABLE;
334 pm_io_write8(PM_LPC_GATING, byte);
335
336 /* Enable port 80 LPC decode in pci function 3 configuration space. */
337 byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
338 byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */
339 pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
340 }
341
342 void sb_lpc_decode(void)
343 {
344 u32 tmp = 0;
345
346 /* Enable I/O decode to LPC bus */
347 tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
348 | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
349 | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
350 | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
351 | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
352 | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
353 | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
354 | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
355 | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
356 | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
357 | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
358 | DECODE_ENABLE_ADLIB_PORT;
359
360 pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
361 }
362
363 static void sb_enable_cf9_io(void)
364 {
365 uint32_t reg = pm_read32(PM_DECODE_EN);
366
367 pm_write32(PM_DECODE_EN, reg | CF9_IO_EN);
368 }
369
370 static void sb_enable_legacy_io(void)
371 {
372 uint32_t reg = pm_read32(PM_DECODE_EN);
373
374 pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
375 }
376
377 void sb_clk_output_48Mhz(u32 osc)
378 {
379 u32 ctrl;
380
381 /*
382 * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
383 * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
384 */
385 ctrl = misc_read32(MISC_CLK_CNTL1);
386
387 switch (osc) {
388 case 1:
389 ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
390 break;
391 case 2:
392 ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
393 break;
394 default:
395 return; /* do nothing if invalid */
396 }
397 misc_write32(MISC_CLK_CNTL1, ctrl);
398 }
399
400 static uintptr_t sb_spibase(void)
401 {
402 u32 base, enables;
403
404 /* Make sure the base address is predictable */
405 base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
406 enables = base & SPI_PRESERVE_BITS;
407 base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
408
409 if (!base) {
410 base = SPI_BASE_ADDRESS;
411 pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER,
412 base | enables | SPI_ROM_ENABLE);
413 /* PCI_COMMAND_MEMORY is read-only and enabled. */
414 }
415 return (uintptr_t)base;
416 }
417
418 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
419 {
420 uintptr_t base = sb_spibase();
421 write16((void *)(base + SPI100_SPEED_CONFIG),
422 (norm << SPI_NORM_SPEED_NEW_SH) |
423 (fast << SPI_FAST_SPEED_NEW_SH) |
424 (alt << SPI_ALT_SPEED_NEW_SH) |
425 (tpm << SPI_TPM_SPEED_NEW_SH));
426 write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
427 }
428
429 void sb_disable_4dw_burst(void)
430 {
431 uintptr_t base = sb_spibase();
432 write16((void *)(base + SPI100_HOST_PREF_CONFIG),
433 read16((void *)(base + SPI100_HOST_PREF_CONFIG))
434 & ~SPI_RD4DW_EN_HOST);
435 }
436
437 void sb_read_mode(u32 mode)
438 {
439 uintptr_t base = sb_spibase();
440 write32((void *)(base + SPI_CNTRL0),
441 (read32((void *)(base + SPI_CNTRL0))
442 & ~SPI_READ_MODE_MASK) | mode);
443 }
444
445 /*
446 * Enable FCH to decode TPM associated Memory and IO regions
447 *
448 * Enable decoding of TPM cycles defined in TPM 1.2 spec
449 * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
450 * 0x7e and 0xef-0xee.
451 * This function should be called if TPM is connected in any way to the FCH and
452 * conforms to the regions decoded.
453 * Absent any other routing configuration the TPM cycles will be claimed by the
454 * LPC bus
455 */
456 void sb_tpm_decode(void)
457 {
458 u32 value;
459
460 value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE);
461 value |= TPM_12_EN | TPM_LEGACY_EN;
462 pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
463 }
464
465 /*
466 * Enable FCH to decode TPM associated Memory and IO regions to SPI
467 *
468 * This should be used if TPM is connected to SPI bus.
469 * Assumes SPI address space is already configured via a call to sb_spibase().
470 */
471 void sb_tpm_decode_spi(void)
472 {
473 /* Enable TPM decoding to FCH */
474 sb_tpm_decode();
475
476 /* Route TPM accesses to SPI */
477 u32 spibase = pci_read_config32(SOC_LPC_DEV,
478 SPIROM_BASE_ADDRESS_REGISTER);
479 pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase
480 | ROUTE_TPM_2_SPI);
481 }
482
483 /*
484 * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
485 *
486 * Hardware should enable LPC ROM by pin straps. This function does not
487 * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
488 *
489 * The southbridge power-on default is to map 512K ROM space.
490 *
491 */
492 void sb_enable_rom(void)
493 {
494 u8 reg8;
495
496 /*
497 * Decode variable LPC ROM address ranges 1 and 2.
498 * Bits 3-4 are not defined in any publicly available datasheet
499 */
500 reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
501 reg8 |= (1 << 3) | (1 << 4);
502 pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
503
504 /*
505 * LPC ROM address range 1:
506 * Enable LPC ROM range mirroring start at 0x000e(0000).
507 */
508 pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e);
509
510 /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
511 pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f);
512
513 /*
514 * LPC ROM address range 2:
515 *
516 * Enable LPC ROM range start at:
517 * 0xfff8(0000): 512KB
518 * 0xfff0(0000): 1MB
519 * 0xffe0(0000): 2MB
520 * 0xffc0(0000): 4MB
521 */
522 pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
523 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
524
525 /* Enable LPC ROM range end at 0xffff(ffff). */
526 pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
527 }
528
529 static void sb_lpc_early_setup(void)
530 {
531 uint32_t dword;
532
533 /* Enable SPI prefetch */
534 dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL);
535 dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;
536 pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
537
538 if (CONFIG(STONEYRIDGE_LEGACY_FREE)) {
539 /* Decode SIOs at 2E/2F and 4E/4F */
540 dword = pci_read_config32(SOC_LPC_DEV,
541 LPC_IO_OR_MEM_DECODE_ENABLE);
542 dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
543 pci_write_config32(SOC_LPC_DEV,
544 LPC_IO_OR_MEM_DECODE_ENABLE, dword);
545 }
546 }
547
548 static void setup_spread_spectrum(int *reboot)
549 {
550 uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
551
552 rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
553 pm_write16(PWR_RESET_CFG, rstcfg);
554
555 uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
556
557 if (cntl1 & CG1PLL_FBDIV_TEST) {
558 printk(BIOS_DEBUG, "Spread spectrum is ready\n");
559 misc_write32(MISC_CGPLL_CONFIG1,
560 misc_read32(MISC_CGPLL_CONFIG1) |
561 CG1PLL_SPREAD_SPECTRUM_ENABLE);
562
563 return;
564 }
565
566 printk(BIOS_DEBUG, "Setting up spread spectrum\n");
567
568 uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
569 cfg6 &= ~CG1PLL_LF_MODE_MASK;
570 cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
571 misc_write32(MISC_CGPLL_CONFIG6, cfg6);
572
573 uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
574 cfg3 &= ~CG1PLL_REFDIV_MASK;
575 cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
576 cfg3 &= ~CG1PLL_FBDIV_MASK;
577 cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
578 misc_write32(MISC_CGPLL_CONFIG3, cfg3);
579
580 uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
581 cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;
582 cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;
583 misc_write32(MISC_CGPLL_CONFIG5, cfg5);
584
585 uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
586 cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;
587 cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;
588 cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;
589 cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)
590 & SS_STEP_SIZE_DSFRAC_MASK;
591 misc_write32(MISC_CGPLL_CONFIG4, cfg4);
592
593 rstcfg |= TOGGLE_ALL_PWR_GOOD;
594 pm_write16(PWR_RESET_CFG, rstcfg);
595
596 cntl1 |= CG1PLL_FBDIV_TEST;
597 misc_write32(MISC_CLK_CNTL1, cntl1);
598
599 *reboot = 1;
600 }
601
602 static void setup_misc(int *reboot)
603 {
604 /* Undocumented register */
605 uint32_t reg = misc_read32(0x50);
606 if (!(reg & BIT(16))) {
607 reg |= BIT(16);
608
609 misc_write32(0x50, reg);
610 *reboot = 1;
611 }
612 }
613
614 static void fch_smbus_init(void)
615 {
616 pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
617 smbus_write8(SMBTIMING, SMB_SPEED_400KHZ);
618 /* Clear all SMBUS status bits */
619 smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
620 smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
621 asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
622 asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
623 }
624
625 /* Before console init */
626 void bootblock_fch_early_init(void)
627 {
628 int reboot = 0;
629
630 sb_enable_rom();
631 sb_lpc_port80();
632 sb_lpc_decode();
633 sb_lpc_early_setup();
634 sb_spibase();
635 sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
636 enable_acpimmio_decode();
637 fch_smbus_init();
638 sb_enable_cf9_io();
639 setup_spread_spectrum(&reboot);
640 setup_misc(&reboot);
641
642 if (reboot)
643 warm_reset();
644
645 sb_enable_legacy_io();
646 enable_aoac_devices();
647 }
648
649 static void print_num_status_bits(int num_bits, uint32_t status,
650 const char *const bit_names[])
651 {
652 int i;
653
654 if (!status)
655 return;
656
657 for (i = num_bits - 1; i >= 0; i--) {
658 if (status & (1 << i)) {
659 if (bit_names[i])
660 printk(BIOS_DEBUG, "%s ", bit_names[i]);
661 else
662 printk(BIOS_DEBUG, "BIT%d ", i);
663 }
664 }
665 }
666
667 static void sb_print_pmxc0_status(void)
668 {
669 /* PMxC0 S5/Reset Status shows the source of previous reset. */
670 uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
671
672 static const char *const pmxc0_status_bits[32] = {
673 [0] = "ThermalTrip",
674 [1] = "FourSecondPwrBtn",
675 [2] = "Shutdown",
676 [3] = "ThermalTripFromTemp",
677 [4] = "RemotePowerDownFromASF",
678 [5] = "ShutDownFan0",
679 [16] = "UserRst",
680 [17] = "SoftPciRst",
681 [18] = "DoInit",
682 [19] = "DoReset",
683 [20] = "DoFullReset",
684 [21] = "SleepReset",
685 [22] = "KbReset",
686 [23] = "LtReset",
687 [24] = "FailBootRst",
688 [25] = "WatchdogIssueReset",
689 [26] = "RemoteResetFromASF",
690 [27] = "SyncFlood",
691 [28] = "HangReset",
692 [29] = "EcWatchdogRst",
693 };
694
695 printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status);
696 print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
697 pmxc0_status_bits);
698 printk(BIOS_DEBUG, "\n");
699 }
700
701 /* After console init */
702 void bootblock_fch_init(void)
703 {
704 sb_print_pmxc0_status();
705 }
706
707 void sb_enable(struct device *dev)
708 {
709 printk(BIOS_DEBUG, "%s\n", __func__);
710 }
711
712 static void sb_init_acpi_ports(void)
713 {
714 u32 reg;
715
716 /* We use some of these ports in SMM regardless of whether or not
717 * ACPI tables are generated. Enable these ports indiscriminately.
718 */
719
720 pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
721 pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
722 pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
723 pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
724 /* CpuControl is in \_PR.CP00, 6 bytes */
725 pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
726
727 if (CONFIG(HAVE_SMI_HANDLER)) {
728 /* APMC - SMI Command Port */
729 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
730 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
731
732 /* SMI on SlpTyp requires sending SMI before completion
733 * response of the I/O write. The BKDG also specifies
734 * clearing ForceStpClkRetry for SMI trapping.
735 */
736 reg = pm_read32(PM_PCI_CTRL);
737 reg |= FORCE_SLPSTATE_RETRY;
738 reg &= ~FORCE_STPCLK_RETRY;
739 pm_write32(PM_PCI_CTRL, reg);
740
741 /* Disable SlpTyp feature */
742 reg = pm_read8(PM_RST_CTRL1);
743 reg &= ~SLPTYPE_CONTROL_EN;
744 pm_write8(PM_RST_CTRL1, reg);
745
746 configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
747 } else {
748 pm_write16(PM_ACPI_SMI_CMD, 0);
749 }
750
751 /* Decode ACPI registers and enable standard features */
752 pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
753 PM_ACPI_GLOBAL_EN |
754 PM_ACPI_RTC_EN_EN |
755 PM_ACPI_TIMER_EN_EN);
756 }
757
758 static uint16_t reset_pm1_status(void)
759 {
760 uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS);
761 acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts);
762 return pm1_sts;
763 }
764
765 static uint16_t print_pm1_status(uint16_t pm1_sts)
766 {
767 static const char *const pm1_sts_bits[16] = {
768 [0] = "TMROF",
769 [4] = "BMSTATUS",
770 [5] = "GBL",
771 [8] = "PWRBTN",
772 [10] = "RTC",
773 [14] = "PCIEXPWAK",
774 [15] = "WAK",
775 };
776
777 if (!pm1_sts)
778 return 0;
779
780 printk(BIOS_DEBUG, "PM1_STS: ");
781 print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
782 printk(BIOS_DEBUG, "\n");
783
784 return pm1_sts;
785 }
786
787 static void sb_log_pm1_status(uint16_t pm1_sts)
788 {
789 if (!CONFIG(ELOG))
790 return;
791
792 if (pm1_sts & WAK_STS)
793 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
794 acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
795
796 if (pm1_sts & PWRBTN_STS)
797 elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
798
799 if (pm1_sts & RTC_STS)
800 elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
801
802 if (pm1_sts & PCIEXPWAK_STS)
803 elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
804 }
805
806 static void sb_save_sws(uint16_t pm1_status)
807 {
808 struct soc_power_reg *sws;
809 uint32_t reg32;
810 uint16_t reg16;
811
812 sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg));
813 if (sws == NULL)
814 return;
815 sws->pm1_sts = pm1_status;
816 sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN);
817 reg32 = acpi_read32(MMIO_ACPI_GPE0_STS);
818 acpi_write32(MMIO_ACPI_GPE0_STS, reg32);
819 sws->gpe0_sts = reg32;
820 sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN);
821 reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
822 reg16 &= SLP_TYP;
823 sws->wake_from = reg16 >> SLP_TYP_SHIFT;
824 }
825
826 static void sb_clear_pm1_status(void)
827 {
828 uint16_t pm1_sts = reset_pm1_status();
829
830 sb_save_sws(pm1_sts);
831 sb_log_pm1_status(pm1_sts);
832 print_pm1_status(pm1_sts);
833 }
834
835 static int get_index_bit(uint32_t value, uint16_t limit)
836 {
837 uint16_t i;
838 uint32_t t;
839
840 if (limit >= TOTAL_BITS(uint32_t))
841 return -1;
842
843 /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */
844 t = (1 << limit) - 1;
845 if ((value & t) == 0)
846 return -1;
847 t = 1;
848 for (i = 0; i < limit; i++) {
849 if (value & t)
850 break;
851 t <<= 1;
852 }
853 return i;
854 }
855
856 static void set_nvs_sws(void *unused)
857 {
858 struct soc_power_reg *sws;
859 struct global_nvs_t *gnvs;
860 int index;
861
862 sws = cbmem_find(CBMEM_ID_POWER_STATE);
863 if (sws == NULL)
864 return;
865 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
866 if (gnvs == NULL)
867 return;
868
869 index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT);
870 if (index < 0)
871 gnvs->pm1i = ~0ULL;
872 else
873 gnvs->pm1i = index;
874
875 index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT);
876 if (index < 0)
877 gnvs->gpei = ~0ULL;
878 else
879 gnvs->gpei = index;
880 }
881
882 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
883
884 void southbridge_init(void *chip_info)
885 {
886 sb_init_acpi_ports();
887 sb_clear_pm1_status();
888 }
889
890 static void set_sb_final_nvs(void)
891 {
892 uintptr_t amdfw_rom;
893 uintptr_t xhci_fw;
894 uintptr_t fwaddr;
895 size_t fwsize;
896 const struct device *sd, *sata;
897
898 struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
899 if (gnvs == NULL)
900 return;
901
902 gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);
903 gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);
904 gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);
905 gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);
906 gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0);
907 gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1);
908 gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2);
909 gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3);
910 /* Rely on these being in sync with devicetree */
911 sd = pcidev_path_on_root(SD_DEVFN);
912 gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0;
913 sata = pcidev_path_on_root(SATA_DEVFN);
914 gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0;
915 gnvs->aoac.espi = 1;
916
917 amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX);
918 xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET));
919
920 fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET
921 + XHCI_FW_BOOTRAM_SIZE));
922 fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET
923 + XHCI_FW_BOOTRAM_SIZE));
924 gnvs->fw00 = 0;
925 gnvs->fw01 = ((32 * KiB) << 16) + 0;
926 gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
927 gnvs->fw03 = fwsize << 16;
928
929 gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
930 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
931 }
932
933 void southbridge_final(void *chip_info)
934 {
935 uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
936
937 if (CONFIG(MAINBOARD_POWER_RESTORE))
938 restored_power = PM_RESTORE_S0_IF_PREV_S0;
939 pm_write8(PM_RTC_SHADOW, restored_power);
940
941 set_sb_final_nvs();
942 }
943
944 /*
945 * Update the PCI devices with a valid IRQ number
946 * that is set in the mainboard PCI_IRQ structures.
947 */
948 static void set_pci_irqs(void *unused)
949 {
950 /* Write PCI_INTR regs 0xC00/0xC01 */
951 write_pci_int_table();
952
953 /* Write IRQs for all devicetree enabled devices */
954 write_pci_cfg_irqs();
955 }
956
957 /*
958 * Hook this function into the PCI state machine
959 * on entry into BS_DEV_ENABLE.
960 */
961 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
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