src/soc/amd/stoneyridge/smihandler.c

   1 /*
   2  * SMI handler for Hudson southbridges
   3  *
   4  * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
   5  * Subject to the GNU GPL v2, or (at your option) any later version.
   6  */
   7
   8 #include <console/console.h>
   9 #include <cpu/x86/smm.h>
  10 #include <delay.h>
  11 #include <soc/smi.h>
  12 #include <soc/southbridge.h>
  13
  14
  15 #define SMI_0x88_ACPI_COMMAND           (1 << 11)
  16
  17 enum smi_source {
  18         SMI_SOURCE_SCI = (1 << 0),
  19         SMI_SOURCE_GPE = (1 << 1),
  20         SMI_SOURCE_0x84 = (1 << 2),
  21         SMI_SOURCE_0x88 = (1 << 3),
  22         SMI_SOURCE_IRQ_TRAP = (1 << 4),
  23         SMI_SOURCE_0x90 = (1 << 5)
  24 };
  25
  26 static void sb_apmc_smi_handler(void)
  27 {
  28         u32 reg32;
  29         const uint8_t cmd = inb(pm_acpi_smi_cmd_port());
  30
  31         switch (cmd) {
  32         case APM_CNT_ACPI_ENABLE:
  33                 reg32 = inl(ACPI_PM1_CNT_BLK);
  34                 reg32 |= (1 << 0);      /* SCI_EN */
  35                 outl(reg32, ACPI_PM1_CNT_BLK);
  36                 break;
  37         case APM_CNT_ACPI_DISABLE:
  38                 reg32 = inl(ACPI_PM1_CNT_BLK);
  39                 reg32 &= ~(1 << 0);     /* clear SCI_EN */
  40                 outl(ACPI_PM1_CNT_BLK, reg32);
  41                 break;
  42         }
  43
  44         mainboard_smi_apmc(cmd);
  45 }
  46
  47 int southbridge_io_trap_handler(int smif)
  48 {
  49         return 0;
  50 }
  51
  52 static void process_smi_sci(void)
  53 {
  54         const uint32_t status = smi_read32(0x10);
  55
  56         /* Clear events to prevent re-entering SMI if event isn't handled */
  57         smi_write32(0x10, status);
  58 }
  59
  60 static void process_gpe_smi(void)
  61 {
  62         const uint32_t status = smi_read32(0x80);
  63         const uint32_t gevent_mask = (1 << 24) - 1;
  64
  65         /* Only Bits [23:0] indicate GEVENT SMIs. */
  66         if (status & gevent_mask) {
  67                 /* A GEVENT SMI occurred */
  68                 mainboard_smi_gpi(status & gevent_mask);
  69         }
  70
  71         /* Clear events to prevent re-entering SMI if event isn't handled */
  72         smi_write32(0x80, status);
  73 }
  74
  75 static void process_smi_0x84(void)
  76 {
  77         const uint32_t status = smi_read32(0x84);
  78
  79         /* Clear events to prevent re-entering SMI if event isn't handled */
  80         smi_write32(0x84, status);
  81 }
  82
  83 static void process_smi_0x88(void)
  84 {
  85         const uint32_t status = smi_read32(0x88);
  86
  87         if (status & SMI_0x88_ACPI_COMMAND) {
  88                 /* Command received via ACPI SMI command port */
  89                 sb_apmc_smi_handler();
  90         }
  91         /* Clear events to prevent re-entering SMI if event isn't handled */
  92         smi_write32(0x88, status);
  93 }
  94
  95 static void process_smi_0x8c(void)
  96 {
  97         const uint32_t status = smi_read32(0x8c);
  98
  99         /* Clear events to prevent re-entering SMI if event isn't handled */
 100         smi_write32(0x8c, status);
 101 }
 102
 103 static void process_smi_0x90(void)
 104 {
 105         const uint32_t status = smi_read32(0x90);
 106
 107         /* Clear events to prevent re-entering SMI if event isn't handled */
 108         smi_write32(0x90, status);
 109 }
 110
 111 void southbridge_smi_handler(void)
 112 {
 113         const uint16_t smi_src = smi_read16(0x94);
 114
 115         if (smi_src & SMI_SOURCE_SCI)
 116                 process_smi_sci();
 117         if (smi_src & SMI_SOURCE_GPE)
 118                 process_gpe_smi();
 119         if (smi_src & SMI_SOURCE_0x84)
 120                 process_smi_0x84();
 121         if (smi_src & SMI_SOURCE_0x88)
 122                 process_smi_0x88();
 123         if (smi_src & SMI_SOURCE_IRQ_TRAP)
 124                 process_smi_0x8c();
 125         if (smi_src & SMI_SOURCE_0x90)
 126                 process_smi_0x90();
 127 }
 128
 129 void southbridge_smi_set_eos(void)
 130 {
 131         uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
 132         reg |= SMITRG0_EOS;
 133         smi_write32(SMI_REG_SMITRIG0, reg);
 134 }