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drivers/elog: Rename ramstage_elog_add_boot_count() to elog_add_boot_count()
[coreboot.git] / util / inteltool / cpu.c
blobef2df3cd00df4630c35f05ff992ad4182ab47a2a
1 /*
2 * inteltool - dump all registers on an Intel CPU + chipset based system.
3 *
4 * Copyright (C) 2008-2010 by coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <fcntl.h>
17 #include <unistd.h>
18 #include <stdio.h>
19 #include <stdlib.h>
20 #include <string.h>
21 #include <errno.h>
22
23 #include "inteltool.h"
24
25 #ifdef __x86_64__
26 # define BREG "%%rbx"
27 #else
28 # define BREG "%%ebx"
29 #endif
30
31 #define IA32_FEATURE_CONTROL 0x3a
32 #define SGX_GLOBAL_ENABLED (1 << 18)
33 #define FEATURE_CONTROL_LOCKED (1)
34 #define MTRR_CAP_MSR 0xfe
35 #define PRMRR_SUPPORTED (1 << 12)
36 #define SGX_SUPPORTED (1 << 2)
37
38 int fd_msr;
39
40 unsigned int cpuid(unsigned int op)
41 {
42 uint32_t ret;
43
44 #if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__)
45 asm volatile (
46 "push " BREG "\n\t"
47 "cpuid\n\t"
48 "pop " BREG "\n\t"
49 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
50 );
51 #else
52 asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
53 #endif
54
55 return ret;
56 }
57
58 inline cpuid_result_t cpuid_ext(int op, unsigned int ecx)
59 {
60 cpuid_result_t result;
61
62 #ifndef __DARWIN__
63 asm volatile (
64 "mov %%ebx, %%edi;"
65 "cpuid;"
66 "mov %%ebx, %%esi;"
67 "mov %%edi, %%ebx;"
68 : "=a" (result.eax),
69 "=S" (result.ebx),
70 "=c" (result.ecx),
71 "=d" (result.edx)
72 : "0" (op), "2" (ecx)
73 : "edi");
74 #endif
75 return result;
76 }
77
78 #ifndef __DARWIN__
79 int msr_readerror = 0;
80
81 msr_t rdmsr(int addr)
82 {
83 uint32_t buf[2];
84 msr_t msr = { 0xffffffff, 0xffffffff };
85
86 if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
87 perror("Could not lseek() to MSR");
88 close(fd_msr);
89 exit(1);
90 }
91
92 if (read(fd_msr, buf, 8) == 8) {
93 msr.lo = buf[0];
94 msr.hi = buf[1];
95 return msr;
96 }
97
98 if (errno == 5) {
99 printf(" (*)"); // Not all bits of the MSR could be read
100 msr_readerror = 1;
101 } else {
102 // A severe error.
103 perror("Could not read() MSR");
104 close(fd_msr);
105 exit(1);
106 }
107
108 return msr;
109 }
110
111 static int open_and_seek(int cpu, unsigned long msr, int mode, int *fd)
112 {
113 char dev[512];
114 char temp_string[50];
115
116 snprintf(dev, sizeof(dev), "/dev/cpu/%d/msr", cpu);
117 *fd = open(dev, mode);
118
119 if (*fd < 0) {
120 snprintf(temp_string, sizeof(temp_string), "open(\"%s\")", dev);
121 perror(temp_string);
122 return -1;
123 }
124
125 if (lseek(*fd, msr, SEEK_SET) == (off_t)-1) {
126 snprintf(temp_string, sizeof(temp_string), "lseek(%lu)", msr);
127 perror(temp_string);
128 close(*fd);
129 return -1;
130 }
131
132 return 0;
133 }
134
135 msr_t rdmsr_from_cpu(int cpu, unsigned long addr)
136 {
137 int fd;
138 msr_t msr = { 0xffffffff, 0xffffffff };
139 uint32_t buf[2];
140 char temp_string[50];
141
142 if (open_and_seek(cpu, addr, O_RDONLY, &fd) < 0) {
143 snprintf(temp_string, sizeof(temp_string),
144 "Could not read MSR for CPU#%d", cpu);
145 perror(temp_string);
146 }
147
148 if (read(fd, buf, 8) == 8) {
149 msr.lo = buf[0];
150 msr.hi = buf[1];
151 }
152
153 close(fd);
154
155 return msr;
156 }
157
158 int get_number_of_cpus(void)
159 {
160 return sysconf(_SC_NPROCESSORS_ONLN);
161 }
162
163 int is_sgx_supported(int cpunum)
164 {
165 cpuid_result_t cpuid_regs;
166 msr_t msr;
167
168 /* CPUID leaf 0x7 subleaf 0x0 to detect SGX support
169 details are mentioned in Intel SDM Chap.36- section 36.7 */
170 cpuid_regs = cpuid_ext(0x7, 0x0);
171 msr = rdmsr_from_cpu(cpunum, MTRR_CAP_MSR);
172 return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED));
173 }
174
175 int is_sgx_enabled(int cpunum)
176 {
177 msr_t data;
178 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
179 return (data.lo & SGX_GLOBAL_ENABLED);
180 }
181
182 int is_sgx_locked(int cpunum)
183 {
184 msr_t data;
185 data = rdmsr_from_cpu(cpunum, IA32_FEATURE_CONTROL);
186 return (data.lo & FEATURE_CONTROL_LOCKED);
187 }
188
189 #endif
190
191 int print_sgx(void)
192 {
193 int error = -1;
194 #ifndef __DARWIN__
195 int ncpus = get_number_of_cpus();
196 int i = 0;
197
198 printf("\n============= Dumping INTEL SGX status =============");
199
200 if (ncpus < 1) {
201 perror("Failed to get number of CPUs");
202 error = -1;
203 } else {
204 printf("\nNumber of CPUs = %d\n", ncpus);
205 for (i = 0; i < ncpus ; i++) {
206
207 printf("------------- CPU %d ----------------\n", i);
208 printf("SGX supported : %s\n",
209 is_sgx_supported(i) ? "YES" : "NO");
210 printf("SGX enabled : %s\n",
211 is_sgx_enabled(i) ? "YES" : "NO");
212 printf("Feature Control locked : %s\n",
213 is_sgx_locked(i) ? "YES" : "NO");
214 }
215 error = 0;
216 }
217 printf("====================================================\n");
218 #endif
219 return error;
220 }
221
222 int print_intel_core_msrs(void)
223 {
224 unsigned int i, core, id;
225 msr_t msr;
226
227 #define IA32_PLATFORM_ID 0x0017
228 #define EBL_CR_POWERON 0x002a
229 #define FSB_CLK_STS 0x00cd
230 #define IA32_TIME_STAMP_COUNTER 0x0010
231 #define IA32_APIC_BASE 0x001b
232
233 typedef struct {
234 int number;
235 char *name;
236 } msr_entry_t;
237
238 /* Pentium III */
239 static const msr_entry_t model67x_global_msrs[] = {
240 { 0x0000, "IA32_P5_MC_ADDR" },
241 { 0x0001, "IA32_P5_MC_TYPE" },
242 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
243 { 0x0017, "IA32_PLATFORM_ID" },
244 { 0x001b, "IA32_APIC_BASE" },
245 { 0x002a, "EBL_CR_POWERON" },
246 { 0x0033, "TEST_CTL" },
247 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
248 { 0x0088, "BBL_CR_D0" },
249 { 0x0089, "BBL_CR_D1" },
250 { 0x008a, "BBL_CR_D2" },
251 { 0x008b, "IA32_BIOS_SIGN_ID" },
252 { 0x00c1, "PERFCTR0" },
253 { 0x00c2, "PERFCTR1" },
254 { 0x00fe, "IA32_MTRRCAP" },
255 { 0x0116, "BBL_CR_ADDR" },
256 { 0x0118, "BBL_CR_DECC" },
257 { 0x0119, "BBL_CR_CTL" },
258 //{ 0x011a, "BBL_CR_TRIG" },
259 { 0x011b, "BBL_CR_BUSY" },
260 { 0x011e, "BBL_CR_CTL3" },
261 { 0x0174, "IA32_SYSENTER_CS" },
262 { 0x0175, "IA32_SYSENTER_ESP" },
263 { 0x0176, "IA32_SYSENTER_EIP" },
264 { 0x0179, "IA32_MCG_CAP" },
265 { 0x017a, "IA32_MCG_STATUS" },
266 { 0x017b, "IA32_MCG_CTL" },
267 { 0x0186, "IA32_PERF_EVNTSEL0" },
268 { 0x0187, "IA32_PERF_EVNTSEL1" },
269 { 0x01d9, "IA32_DEBUGCTL" },
270 { 0x01db, "MSR_LASTBRANCHFROMIP" },
271 { 0x01dc, "MSR_LASTBRANCHTOIP" },
272 { 0x01dd, "MSR_LASTINTFROMIP" },
273 { 0x01de, "MSR_LASTINTTOIP" },
274 { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" },
275 { 0x0200, "IA32_MTRR_PHYSBASE0" },
276 { 0x0201, "IA32_MTRR_PHYSMASK0" },
277 { 0x0202, "IA32_MTRR_PHYSBASE1" },
278 { 0x0203, "IA32_MTRR_PHYSMASK1" },
279 { 0x0204, "IA32_MTRR_PHYSBASE2" },
280 { 0x0205, "IA32_MTRR_PHYSMASK2" },
281 { 0x0206, "IA32_MTRR_PHYSBASE3" },
282 { 0x0207, "IA32_MTRR_PHYSMASK3" },
283 { 0x0208, "IA32_MTRR_PHYSBASE4" },
284 { 0x0209, "IA32_MTRR_PHYSMASK4" },
285 { 0x020a, "IA32_MTRR_PHYSBASE5" },
286 { 0x020b, "IA32_MTRR_PHYSMASK5" },
287 { 0x020c, "IA32_MTRR_PHYSBASE6" },
288 { 0x020d, "IA32_MTRR_PHYSMASK6" },
289 { 0x020e, "IA32_MTRR_PHYSBASE7" },
290 { 0x020f, "IA32_MTRR_PHYSMASK7" },
291 { 0x0250, "IA32_MTRR_FIX64K_00000" },
292 { 0x0258, "IA32_MTRR_FIX16K_80000" },
293 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
294 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
295 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
296 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
297 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
298 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
299 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
300 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
301 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
302 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
303 { 0x0400, "IA32_MC0_CTL" },
304 { 0x0401, "IA32_MC0_STATUS" },
305 { 0x0402, "IA32_MC0_ADDR" },
306 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
307 { 0x0404, "IA32_MC1_CTL" },
308 { 0x0405, "IA32_MC1_STATUS" },
309 { 0x0406, "IA32_MC1_ADDR" },
310 //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO
311 { 0x0408, "IA32_MC2_CTL" },
312 { 0x0409, "IA32_MC2_STATUS" },
313 { 0x040a, "IA32_MC2_ADDR" },
314 //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO
315 { 0x040c, "IA32_MC4_CTL" },
316 { 0x040d, "IA32_MC4_STATUS" },
317 { 0x040e, "IA32_MC4_ADDR" },
318 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
319 { 0x0410, "IA32_MC3_CTL" },
320 { 0x0411, "IA32_MC3_STATUS" },
321 { 0x0412, "IA32_MC3_ADDR" },
322 //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO
323 };
324
325 static const msr_entry_t model6bx_global_msrs[] = {
326 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
327 { 0x0017, "IA32_PLATFORM_ID" },
328 { 0x001b, "IA32_APIC_BASE" },
329 { 0x002a, "EBL_CR_POWERON" },
330 { 0x0033, "TEST_CTL" },
331 { 0x003f, "THERM_DIODE_OFFSET" },
332 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
333 { 0x008b, "IA32_BIOS_SIGN_ID" },
334 { 0x00c1, "PERFCTR0" },
335 { 0x00c2, "PERFCTR1" },
336 { 0x011e, "BBL_CR_CTL3" },
337 { 0x0179, "IA32_MCG_CAP" },
338 { 0x017a, "IA32_MCG_STATUS" },
339 { 0x0198, "IA32_PERF_STATUS" },
340 { 0x0199, "IA32_PERF_CONTROL" },
341 { 0x019a, "IA32_CLOCK_MODULATION" },
342 { 0x01a0, "IA32_MISC_ENABLES" },
343 { 0x01d9, "IA32_DEBUGCTL" },
344 { 0x0200, "IA32_MTRR_PHYSBASE0" },
345 { 0x0201, "IA32_MTRR_PHYSMASK0" },
346 { 0x0202, "IA32_MTRR_PHYSBASE1" },
347 { 0x0203, "IA32_MTRR_PHYSMASK1" },
348 { 0x0204, "IA32_MTRR_PHYSBASE2" },
349 { 0x0205, "IA32_MTRR_PHYSMASK2" },
350 { 0x0206, "IA32_MTRR_PHYSBASE3" },
351 { 0x0207, "IA32_MTRR_PHYSMASK3" },
352 { 0x0208, "IA32_MTRR_PHYSBASE4" },
353 { 0x0209, "IA32_MTRR_PHYSMASK4" },
354 { 0x020a, "IA32_MTRR_PHYSBASE5" },
355 { 0x020b, "IA32_MTRR_PHYSMASK5" },
356 { 0x020c, "IA32_MTRR_PHYSBASE6" },
357 { 0x020d, "IA32_MTRR_PHYSMASK6" },
358 { 0x020e, "IA32_MTRR_PHYSBASE7" },
359 { 0x020f, "IA32_MTRR_PHYSMASK7" },
360 { 0x0250, "IA32_MTRR_FIX64K_00000" },
361 { 0x0258, "IA32_MTRR_FIX16K_80000" },
362 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
363 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
364 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
365 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
366 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
367 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
368 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
369 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
370 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
371 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
372 { 0x0400, "IA32_MC0_CTL" },
373 { 0x0401, "IA32_MC0_STATUS" },
374 { 0x0402, "IA32_MC0_ADDR" },
375 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
376 { 0x040c, "IA32_MC4_CTL" },
377 { 0x040d, "IA32_MC4_STATUS" },
378 { 0x040e, "IA32_MC4_ADDR" },
379 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
380 };
381
382 static const msr_entry_t model6ex_global_msrs[] = {
383 { 0x0017, "IA32_PLATFORM_ID" },
384 { 0x002a, "EBL_CR_POWERON" },
385 { 0x00cd, "FSB_CLOCK_STS" },
386 { 0x00ce, "FSB_CLOCK_VCC" },
387 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
388 { 0x00e3, "PMG_IO_BASE_ADDR" },
389 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
390 { 0x00ee, "EXT_CONFIG" },
391 { 0x011e, "BBL_CR_CTL3" },
392 { 0x0194, "CLOCK_FLEX_MAX" },
393 { 0x0198, "IA32_PERF_STATUS" },
394 { 0x01a0, "IA32_MISC_ENABLES" },
395 { 0x01aa, "PIC_SENS_CFG" },
396 { 0x0400, "IA32_MC0_CTL" },
397 { 0x0401, "IA32_MC0_STATUS" },
398 { 0x0402, "IA32_MC0_ADDR" },
399 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
400 { 0x040c, "IA32_MC4_CTL" },
401 { 0x040d, "IA32_MC4_STATUS" },
402 { 0x040e, "IA32_MC4_ADDR" },
403 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
404 };
405
406 static const msr_entry_t model6ex_per_core_msrs[] = {
407 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
408 { 0x001b, "IA32_APIC_BASE" },
409 { 0x003a, "IA32_FEATURE_CONTROL" },
410 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
411 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
412 { 0x008b, "IA32_BIOS_SIGN_ID" },
413 { 0x00e7, "IA32_MPERF" },
414 { 0x00e8, "IA32_APERF" },
415 { 0x00fe, "IA32_MTRRCAP" },
416 { 0x015f, "DTS_CAL_CTRL" },
417 { 0x0179, "IA32_MCG_CAP" },
418 { 0x017a, "IA32_MCG_STATUS" },
419 { 0x0199, "IA32_PERF_CONTROL" },
420 { 0x019a, "IA32_CLOCK_MODULATION" },
421 { 0x019b, "IA32_THERM_INTERRUPT" },
422 { 0x019c, "IA32_THERM_STATUS" },
423 { 0x019d, "GV_THERM" },
424 { 0x01d9, "IA32_DEBUGCTL" },
425 { 0x0200, "IA32_MTRR_PHYSBASE0" },
426 { 0x0201, "IA32_MTRR_PHYSMASK0" },
427 { 0x0202, "IA32_MTRR_PHYSBASE1" },
428 { 0x0203, "IA32_MTRR_PHYSMASK1" },
429 { 0x0204, "IA32_MTRR_PHYSBASE2" },
430 { 0x0205, "IA32_MTRR_PHYSMASK2" },
431 { 0x0206, "IA32_MTRR_PHYSBASE3" },
432 { 0x0207, "IA32_MTRR_PHYSMASK3" },
433 { 0x0208, "IA32_MTRR_PHYSBASE4" },
434 { 0x0209, "IA32_MTRR_PHYSMASK4" },
435 { 0x020a, "IA32_MTRR_PHYSBASE5" },
436 { 0x020b, "IA32_MTRR_PHYSMASK5" },
437 { 0x020c, "IA32_MTRR_PHYSBASE6" },
438 { 0x020d, "IA32_MTRR_PHYSMASK6" },
439 { 0x020e, "IA32_MTRR_PHYSBASE7" },
440 { 0x020f, "IA32_MTRR_PHYSMASK7" },
441 { 0x0250, "IA32_MTRR_FIX64K_00000" },
442 { 0x0258, "IA32_MTRR_FIX16K_80000" },
443 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
444 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
445 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
446 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
447 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
448 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
449 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
450 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
451 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
452 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
453 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
454 };
455
456 static const msr_entry_t model6fx_global_msrs[] = {
457 { 0x0017, "IA32_PLATFORM_ID" },
458 { 0x002a, "EBL_CR_POWERON" },
459 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
460 { 0x00a8, "EMTTM_CR_TABLE0" },
461 { 0x00a9, "EMTTM_CR_TABLE1" },
462 { 0x00aa, "EMTTM_CR_TABLE2" },
463 { 0x00ab, "EMTTM_CR_TABLE3" },
464 { 0x00ac, "EMTTM_CR_TABLE4" },
465 { 0x00ad, "EMTTM_CR_TABLE5" },
466 { 0x00cd, "FSB_CLOCK_STS" },
467 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
468 { 0x00e3, "PMG_IO_BASE_ADDR" },
469 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
470 { 0x00ee, "EXT_CONFIG" },
471 { 0x011e, "BBL_CR_CTL3" },
472 { 0x0194, "CLOCK_FLEX_MAX" },
473 { 0x0198, "IA32_PERF_STATUS" },
474 { 0x01a0, "IA32_MISC_ENABLES" },
475 { 0x01aa, "PIC_SENS_CFG" },
476 { 0x0400, "IA32_MC0_CTL" },
477 { 0x0401, "IA32_MC0_STATUS" },
478 { 0x0402, "IA32_MC0_ADDR" },
479 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
480 { 0x040c, "IA32_MC4_CTL" },
481 { 0x040d, "IA32_MC4_STATUS" },
482 { 0x040e, "IA32_MC4_ADDR" },
483 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
484 };
485
486 static const msr_entry_t model6fx_per_core_msrs[] = {
487 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
488 { 0x001b, "IA32_APIC_BASE" },
489 { 0x003a, "IA32_FEATURE_CONTROL" },
490 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
491 { 0x008b, "IA32_BIOS_SIGN_ID" },
492 { 0x00e1, "SMM_CST_MISC_INFO" },
493 { 0x00e7, "IA32_MPERF" },
494 { 0x00e8, "IA32_APERF" },
495 { 0x00fe, "IA32_MTRRCAP" },
496 { 0x0179, "IA32_MCG_CAP" },
497 { 0x017a, "IA32_MCG_STATUS" },
498 { 0x0199, "IA32_PERF_CONTROL" },
499 { 0x019a, "IA32_THERM_CTL" },
500 { 0x019b, "IA32_THERM_INTERRUPT" },
501 { 0x019c, "IA32_THERM_STATUS" },
502 { 0x019d, "MSR_THERM2_CTL" },
503 { 0x01d9, "IA32_DEBUGCTL" },
504 { 0x0200, "IA32_MTRR_PHYSBASE0" },
505 { 0x0201, "IA32_MTRR_PHYSMASK0" },
506 { 0x0202, "IA32_MTRR_PHYSBASE1" },
507 { 0x0203, "IA32_MTRR_PHYSMASK1" },
508 { 0x0204, "IA32_MTRR_PHYSBASE2" },
509 { 0x0205, "IA32_MTRR_PHYSMASK2" },
510 { 0x0206, "IA32_MTRR_PHYSBASE3" },
511 { 0x0207, "IA32_MTRR_PHYSMASK3" },
512 { 0x0208, "IA32_MTRR_PHYSBASE4" },
513 { 0x0209, "IA32_MTRR_PHYSMASK4" },
514 { 0x020a, "IA32_MTRR_PHYSBASE5" },
515 { 0x020b, "IA32_MTRR_PHYSMASK5" },
516 { 0x020c, "IA32_MTRR_PHYSBASE6" },
517 { 0x020d, "IA32_MTRR_PHYSMASK6" },
518 { 0x020e, "IA32_MTRR_PHYSBASE7" },
519 { 0x020f, "IA32_MTRR_PHYSMASK7" },
520 { 0x0250, "IA32_MTRR_FIX64K_00000" },
521 { 0x0258, "IA32_MTRR_FIX16K_80000" },
522 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
523 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
524 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
525 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
526 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
527 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
528 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
529 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
530 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
531 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
532 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
533 };
534
535 /* Pentium 4 and XEON */
536 /*
537 * All MSRs per
538 *
539 * Intel 64 and IA-32 Architectures Software Developer's Manual
540 * Volume 3B: System Programming Guide, Part 2
541 *
542 * Table B-5, B-7
543 */
544 static const msr_entry_t modelf2x_global_msrs[] = {
545 { 0x0000, "IA32_P5_MC_ADDR" },
546 { 0x0001, "IA32_P5_MC_TYPE" },
547 /* 0x6: Not available in model 2. */
548 { 0x0017, "IA32_PLATFORM_ID" },
549 { 0x002a, "MSR_EBC_HARD_POWERON" },
550 { 0x002b, "MSR_EBC_SOFT_POWERON" },
551 /* 0x2c: Not available in model 2. */
552 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
553 { 0x019c, "IA32_THERM_STATUS" },
554 /* 0x19d: Not available in model 2. */
555 { 0x01a0, "IA32_MISC_ENABLE" },
556 /* 0x1a1: Not available in model 2. */
557 { 0x0200, "IA32_MTRR_PHYSBASE0" },
558 { 0x0201, "IA32_MTRR_PHYSMASK0" },
559 { 0x0202, "IA32_MTRR_PHYSBASE1" },
560 { 0x0203, "IA32_MTRR_PHYSMASK1" },
561 { 0x0204, "IA32_MTRR_PHYSBASE2" },
562 { 0x0205, "IA32_MTRR_PHYSMASK2" },
563 { 0x0206, "IA32_MTRR_PHYSBASE3" },
564 { 0x0207, "IA32_MTRR_PHYSMASK3" },
565 { 0x0208, "IA32_MTRR_PHYSBASE4" },
566 { 0x0209, "IA32_MTRR_PHYSMASK4" },
567 { 0x020a, "IA32_MTRR_PHYSBASE5" },
568 { 0x020b, "IA32_MTRR_PHYSMASK5" },
569 { 0x020c, "IA32_MTRR_PHYSBASE6" },
570 { 0x020d, "IA32_MTRR_PHYSMASK6" },
571 { 0x020e, "IA32_MTRR_PHYSBASE7" },
572 { 0x020f, "IA32_MTRR_PHYSMASK7" },
573 { 0x0250, "IA32_MTRR_FIX64K_00000" },
574 { 0x0258, "IA32_MTRR_FIX16K_80000" },
575 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
576 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
577 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
578 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
579 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
580 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
581 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
582 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
583 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
584 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
585 { 0x0300, "MSR_BPU_COUNTER0" },
586 { 0x0301, "MSR_BPU_COUNTER1" },
587 { 0x0302, "MSR_BPU_COUNTER2" },
588 { 0x0303, "MSR_BPU_COUNTER3" },
589 { 0x0304, "MSR_MS_COUNTER0" },
590 { 0x0305, "MSR_MS_COUNTER1" },
591 { 0x0306, "MSR_MS_COUNTER2" },
592 { 0x0307, "MSR_MS_COUNTER3" },
593 { 0x0308, "MSR_FLAME_COUNTER0" },
594 { 0x0309, "MSR_FLAME_COUNTER1" },
595 { 0x030a, "MSR_FLAME_COUNTER2" },
596 { 0x030b, "MSR_FLAME_COUNTER3" },
597 { 0x030c, "MSR_IQ_COUNTER0" },
598 { 0x030d, "MSR_IQ_COUNTER1" },
599 { 0x030e, "MSR_IQ_COUNTER2" },
600 { 0x030f, "MSR_IQ_COUNTER3" },
601 { 0x0310, "MSR_IQ_COUNTER4" },
602 { 0x0311, "MSR_IQ_COUNTER5" },
603 { 0x0360, "MSR_BPU_CCCR0" },
604 { 0x0361, "MSR_BPU_CCCR1" },
605 { 0x0362, "MSR_BPU_CCCR2" },
606 { 0x0363, "MSR_BPU_CCCR3" },
607 { 0x0364, "MSR_MS_CCCR0" },
608 { 0x0365, "MSR_MS_CCCR1" },
609 { 0x0366, "MSR_MS_CCCR2" },
610 { 0x0367, "MSR_MS_CCCR3" },
611 { 0x0368, "MSR_FLAME_CCCR0" },
612 { 0x0369, "MSR_FLAME_CCCR1" },
613 { 0x036a, "MSR_FLAME_CCCR2" },
614 { 0x036b, "MSR_FLAME_CCCR3" },
615 { 0x036c, "MSR_IQ_CCCR0" },
616 { 0x036d, "MSR_IQ_CCCR1" },
617 { 0x036e, "MSR_IQ_CCCR2" },
618 { 0x036f, "MSR_IQ_CCCR3" },
619 { 0x0370, "MSR_IQ_CCCR4" },
620 { 0x0371, "MSR_IQ_CCCR5" },
621 { 0x03a0, "MSR_BSU_ESCR0" },
622 { 0x03a1, "MSR_BSU_ESCR1" },
623 { 0x03a2, "MSR_FSB_ESCR0" },
624 { 0x03a3, "MSR_FSB_ESCR1" },
625 { 0x03a4, "MSR_FIRM_ESCR0" },
626 { 0x03a5, "MSR_FIRM_ESCR1" },
627 { 0x03a6, "MSR_FLAME_ESCR0" },
628 { 0x03a7, "MSR_FLAME_ESCR1" },
629 { 0x03a8, "MSR_DAC_ESCR0" },
630 { 0x03a9, "MSR_DAC_ESCR1" },
631 { 0x03aa, "MSR_MOB_ESCR0" },
632 { 0x03ab, "MSR_MOB_ESCR1" },
633 { 0x03ac, "MSR_PMH_ESCR0" },
634 { 0x03ad, "MSR_PMH_ESCR1" },
635 { 0x03ae, "MSR_SAAT_ESCR0" },
636 { 0x03af, "MSR_SAAT_ESCR1" },
637 { 0x03b0, "MSR_U2L_ESCR0" },
638 { 0x03b1, "MSR_U2L_ESCR1" },
639 { 0x03b2, "MSR_BPU_ESCR0" },
640 { 0x03b3, "MSR_BPU_ESCR1" },
641 { 0x03b4, "MSR_IS_ESCR0" },
642 { 0x03b5, "MSR_BPU_ESCR1" },
643 { 0x03b6, "MSR_ITLB_ESCR0" },
644 { 0x03b7, "MSR_ITLB_ESCR1" },
645 { 0x03b8, "MSR_CRU_ESCR0" },
646 { 0x03b9, "MSR_CRU_ESCR1" },
647 { 0x03ba, "MSR_IQ_ESCR0" },
648 { 0x03bb, "MSR_IQ_ESCR1" },
649 { 0x03bc, "MSR_RAT_ESCR0" },
650 { 0x03bd, "MSR_RAT_ESCR1" },
651 { 0x03be, "MSR_SSU_ESCR0" },
652 { 0x03c0, "MSR_MS_ESCR0" },
653 { 0x03c1, "MSR_MS_ESCR1" },
654 { 0x03c2, "MSR_TBPU_ESCR0" },
655 { 0x03c3, "MSR_TBPU_ESCR1" },
656 { 0x03c4, "MSR_TC_ESCR0" },
657 { 0x03c5, "MSR_TC_ESCR1" },
658 { 0x03c8, "MSR_IX_ESCR0" },
659 { 0x03c9, "MSR_IX_ESCR1" },
660 { 0x03ca, "MSR_ALF_ESCR0" },
661 { 0x03cb, "MSR_ALF_ESCR1" },
662 { 0x03cc, "MSR_CRU_ESCR2" },
663 { 0x03cd, "MSR_CRU_ESCR3" },
664 { 0x03e0, "MSR_CRU_ESCR4" },
665 { 0x03e1, "MSR_CRU_ESCR5" },
666 { 0x03f0, "MSR_TC_PRECISE_EVENT" },
667 { 0x03f1, "MSR_PEBS_ENABLE" },
668 { 0x03f2, "MSR_PEBS_MATRIX_VERT" },
669
670 /*
671 * All MCX_ADDR and MCX_MISC MSRs depend on a bit being
672 * set in MCX_STATUS.
673 */
674 { 0x400, "IA32_MC0_CTL" },
675 { 0x401, "IA32_MC0_STATUS" },
676 { 0x402, "IA32_MC0_ADDR" },
677 { 0x403, "IA32_MC0_MISC" },
678 { 0x404, "IA32_MC1_CTL" },
679 { 0x405, "IA32_MC1_STATUS" },
680 { 0x406, "IA32_MC1_ADDR" },
681 { 0x407, "IA32_MC1_MISC" },
682 { 0x408, "IA32_MC2_CTL" },
683 { 0x409, "IA32_MC2_STATUS" },
684 { 0x40a, "IA32_MC2_ADDR" },
685 { 0x40b, "IA32_MC2_MISC" },
686 { 0x40c, "IA32_MC3_CTL" },
687 { 0x40d, "IA32_MC3_STATUS" },
688 { 0x40e, "IA32_MC3_ADDR" },
689 { 0x40f, "IA32_MC3_MISC" },
690 { 0x410, "IA32_MC4_CTL" },
691 { 0x411, "IA32_MC4_STATUS" },
692 { 0x412, "IA32_MC4_ADDR" },
693 { 0x413, "IA32_MC4_MISC" },
694 };
695
696 static const msr_entry_t modelf2x_per_core_msrs[] = {
697 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
698 { 0x001b, "IA32_APIC_BASE" },
699 /* 0x3a: Not available in model 2. */
700 { 0x008b, "IA32_BIOS_SIGN_ID" },
701 /* 0x9b: Not available in model 2. */
702 { 0x00fe, "IA32_MTRRCAP" },
703 { 0x0174, "IA32_SYSENTER_CS" },
704 { 0x0175, "IA32_SYSENTER_ESP" },
705 { 0x0176, "IA32_SYSENTER_EIP" },
706 { 0x0179, "IA32_MCG_CAP" },
707 { 0x017a, "IA32_MCG_STATUS" },
708 { 0x017b, "IA32_MCG_CTL" },
709 { 0x0180, "MSR_MCG_RAX" },
710 { 0x0181, "MSR_MCG_RBX" },
711 { 0x0182, "MSR_MCG_RCX" },
712 { 0x0183, "MSR_MCG_RDX" },
713 { 0x0184, "MSR_MCG_RSI" },
714 { 0x0185, "MSR_MCG_RDI" },
715 { 0x0186, "MSR_MCG_RBP" },
716 { 0x0187, "MSR_MCG_RSP" },
717 { 0x0188, "MSR_MCG_RFLAGS" },
718 { 0x0189, "MSR_MCG_RIP" },
719 { 0x018a, "MSR_MCG_MISC" },
720 /* 0x18b-0x18f: Reserved */
721 { 0x0190, "MSR_MCG_R8" },
722 { 0x0191, "MSR_MCG_R9" },
723 { 0x0192, "MSR_MCG_R10" },
724 { 0x0193, "MSR_MCG_R11" },
725 { 0x0194, "MSR_MCG_R12" },
726 { 0x0195, "MSR_MCG_R13" },
727 { 0x0196, "MSR_MCG_R14" },
728 { 0x0197, "MSR_MCG_R15" },
729 /* 0x198: Not available in model 2. */
730 /* 0x199: Not available in model 2. */
731 { 0x019a, "IA32_CLOCK_MODULATION" },
732 { 0x019b, "IA32_THERM_INTERRUPT" },
733 { 0x01a0, "IA32_MISC_ENABLE" },
734 { 0x01d7, "MSR_LER_FROM_LIP" },
735 { 0x01d8, "MSR_LER_TO_LIP" },
736 { 0x01d9, "MSR_DEBUGCTLA" },
737 { 0x01da, "MSR_LASTBRANCH_TOS" },
738 { 0x01db, "MSR_LASTBRANCH_0" },
739 { 0x01dd, "MSR_LASTBRANCH_2" },
740 { 0x01de, "MSR_LASTBRANCH_3" },
741 { 0x0277, "IA32_PAT" },
742 /* 0x480-0x48b : Not available in model 2. */
743 { 0x0600, "IA32_DS_AREA" },
744 /* 0x0680 - 0x06cf Branch Records Skipped */
745 };
746
747 static const msr_entry_t modelf4x_global_msrs[] = {
748 { 0x0000, "IA32_P5_MC_ADDR" },
749 { 0x0001, "IA32_P5_MC_TYPE" },
750 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
751 { 0x0017, "IA32_PLATFORM_ID" },
752 { 0x002a, "MSR_EBC_HARD_POWERON" },
753 { 0x002b, "MSR_EBC_SOFT_POWERON" },
754 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
755 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
756 { 0x019c, "IA32_THERM_STATUS" },
757 { 0x019d, "MSR_THERM2_CTL" },
758 { 0x01a0, "IA32_MISC_ENABLE" },
759 { 0x01a1, "MSR_PLATFORM_BRV" },
760 { 0x0200, "IA32_MTRR_PHYSBASE0" },
761 { 0x0201, "IA32_MTRR_PHYSMASK0" },
762 { 0x0202, "IA32_MTRR_PHYSBASE1" },
763 { 0x0203, "IA32_MTRR_PHYSMASK1" },
764 { 0x0204, "IA32_MTRR_PHYSBASE2" },
765 { 0x0205, "IA32_MTRR_PHYSMASK2" },
766 { 0x0206, "IA32_MTRR_PHYSBASE3" },
767 { 0x0207, "IA32_MTRR_PHYSMASK3" },
768 { 0x0208, "IA32_MTRR_PHYSBASE4" },
769 { 0x0209, "IA32_MTRR_PHYSMASK4" },
770 { 0x020a, "IA32_MTRR_PHYSBASE5" },
771 { 0x020b, "IA32_MTRR_PHYSMASK5" },
772 { 0x020c, "IA32_MTRR_PHYSBASE6" },
773 { 0x020d, "IA32_MTRR_PHYSMASK6" },
774 { 0x020e, "IA32_MTRR_PHYSBASE7" },
775 { 0x020f, "IA32_MTRR_PHYSMASK7" },
776 { 0x0250, "IA32_MTRR_FIX64K_00000" },
777 { 0x0258, "IA32_MTRR_FIX16K_80000" },
778 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
779 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
780 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
781 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
782 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
783 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
784 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
785 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
786 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
787 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
788 { 0x0300, "MSR_BPU_COUNTER0" },
789 { 0x0301, "MSR_BPU_COUNTER1" },
790 { 0x0302, "MSR_BPU_COUNTER2" },
791 { 0x0303, "MSR_BPU_COUNTER3" },
792 /* Skipped through 0x3ff for now*/
793
794 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
795 * set in MCX_STATUS */
796 { 0x400, "IA32_MC0_CTL" },
797 { 0x401, "IA32_MC0_STATUS" },
798 { 0x402, "IA32_MC0_ADDR" },
799 { 0x403, "IA32_MC0_MISC" },
800 { 0x404, "IA32_MC1_CTL" },
801 { 0x405, "IA32_MC1_STATUS" },
802 { 0x406, "IA32_MC1_ADDR" },
803 { 0x407, "IA32_MC1_MISC" },
804 { 0x408, "IA32_MC2_CTL" },
805 { 0x409, "IA32_MC2_STATUS" },
806 { 0x40a, "IA32_MC2_ADDR" },
807 { 0x40b, "IA32_MC2_MISC" },
808 { 0x40c, "IA32_MC3_CTL" },
809 { 0x40d, "IA32_MC3_STATUS" },
810 { 0x40e, "IA32_MC3_ADDR" },
811 { 0x40f, "IA32_MC3_MISC" },
812 { 0x410, "IA32_MC4_CTL" },
813 { 0x411, "IA32_MC4_STATUS" },
814 { 0x412, "IA32_MC4_ADDR" },
815 { 0x413, "IA32_MC4_MISC" },
816 };
817
818 static const msr_entry_t modelf4x_per_core_msrs[] = {
819 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
820 { 0x001b, "IA32_APIC_BASE" },
821 { 0x003a, "IA32_FEATURE_CONTROL" },
822 { 0x008b, "IA32_BIOS_SIGN_ID" },
823 { 0x009b, "IA32_SMM_MONITOR_CTL" },
824 { 0x00fe, "IA32_MTRRCAP" },
825 { 0x0174, "IA32_SYSENTER_CS" },
826 { 0x0175, "IA32_SYSENTER_ESP" },
827 { 0x0176, "IA32_SYSENTER_EIP" },
828 { 0x0179, "IA32_MCG_CAP" },
829 { 0x017a, "IA32_MCG_STATUS" },
830 { 0x0180, "MSR_MCG_RAX" },
831 { 0x0181, "MSR_MCG_RBX" },
832 { 0x0182, "MSR_MCG_RCX" },
833 { 0x0183, "MSR_MCG_RDX" },
834 { 0x0184, "MSR_MCG_RSI" },
835 { 0x0185, "MSR_MCG_RDI" },
836 { 0x0186, "MSR_MCG_RBP" },
837 { 0x0187, "MSR_MCG_RSP" },
838 { 0x0188, "MSR_MCG_RFLAGS" },
839 { 0x0189, "MSR_MCG_RIP" },
840 { 0x018a, "MSR_MCG_MISC" },
841 // 0x18b-f Reserved
842 { 0x0190, "MSR_MCG_R8" },
843 { 0x0191, "MSR_MCG_R9" },
844 { 0x0192, "MSR_MCG_R10" },
845 { 0x0193, "MSR_MCG_R11" },
846 { 0x0194, "MSR_MCG_R12" },
847 { 0x0195, "MSR_MCG_R13" },
848 { 0x0196, "MSR_MCG_R14" },
849 { 0x0197, "MSR_MCG_R15" },
850 { 0x0198, "IA32_PERF_STATUS" },
851 { 0x0199, "IA32_PERF_CTL" },
852 { 0x019a, "IA32_CLOCK_MODULATION" },
853 { 0x019b, "IA32_THERM_INTERRUPT" },
854 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
855 { 0x01d7, "MSR_LER_FROM_LIP" },
856 { 0x01d8, "MSR_LER_TO_LIP" },
857 { 0x01d9, "MSR_DEBUGCTLA" },
858 { 0x01da, "MSR_LASTBRANCH_TOS" },
859 { 0x0277, "IA32_PAT" },
860 /** Virtualization
861 { 0x480, "IA32_VMX_BASIC" },
862 through
863 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
864 Not implemented in my CPU
865 */
866 { 0x0600, "IA32_DS_AREA" },
867 /* 0x0680 - 0x06cf Branch Records Skipped */
868
869 };
870
871 /*
872 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual
873 * September 2016
874 */
875 static const msr_entry_t modelf6x_global_msrs[] = {
876 { 0x0000, "IA32_P5_MC_ADDR" },
877 { 0x0001, "IA32_P5_MC_TYPE" },
878 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
879 { 0x0017, "IA32_PLATFORM_ID" },
880 { 0x002a, "MSR_EBC_HARD_POWERON" },
881 { 0x002b, "MSR_EBC_SOFT_POWERON" },
882 { 0x002c, "MSR_EBC_FREQUENCY_ID" },
883 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
884 { 0x019c, "IA32_THERM_STATUS" },
885 { 0x019d, "MSR_THERM2_CTL" },
886 { 0x01a0, "IA32_MISC_ENABLE" },
887 { 0x01a1, "MSR_PLATFORM_BRV" },
888 { 0x0200, "IA32_MTRR_PHYSBASE0" },
889 { 0x0201, "IA32_MTRR_PHYSMASK0" },
890 { 0x0202, "IA32_MTRR_PHYSBASE1" },
891 { 0x0203, "IA32_MTRR_PHYSMASK1" },
892 { 0x0204, "IA32_MTRR_PHYSBASE2" },
893 { 0x0205, "IA32_MTRR_PHYSMASK2" },
894 { 0x0206, "IA32_MTRR_PHYSBASE3" },
895 { 0x0207, "IA32_MTRR_PHYSMASK3" },
896 { 0x0208, "IA32_MTRR_PHYSBASE4" },
897 { 0x0209, "IA32_MTRR_PHYSMASK4" },
898 { 0x020a, "IA32_MTRR_PHYSBASE5" },
899 { 0x020b, "IA32_MTRR_PHYSMASK5" },
900 { 0x020c, "IA32_MTRR_PHYSBASE6" },
901 { 0x020d, "IA32_MTRR_PHYSMASK6" },
902 { 0x020e, "IA32_MTRR_PHYSBASE7" },
903 { 0x020f, "IA32_MTRR_PHYSMASK7" },
904 { 0x0250, "IA32_MTRR_FIX64K_00000" },
905 { 0x0258, "IA32_MTRR_FIX16K_80000" },
906 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
907 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
908 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
909 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
910 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
911 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
912 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
913 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
914 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
915 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
916 { 0x0300, "MSR_BPU_COUNTER0" },
917 { 0x0301, "MSR_BPU_COUNTER1" },
918 { 0x0302, "MSR_BPU_COUNTER2" },
919 { 0x0303, "MSR_BPU_COUNTER3" },
920 { 0x0304, "MSR_MS_COUNTER0" },
921 { 0x0305, "MSR_MS_COUNTER1" },
922 { 0x0306, "MSR_MS_COUNTER2" },
923 { 0x0307, "MSR_MS_COUNTER3" },
924 { 0x0308, "MSR_FLAME_COUNTER0" },
925 { 0x0309, "MSR_FLAME_COUNTER1" },
926 { 0x030a, "MSR_FLAME_COUNTER2" },
927 { 0x030b, "MSR_FLAME_COUNTER3" },
928 { 0x030c, "MSR_IQ_COUNTER0" },
929 { 0x030d, "MSR_IQ_COUNTER1" },
930 { 0x030e, "MSR_IQ_COUNTER2" },
931 { 0x030f, "MSR_IQ_COUNTER3" },
932 { 0x0310, "MSR_IQ_COUNTER4" },
933 { 0x0311, "MSR_IQ_COUNTER5" },
934 { 0x0360, "MSR_BPU_CCCR0" },
935 { 0x0361, "MSR_BPU_CCCR1" },
936 { 0x0362, "MSR_BPU_CCCR2" },
937 { 0x0363, "MSR_BPU_CCCR3" },
938 { 0x0364, "MSR_MS_CCCR0" },
939 { 0x0365, "MSR_MS_CCCR1" },
940 { 0x0366, "MSR_MS_CCCR2" },
941 { 0x0367, "MSR_MS_CCCR3" },
942 { 0x0368, "MSR_FLAME_CCCR0" },
943 { 0x0369, "MSR_FLAME_CCCR1" },
944 { 0x036A, "MSR_FLAME_CCCR2" },
945 { 0x036B, "MSR_FLAME_CCCR3" },
946 { 0x036C, "MSR_IQ_CCCR0" },
947 { 0x036D, "MSR_IQ_CCCR1" },
948 { 0x036E, "MSR_IQ_CCCR2" },
949 { 0x036F, "MSR_IQ_CCCR3" },
950 { 0x0370, "MSR_IQ_CCCR4" },
951 { 0x0371, "MSR_IQ_CCCR5" },
952 { 0x03A0, "MSR_BSU_ESCR0" },
953 { 0x03A1, "MSR_BSU_ESCR1" },
954 { 0x03A2, "MSR_FSB_ESCR0" },
955 { 0x03A3, "MSR_FSB_ESCR1" },
956 { 0x03A4, "MSR_FIRM_ESCR0" },
957 { 0x03A5, "MSR_FIRM_ESCR1" },
958 { 0x03A6, "MSR_FLAME_ESCR0" },
959 { 0x03A7, "MSR_FLAME_ESCR1" },
960 { 0x03A8, "MSR_DAC_ESCR0" },
961 { 0x03A9, "MSR_DAC_ESCR1" },
962 { 0x03AA, "MSR_MOB_ESCR0" },
963 { 0x03AB, "MSR_MOB_ESCR1" },
964 { 0x03AC, "MSR_PMH_ESCR0" },
965 { 0x03AD, "MSR_PMH_ESCR1" },
966 { 0x03AE, "MSR_SAAT_ESCR0" },
967 { 0x03AF, "MSR_SAAT_ESCR1" },
968 { 0x03B0, "MSR_U2L_ESCR0" },
969 { 0x03B1, "MSR_U2L_ESCR1" },
970 { 0x03B2, "MSR_BPU_ESCR0" },
971 { 0x03B3, "MSR_BPU_ESCR1" },
972 { 0x03B4, "MSR_IS_ESCR0" },
973 { 0x03B5, "MSR_IS_ESCR1" },
974 { 0x03B6, "MSR_ITLB_ESCR0" },
975 { 0x03B7, "MSR_ITLB_ESCR1" },
976 { 0x03B8, "MSR_CRU_ESCR0" },
977 { 0x03B9, "MSR_CRU_ESCR1" },
978 { 0x03BA, "MSR_IQ_ESCR0" },
979 { 0x03BB, "MSR_IQ_ESCR1" },
980 { 0x03BC, "MSR_RAT_ESCR0" },
981 { 0x03BD, "MSR_RAT_ESCR1" },
982 { 0x03BE, "MSR_SSU_ESCR0" },
983 { 0x03C0, "MSR_MS_ESCR0" },
984 { 0x03C1, "MSR_MS_ESCR1" },
985 { 0x03C2, "MSR_TBPU_ESCR0" },
986 { 0x03C3, "MSR_TBPU_ESCR1" },
987 { 0x03C4, "MSR_TC_ESCR0" },
988 { 0x03C5, "MSR_TC_ESCR1" },
989 { 0x03C8, "MSR_IX_ESCR0" },
990 { 0x03C9, "MSR_IX_ESCR1" },
991 { 0x03CA, "MSR_ALF_ESCR0" },
992 { 0x03CB, "MSR_ALF_ESCR1" },
993 { 0x03CC, "MSR_CRU_ESCR2" },
994 { 0x03CD, "MSR_CRU_ESCR3" },
995 { 0x03E0, "MSR_CRU_ESCR4" },
996 { 0x03E1, "MSR_CRU_ESCR5" },
997 { 0x03F0, "MSR_TC_PRECISE_EVENT" },
998 { 0x03F1, "MSR_PEBS_ENABLE" },
999 { 0x03F2, "MSR_PEBS_MATRIX_VERT" },
1000 { 0x0400, "IA32_MC0_CTL" },
1001 { 0x0401, "IA32_MC0_STATUS" },
1002 { 0x0402, "IA32_MC0_ADDR" },
1003 { 0x0403, "IA32_MC0_MISC" },
1004 { 0x0404, "IA32_MC1_CTL" },
1005 { 0x0405, "IA32_MC1_STATUS" },
1006 { 0x0406, "IA32_MC1_ADDR" },
1007 { 0x0408, "IA32_MC2_CTL" },
1008 { 0x0409, "IA32_MC2_STATUS" },
1009 { 0x040b, "IA32_MC2_MISC" },
1010 { 0x040c, "IA32_MC3_CTL" },
1011 { 0x040d, "IA32_MC3_STATUS" },
1012 { 0x040e, "IA32_MC3_ADDR" },
1013 { 0x040f, "IA32_MC3_MISC" },
1014 };
1015
1016 static const msr_entry_t modelf6x_per_core_msrs[] = {
1017 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1018 { 0x001b, "IA32_APIC_BASE" },
1019 { 0x008b, "IA32_BIOS_SIGN_ID" },
1020 { 0x00fe, "IA32_MTRRCAP" },
1021 { 0x0174, "IA32_SYSENTER_CS" },
1022 { 0x0175, "IA32_SYSENTER_ESP" },
1023 { 0x0176, "IA32_SYSENTER_EIP" },
1024 { 0x0179, "IA32_MCG_CAP" },
1025 { 0x017a, "IA32_MCG_STATUS" },
1026 { 0x0180, "MSR_MCG_RAX" },
1027 { 0x0181, "MSR_MCG_RBX" },
1028 { 0x0182, "MSR_MCG_RCX" },
1029 { 0x0183, "MSR_MCG_RDX" },
1030 { 0x0184, "MSR_MCG_RSI" },
1031 { 0x0185, "MSR_MCG_RDI" },
1032 { 0x0186, "MSR_MCG_RBP" },
1033 { 0x0187, "MSR_MCG_RSP" },
1034 { 0x0188, "MSR_MCG_RFLAGS" },
1035 { 0x0189, "MSR_MCG_RIP" },
1036 { 0x018a, "MSR_MCG_MISC" },
1037 { 0x0190, "MSR_MCG_R8" },
1038 { 0x0191, "MSR_MCG_R9" },
1039 { 0x0192, "MSR_MCG_R10" },
1040 { 0x0193, "MSR_MCG_R11" },
1041 { 0x0194, "MSR_MCG_R12" },
1042 { 0x0195, "MSR_MCG_R13" },
1043 { 0x0196, "MSR_MCG_R14" },
1044 { 0x0197, "MSR_MCG_R15" },
1045 { 0x0198, "IA32_PERF_STATUS" },
1046 { 0x0199, "IA32_PERF_CTL" },
1047 { 0x019a, "IA32_CLOCK_MODULATION" },
1048 { 0x019b, "IA32_THERM_INTERRUPT" },
1049 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1050 { 0x01d7, "MSR_LER_FROM_LIP" },
1051 { 0x01d8, "MSR_LER_TO_LIP" },
1052 { 0x01d9, "MSR_DEBUGCTLA" },
1053 { 0x01da, "MSR_LASTBRANCH_TOS" },
1054 { 0x0277, "IA32_PAT" },
1055 { 0x0600, "IA32_DS_AREA" },
1056 { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
1057 { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
1058 { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
1059 { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
1060 { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
1061 { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
1062 { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
1063 { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
1064 { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
1065 { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
1066 { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
1067 { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
1068 { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
1069 { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
1070 { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
1071 { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
1072 { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
1073 { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
1074 { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
1075 { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
1076 { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
1077 { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
1078 { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
1079 { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
1080 { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
1081 { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
1082 { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
1083 { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
1084 { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
1085 { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
1086 { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
1087 { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
1088 /* Intel Xeon processor 7100 with L3 */
1089 // { 0x107CC, "MSR_EMON_L3_CTR_CTL0" },
1090 // { 0x107CD, "MSR_EMON_L3_CTR_CTL1" },
1091 // { 0x107CE, "MSR_EMON_L3_CTR_CTL2" },
1092 // { 0x107CF, "MSR_EMON_L3_CTR_CTL3" },
1093 // { 0x107D0, "MSR_EMON_L3_CTR_CTL4" },
1094 // { 0x107D1, "MSR_EMON_L3_CTR_CTL5" },
1095 // { 0x107D2, "MSR_EMON_L3_CTR_CTL6" },
1096 // { 0x107D3, "MSR_EMON_L3_CTR_CTL7" },
1097 };
1098
1099 /* Atom N455
1100 *
1101 * This should apply to the following processors:
1102 * 06_1CH
1103 * 06_26H
1104 * 06_27H
1105 * 06_35
1106 * 06_36
1107 */
1108 /*
1109 * All MSRs per
1110 *
1111 * Intel 64 and IA-32 Architectures Software Developer's Manual
1112 * Volume 3C: System Programming Guide, Part 3
1113 * Order Number 326019
1114 * January 2013
1115 *
1116 * Table 35-4, 35-5
1117 *
1118 * For now it has only been tested with 06_1CH.
1119 */
1120 static const msr_entry_t model6_atom_global_msrs[] = {
1121 { 0x0000, "IA32_P5_MC_ADDR" },
1122 { 0x0001, "IA32_P5_MC_TYPE" },
1123 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1124 { 0x0017, "IA32_PLATFORM_ID" },
1125 { 0x002a, "MSR_EBC_HARD_POWERON" },
1126 { 0x00cd, "MSR_FSB_FREQ" },
1127 { 0x00fe, "IA32_MTRRCAP" },
1128 { 0x011e, "MSR_BBL_CR_CTL3" },
1129 { 0x0198, "IA32_PERF_STATUS" },
1130 { 0x019d, "MSR_THERM2_CTL" },
1131 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1132 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1133 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1134 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1135 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1136 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1137 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1138 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1139 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1140 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1141 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1142 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1143 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1144 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1145 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1146 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1147 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1148 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1149 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1150 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1151 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1152 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1153 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1154 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1155 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1156 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1157 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1158 { 0x0345, "IA32_PERF_CAPABILITIES" },
1159 { 0x400, "IA32_MC0_CTL" },
1160 { 0x401, "IA32_MC0_STATUS" },
1161 { 0x402, "IA32_MC0_ADDR" },
1162 { 0x404, "IA32_MC1_CTL" },
1163 { 0x405, "IA32_MC1_STATUS" },
1164 { 0x408, "IA32_MC2_CTL" },
1165 { 0x409, "IA32_MC2_STATUS" },
1166 { 0x40a, "IA32_MC2_ADDR" },
1167 { 0x40c, "IA32_MC3_CTL" },
1168 { 0x40d, "IA32_MC3_STATUS" },
1169 { 0x40e, "IA32_MC3_ADDR" },
1170 { 0x410, "IA32_MC4_CTL" },
1171 { 0x411, "IA32_MC4_STATUS" },
1172 { 0x412, "IA32_MC4_ADDR" },
1173 /*
1174 * Only 06_27C has the following MSRs
1175 */
1176 /*
1177 { 0x03f8, "MSR_PKG_C2_RESIDENCY" },
1178 { 0x03f9, "MSR_PKG_C4_RESIDENCY" },
1179 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1180 */
1181 };
1182
1183 static const msr_entry_t model6_atom_per_core_msrs[] = {
1184 { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
1185 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1186 { 0x001b, "IA32_APIC_BASE" },
1187 { 0x003a, "IA32_FEATURE_CONTROL" },
1188 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1189 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1190 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1191 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1192 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1193 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1194 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1195 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1196 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1197 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1198 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1199 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1200 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1201 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1202 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1203 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1204 /* Write register */
1205 /*
1206 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1207 */
1208 { 0x008b, "IA32_BIOS_SIGN_ID" },
1209 { 0x00c1, "IA32_PMC0" },
1210 { 0x00c2, "IA32_PMC1" },
1211 { 0x00e7, "IA32_MPERF" },
1212 { 0x00e8, "IA32_APERF" },
1213 { 0x0174, "IA32_SYSENTER_CS" },
1214 { 0x0175, "IA32_SYSENTER_ESP" },
1215 { 0x0176, "IA32_SYSENTER_EIP" },
1216 { 0x017a, "IA32_MCG_STATUS" },
1217 { 0x0186, "IA32_PERF_EVNTSEL0" },
1218 { 0x0187, "IA32_PERF_EVNTSEL1" },
1219 { 0x0199, "IA32_PERF_CONTROL" },
1220 { 0x019a, "IA32_CLOCK_MODULATION" },
1221 { 0x019b, "IA32_THERM_INTERRUPT" },
1222 { 0x019c, "IA32_THERM_STATUS" },
1223 { 0x01a0, "IA32_MISC_ENABLES" },
1224 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1225 { 0x01d9, "IA32_DEBUGCTL" },
1226 { 0x01dd, "MSR_LER_FROM_LIP" },
1227 { 0x01de, "MSR_LER_TO_LIP" },
1228 { 0x0277, "IA32_PAT" },
1229 { 0x0309, "IA32_FIXED_CTR0" },
1230 { 0x030a, "IA32_FIXED_CTR1" },
1231 { 0x030b, "IA32_FIXED_CTR2" },
1232 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1233 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1234 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1235 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1236 { 0x03f1, "MSR_PEBS_ENABLE" },
1237 { 0x0480, "IA32_VMX_BASIC" },
1238 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1239 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1240 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1241 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1242 { 0x0485, "IA32_VMX_MISC" },
1243 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1244 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1245 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1246 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1247 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1248 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1249 { 0x0600, "IA32_DS_AREA" },
1250 };
1251
1252 static const msr_entry_t model20650_global_msrs[] = {
1253 { 0x0000, "IA32_P5_MC_ADDR" },
1254 { 0x0001, "IA32_P5_MC_TYPE" },
1255 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1256 { 0x0017, "IA32_PLATFORM_ID" },
1257 { 0x002a, "MSR_EBC_HARD_POWERON" },
1258 // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1259 { 0x00ce, "IA32_MSR_PLATFORM_INFO" },
1260 { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
1261 { 0x019c, "IA32_THERM_STATUS" },
1262 { 0x019d, "MSR_THERM2_CTL" },
1263 { 0x01a0, "IA32_MISC_ENABLE" },
1264 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1265 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1266 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1267 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1268 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1269 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1270 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1271 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1272 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1273 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1274 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1275 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1276 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1277 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1278 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1279 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1280 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1281 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1282 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1283 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1284 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1285 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1286 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1287 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1288 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1289 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1290 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1291 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
1292 { 0x0300, "MSR_BPU_COUNTER0" },
1293 { 0x0301, "MSR_BPU_COUNTER1" },
1294 /* Skipped through 0x3ff for now*/
1295
1296 /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
1297 * set in MCX_STATUS */
1298 { 0x400, "IA32_MC0_CTL" },
1299 { 0x401, "IA32_MC0_STATUS" },
1300 { 0x402, "IA32_MC0_ADDR" },
1301 { 0x403, "IA32_MC0_MISC" },
1302 { 0x404, "IA32_MC1_CTL" },
1303 { 0x405, "IA32_MC1_STATUS" },
1304 { 0x406, "IA32_MC1_ADDR" },
1305 { 0x407, "IA32_MC1_MISC" },
1306 { 0x408, "IA32_MC2_CTL" },
1307 { 0x409, "IA32_MC2_STATUS" },
1308 { 0x40a, "IA32_MC2_ADDR" },
1309 { 0x40c, "IA32_MC3_CTL" },
1310 { 0x40d, "IA32_MC3_STATUS" },
1311 { 0x40e, "IA32_MC3_ADDR" },
1312 { 0x410, "IA32_MC4_CTL" },
1313 { 0x411, "IA32_MC4_STATUS" },
1314 };
1315
1316 static const msr_entry_t model20650_per_core_msrs[] = {
1317 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1318 { 0x001b, "IA32_APIC_BASE" },
1319 { 0x003a, "IA32_FEATURE_CONTROL" },
1320 { 0x008b, "IA32_BIOS_SIGN_ID" },
1321 { 0x009b, "IA32_SMM_MONITOR_CTL" },
1322 { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
1323 { 0x00fe, "IA32_MTRRCAP" },
1324 { 0x0174, "IA32_SYSENTER_CS" },
1325 { 0x0175, "IA32_SYSENTER_ESP" },
1326 { 0x0176, "IA32_SYSENTER_EIP" },
1327 { 0x0179, "IA32_MCG_CAP" },
1328 { 0x017a, "IA32_MCG_STATUS" },
1329 { 0x0186, "MSR_MCG_RBP" },
1330 { 0x0187, "MSR_MCG_RSP" },
1331 { 0x0188, "MSR_MCG_RFLAGS" },
1332 { 0x0189, "MSR_MCG_RIP" },
1333 { 0x0194, "MSR_MCG_R12" },
1334 { 0x0198, "IA32_PERF_STATUS" },
1335 { 0x0199, "IA32_PERF_CTL" },
1336 { 0x019a, "IA32_CLOCK_MODULATION" },
1337 { 0x019b, "IA32_THERM_INTERRUPT" },
1338 { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
1339 { 0x01aa, "IA32_MISC_PWR_MGMT" },
1340 { 0x01d9, "MSR_DEBUGCTLA" },
1341 { 0x01fc, "MSR_POWER_CTL" },
1342 { 0x0277, "IA32_PAT" },
1343 /** Virtualization
1344 { 0x480, "IA32_VMX_BASIC" },
1345 through
1346 { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
1347 Not implemented in my CPU
1348 */
1349 { 0x0600, "IA32_DS_AREA" },
1350 /* 0x0680 - 0x06cf Branch Records Skipped */
1351
1352 { 0x3a, "IA32_FEATURE_CONTROL" },
1353 { 0x13c, "MSR_FEATURE_CONFIG" },
1354 { 0x194, "MSR_FLEX_RATIO" },
1355 { 0x1a0, "IA32_MISC_ENABLE" },
1356 { 0x1a2, "MSR_TEMPERATURE_TARGET" },
1357 { 0x199, "IA32_PERF_CTL" },
1358 { 0x19b, "IA32_THERM_INTERRUPT" },
1359 { 0x401, "IA32_MC0_STATUS" },
1360 { 0x2e, "MSR_PIC_MSG_CONTROL" },
1361 { 0xce, "MSR_PLATFORM_INFO" },
1362 { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
1363 { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
1364 { 0x1aa, "MSR_MISC_PWR_MGMT" },
1365 { 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
1366 { 0x1fc, "MSR_POWER_CTL" },
1367 };
1368
1369 /*
1370 * The following two tables are the Silvermont registers listed in Table 35-6
1371 * Intel® 64 and IA-32 Architectures Software Developer's Manual
1372 * September 2014
1373 * Vol. 3C 35-59
1374 */
1375 static const msr_entry_t silvermont_per_core_msrs[] = {
1376 /*
1377 * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
1378 * These are MSRs marked as "core"
1379 *
1380 */
1381 { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
1382 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
1383 { 0x001b, "IA32_APIC_BASE" },
1384 { 0x0034, "MSR_SMI_COUNT" },
1385 { 0x003a, "IA32_FEATURE_CONTROL" },
1386 { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
1387 { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
1388 { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
1389 { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
1390 { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
1391 { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
1392 { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
1393 { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
1394 { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
1395 { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
1396 { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
1397 { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
1398 { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
1399 { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
1400 { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
1401 { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
1402 /* Write register
1403 { 0x0079, "IA32_BIOS_UPDT_TRIG" },
1404 */
1405 { 0x008b, "IA32_BIOS_SIGN_ID" },
1406 { 0x00c1, "IA32_PMC0" },
1407 { 0x00c2, "IA32_PMC1" },
1408 { 0x00e7, "IA32_MPERF" },
1409 { 0x00e8, "IA32_APERF" },
1410 { 0x00fe, "IA32_MTRRCAP" },
1411 { 0x0174, "IA32_SYSENTER_CS" },
1412 { 0x0175, "IA32_SYSENTER_ESP" },
1413 { 0x0176, "IA32_SYSENTER_EIP" },
1414 { 0x0179, "IA32_MCG_CAP" },
1415 { 0x017a, "IA32_MCG_STATUS" },
1416 { 0x0186, "IA32_PERF_EVNTSEL0" },
1417 { 0x0187, "IA32_PERF_EVNTSEL1" },
1418 { 0x0199, "IA32_PERF_CONTROL" },
1419 { 0x019a, "IA32_CLOCK_MODULATION" },
1420 { 0x019b, "IA32_THERM_INTERRUPT" },
1421 { 0x019c, "IA32_THERM_STATUS" },
1422 { 0x01a0, "IA32_MISC_ENABLES" },
1423 { 0x01b0, "IA32_ENERGY_PERF_BIAS" },
1424 { 0x01c9, "MSR_LASTBRANCH_TOS" },
1425 { 0x01d9, "IA32_DEBUGCTL" },
1426 { 0x01dd, "MSR_LER_FROM_LIP" },
1427 { 0x01de, "MSR_LER_TO_LIP" },
1428 { 0x01f2, "IA32_SMRR_PHYSBASE" },
1429 { 0x01f3, "IA32_SMRR_PHYSMASK" },
1430 { 0x0200, "IA32_MTRR_PHYSBASE0" },
1431 { 0x0201, "IA32_MTRR_PHYSMASK0" },
1432 { 0x0202, "IA32_MTRR_PHYSBASE1" },
1433 { 0x0203, "IA32_MTRR_PHYSMASK1" },
1434 { 0x0204, "IA32_MTRR_PHYSBASE2" },
1435 { 0x0205, "IA32_MTRR_PHYSMASK2" },
1436 { 0x0206, "IA32_MTRR_PHYSBASE3" },
1437 { 0x0207, "IA32_MTRR_PHYSMASK3" },
1438 { 0x0208, "IA32_MTRR_PHYSBASE4" },
1439 { 0x0209, "IA32_MTRR_PHYSMASK4" },
1440 { 0x020a, "IA32_MTRR_PHYSBASE5" },
1441 { 0x020b, "IA32_MTRR_PHYSMASK5" },
1442 { 0x020c, "IA32_MTRR_PHYSBASE6" },
1443 { 0x020d, "IA32_MTRR_PHYSMASK6" },
1444 { 0x020e, "IA32_MTRR_PHYSBASE7" },
1445 { 0x020f, "IA32_MTRR_PHYSMASK7" },
1446 { 0x0250, "IA32_MTRR_FIX64K_00000" },
1447 { 0x0258, "IA32_MTRR_FIX16K_80000" },
1448 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
1449 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
1450 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
1451 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
1452 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
1453 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
1454 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
1455 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
1456 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
1457 { 0x0277, "IA32_PAT" },
1458 { 0x02FF, "IA32_MTRR_DEF_TYPE" },
1459 { 0x0309, "IA32_FIXED_CTR0" },
1460 { 0x030a, "IA32_FIXED_CTR1" },
1461 { 0x030b, "IA32_FIXED_CTR2" },
1462 { 0x0345, "IA32_PERF_CAPABILITIES" },
1463 { 0x038d, "IA32_FIXED_CTR_CTRL" },
1464 { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
1465 { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
1466 { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
1467 { 0x03f1, "MSR_PEBS_ENABLE" },
1468 { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
1469 { 0x40c, "IA32_MC3_CTL" },
1470 { 0x40d, "IA32_MC3_STATUS" },
1471 { 0x40e, "IA32_MC3_ADDR" },
1472 { 0x410, "IA32_MC4_CTL" },
1473 { 0x411, "IA32_MC4_STATUS" },
1474 { 0x412, "IA32_MC4_ADDR" },
1475 { 0x0480, "IA32_VMX_BASIC" },
1476 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1477 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1478 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1479 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1480 { 0x0485, "IA32_VMX_MISC" },
1481 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1482 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1483 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1484 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1485 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1486 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1487 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1488 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1489 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1490 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1491 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1492 { 0x0491, "IA32_VMX_FMFUNC" },
1493 { 0x04c1, "IA32_A_PMC0" },
1494 { 0x04c2, "IA32_A_PMC1" },
1495 { 0x0600, "IA32_DS_AREA" },
1496 { 0x0660, "MSR_CORE_C1_RESIDENCY" },
1497 { 0x06e0, "IA32_TSC_DEADLINE" },
1498 };
1499
1500 static const msr_entry_t silvermont_global_msrs[] = {
1501 /*
1502 * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
1503 * These are MSRs marked as "shared" or "package"
1504 */
1505 { 0x0000, "IA32_P5_MC_ADDR" },
1506 { 0x0001, "IA32_P5_MC_TYPE" },
1507 { 0x0017, "IA32_PLATFORM_ID" },
1508 { 0x002a, "MSR_EBC_HARD_POWERON" },
1509 { 0x00cd, "MSR_FSB_FREQ" },
1510 { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
1511 { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
1512 { 0x011e, "BBL_CR_CTL3" },
1513 { 0x0198, "IA32_PERF_STATUS" },
1514 { 0x01A2, "MSR_TEMPERATURE_TARGET" },
1515 { 0x01A6, "MSR_OFFCORE_RSP_0" },
1516 { 0x01A7, "MSR_OFFCORE_RSP_1" },
1517 { 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
1518 { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
1519 { 0x400, "IA32_MC0_CTL" },
1520 { 0x401, "IA32_MC0_STATUS" },
1521 { 0x402, "IA32_MC0_ADDR" },
1522 { 0x404, "IA32_MC1_CTL" },
1523 { 0x405, "IA32_MC1_STATUS" },
1524 { 0x408, "IA32_MC2_CTL" },
1525 { 0x409, "IA32_MC2_STATUS" },
1526 { 0x40a, "IA32_MC2_ADDR" },
1527 { 0x414, "MSR_MC5_CTL" },
1528 { 0x415, "MSR_MC5_STATUS" },
1529 { 0x416, "MSR_MC5_ADDR" },
1530 };
1531
1532 /*
1533 * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes
1534 * Page 4668
1535 *
1536 * The following two tables are for the Kaby Lake processors
1537 * 06_9EH.
1538 *
1539 */
1540
1541 static const msr_entry_t model96ex_global_msrs[] = {
1542 { 0x0000, "IA32_PLATFORM_ID"},
1543 { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"},
1544 { 0x00CE, "MSR_PLATFORM_INFO"},
1545 { 0x0198, "IA32_PERF_STATUS"},
1546 { 0x01A2, "MSR_TEMPERATURE_TARGET"},
1547 { 0x01AD, "MSR_TURBO_RATIO_LIMIT"},
1548 { 0x0284, "IA32_MC4_CTL2"},
1549 { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"},
1550 { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"},
1551 { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"},
1552 { 0x0395, "MSR_UNC_PERF_FIXED_CTR"},
1553 { 0x060A, "MSR_PKGC3_IRTL"},
1554 { 0x060B, "MSR_PKGC6_IRTL"},
1555 { 0x060D, "MSR_PKG_C2_RESIDENCY"},
1556 { 0x0610, "MSR_PKG_POWER_LIMIT"},
1557 { 0x0614, "MSR_PKG_POWER_INFO"},
1558 { 0x0620, "MSR_RING_RATIO_LIMIT"},
1559 { 0x0638, "MSR_PP0_POWER_LIMIT"},
1560 { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"},
1561 { 0x0652, "MSR_PKG_HDC_CONFIG"},
1562 { 0x065C, "MSR_PLATFORM_POWER_LIMIT"},
1563 { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"},
1564 { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"},
1565 { 0x0770, "IA32_PM_ENABLE"},
1566 { 0x0DB0, "IA32_PKG_HDC_CTL"},
1567 { 0x03B0, "MSR_UNC_ARB_PERFCTR0"},
1568 { 0x03B1, "MSR_UNC_ARB_PERFCTR1"},
1569 { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"},
1570 { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"},
1571 { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"},
1572 { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"},
1573 { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"},
1574 { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"},
1575 { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"},
1576 { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"},
1577 { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"},
1578 { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"},
1579 { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"},
1580 { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"},
1581 { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"},
1582 { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"},
1583 { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"},
1584 { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"},
1585 { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"},
1586 { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"},
1587 { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"},
1588 { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"},
1589 };
1590
1591 static const msr_entry_t model96ex_per_core_msrs[] = {
1592 /* Per core MSRs for Sandy Bridge and above */
1593 { 0x0000, "IA32_P5_MC_ADDR"},
1594 { 0x0001, "IA32_P5_MC_TYPE"},
1595 { 0x0006, "IA32_MONITOR_FILTER_SIZE"},
1596 { 0x0010, "IA32_TIME_STAMP_COUNTER"},
1597 { 0x001B, "IA32_APIC_BASE"},
1598 { 0x0034, "MSR_SMI_COUNT"},
1599 { 0x003A, "IA32_FEATURE_CONTROL"},
1600 { 0x008B, "IA32_BIOS_SIGN_ID"},
1601 { 0x00C1, "IA32_PMC0" },
1602 { 0x00C2, "IA32_PMC1" },
1603 { 0x00C3, "IA32_PMC2" },
1604 { 0x00C4, "IA32_PMC3" },
1605 { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" },
1606 { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"},
1607 { 0x00E7, "IA32_MPERF"},
1608 { 0x00E8, "IA32_APERF"},
1609 { 0x00FE, "IA32_MTRRCAP"},
1610 { 0x013C, "MSR_FEATURE_CONFIG"},
1611 { 0x0174, "IA32_SYSENTER_CS"},
1612 { 0x0175, "IA32_SYSENTER_ESP"},
1613 { 0x0176, "IA32_SYSENTER_EIP"},
1614 { 0x0179, "IA32_MCG_CAP"},
1615 { 0x017A, "IA32_MCG_STATUS"},
1616 { 0x0186, "IA32_PERFEVTSEL0"},
1617 { 0x0187, "IA32_PERFEVTSEL1"},
1618 { 0x0188, "IA32_PERFEVTSEL2"},
1619 { 0x0189, "IA32_PERFEVTSEL3"},
1620 { 0x0199, "IA32_PERF_CTL"},
1621 { 0x019A, "IA32_CLOCK_MODULATION"},
1622 { 0x019B, "IA32_THERM_INTERRUPT"},
1623 { 0x019C, "IA32_THERM_STATUS"},
1624 { 0x01A0, "IA32_MISC_ENABLE"},
1625 { 0x01A4, "IA32_MISC_FEATURE_CONTROL"},
1626 { 0x01A6, "MSR_OFFCORE_RSP_0"},
1627 { 0x01A7, "MSR_OFFCORE_RSP_1"},
1628 { 0x01C8, "MSR_LBR_SELECT"},
1629 { 0x01C9, "MSR_LASTBRANCH_TOS"},
1630 { 0x01D9, "IA32_DEBUGCTL"},
1631 { 0x01DD, "MSR_LER_FROM_LIP"},
1632 { 0x01DE, "MSR_LER_TO_LIP"},
1633 { 0x01F2, "IA32_SMRR_PHYSBASE"},
1634 { 0x01F3, "IA32_SMRR_PHYSMASK"},
1635 { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
1636 { 0x01F5, "MSR_PRMRR_PHYS_MASK"},
1637 { 0x01F4, "MSR_PRMRR_PHYS_BASE"},
1638 { 0x01FB, "MSR_PRMRR_VALID_CONFIG"},
1639 { 0x01FC, "MSR_POWER_CTL"},
1640 { 0x0200, "IA32_MTRR_PHYSBASE0"},
1641 { 0x0201, "IA32_MTRR_PHYSBASE0"},
1642 { 0x0202, "IA32_MTRR_PHYSBASE1"},
1643 { 0x0203, "IA32_MTRR_PHYSBASE1"},
1644 { 0x0204, "IA32_MTRR_PHYSBASE2"},
1645 { 0x0205, "IA32_MTRR_PHYSBASE2"},
1646 { 0x0206, "IA32_MTRR_PHYSBASE3"},
1647 { 0x0207, "IA32_MTRR_PHYSBASE3"},
1648 { 0x0208, "IA32_MTRR_PHYSBASE4"},
1649 { 0x0209, "IA32_MTRR_PHYSBASE4"},
1650 { 0x020A, "IA32_MTRR_PHYSBASE5"},
1651 { 0x020B, "IA32_MTRR_PHYSBASE5"},
1652 { 0x020C, "IA32_MTRR_PHYSBASE6"},
1653 { 0x020D, "IA32_MTRR_PHYSBASE6"},
1654 { 0x020E, "IA32_MTRR_PHYSBASE7"},
1655 { 0x020F, "IA32_MTRR_PHYSBASE7"},
1656 { 0x0210, "IA32_MTRR_PHYSBASE8"},
1657 { 0x0211, "IA32_MTRR_PHYSBASE8"},
1658 { 0x0212, "IA32_MTRR_PHYSBASE9"},
1659 { 0x0213, "IA32_MTRR_PHYSBASE9"},
1660 { 0x0250, "IA32_MTRR_FIX64K_00000"},
1661 { 0x0258, "IA32_MTRR_FIX16K_80000"},
1662 { 0x0259, "IA32_MTRR_FIX16K_A0000"},
1663 { 0x0268, "IA32_MTRR_FIX4K_C0000"},
1664 { 0x0269, "IA32_MTRR_FIX4K_C8000"},
1665 { 0x026A, "IA32_MTRR_FIX4K_D0000"},
1666 { 0x026B, "IA32_MTRR_FIX4K_D8000"},
1667 { 0x026C, "IA32_MTRR_FIX4K_E0000"},
1668 { 0x026D, "IA32_MTRR_FIX4K_E8000"},
1669 { 0x026E, "IA32_MTRR_FIX4K_F0000"},
1670 { 0x026F, "IA32_MTRR_FIX4K_F8000"},
1671 { 0x0277, "IA32_PAT"},
1672 { 0x0280, "IA32_MC0_CTL2"},
1673 { 0x0281, "IA32_MC1_CTL2"},
1674 { 0x0282, "IA32_MC2_CTL2"},
1675 { 0x0283, "IA32_MC3_CTL2"},
1676 { 0x02FF, "IA32_MTRR_DEF_TYPE"},
1677 { 0x0309, "IA32_FIXED_CTR0"},
1678 { 0x030A, "IA32_FIXED_CTR1"},
1679 { 0x030B, "IA32_FIXED_CTR2"},
1680 { 0x0345, "IA32_PERF_CAPABILITIES"},
1681 { 0x038D, "IA32_FIXED_CTR_CTRL"},
1682 { 0x038E, "IA32_PERF_GLOBAL_STATUS"},
1683 { 0x038F, "IA32_PERF_GLOBAL_CTRL"},
1684 { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"},
1685 { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"},
1686 { 0x03F1, "MSR_PEBS_ENABLE"},
1687 { 0x03F6, "MSR_PEBS_LD_LAT"},
1688 { 0x03F7, "MSR_PEBS_FRONTEND"},
1689 { 0x03FC, "MSR_CORE_C3_RESIDENCY"},
1690 { 0x03FD, "MSR_CORE_C6_RESIDENCY"},
1691 { 0x03FE, "MSR_CORE_C7_RESIDENCY"},
1692 { 0x0400, "IA32_MC0_CTL" },
1693 { 0x0401, "IA32_MC0_STATUS" },
1694 { 0x0402, "IA32_MC0_ADDR" },
1695 { 0x0403, "IA32_MC0_MISC" },
1696 { 0x0404, "IA32_MC1_CTL" },
1697 { 0x0405, "IA32_MC1_STATUS" },
1698 { 0x0406, "IA32_MC1_ADDR" },
1699 { 0x0407, "IA32_MC1_MISC" },
1700 { 0x0408, "IA32_MC2_CTL" },
1701 { 0x0409, "IA32_MC2_STATUS" },
1702 { 0x040a, "IA32_MC2_ADDR" },
1703 { 0x040c, "IA32_MC3_CTL" },
1704 { 0x040d, "IA32_MC3_STATUS" },
1705 { 0x040e, "IA32_MC3_ADDR" },
1706 { 0x0410, "IA32_MC4_CTL" },
1707 { 0x0411, "IA32_MC4_STATUS" },
1708 { 0x0480, "IA32_VMX_BASIC" },
1709 { 0x0481, "IA32_VMX_PINBASED_CTLS" },
1710 { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
1711 { 0x0483, "IA32_VMX_EXIT_CTLS" },
1712 { 0x0484, "IA32_VMX_ENTRY_CTLS" },
1713 { 0x0485, "IA32_VMX_MISC" },
1714 { 0x0486, "IA32_VMX_CR0_FIXED0" },
1715 { 0x0487, "IA32_VMX_CR0_FIXED1" },
1716 { 0x0488, "IA32_VMX_CR4_FIXED0" },
1717 { 0x0489, "IA32_VMX_CR4_FIXED1" },
1718 { 0x048a, "IA32_VMX_VMCS_ENUM" },
1719 { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
1720 { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
1721 { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
1722 { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
1723 { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
1724 { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
1725 { 0x04C1, "IA32_A_PMC0"},
1726 { 0x04C2, "IA32_A_PMC1"},
1727 { 0x04C3, "IA32_A_PMC2"},
1728 { 0x04C4, "IA32_A_PMC3"},
1729 { 0x0500, "IA32_SGX_SVN_STATUS"},
1730 { 0x0560, "IA32_RTIT_OUTPUT_BASE"},
1731 { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"},
1732 { 0x0570, "IA32_RTIT_CTL"},
1733 { 0x0571, "IA32_RTIT_STATUS"},
1734 { 0x0572, "IA32_RTIT_CR3_MATCH"},
1735 { 0x0580, "IA32_RTIT_ADDR0_A"},
1736 { 0x0581, "IA32_RTIT_ADDR0_B"},
1737 { 0x0582, "IA32_RTIT_ADDR1_A"},
1738 { 0x0583, "IA32_RTIT_ADDR1_B"},
1739 { 0x0600, "IA32_DS_AREA" },
1740 { 0x064E, "MSR_PPERF"},
1741 { 0x0653, "MSR_CORE_HDC_RESIDENCY"},
1742 { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" },
1743 { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" },
1744 { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" },
1745 { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" },
1746 { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" },
1747 { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" },
1748 { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" },
1749 { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" },
1750 { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" },
1751 { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" },
1752 { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" },
1753 { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" },
1754 { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" },
1755 { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" },
1756 { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" },
1757 { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" },
1758 { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" },
1759 { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" },
1760 { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" },
1761 { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" },
1762 { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" },
1763 { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" },
1764 { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" },
1765 { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" },
1766 { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" },
1767 { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" },
1768 { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" },
1769 { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" },
1770 { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" },
1771 { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" },
1772 { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" },
1773 { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" },
1774 { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" },
1775 { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" },
1776 { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" },
1777 { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" },
1778 { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" },
1779 { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" },
1780 { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" },
1781 { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" },
1782 { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" },
1783 { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" },
1784 { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" },
1785 { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" },
1786 { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" },
1787 { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" },
1788 { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" },
1789 { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" },
1790 { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" },
1791 { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" },
1792 { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" },
1793 { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" },
1794 { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" },
1795 { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" },
1796 { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" },
1797 { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" },
1798 { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" },
1799 { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" },
1800 { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" },
1801 { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" },
1802 { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" },
1803 { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" },
1804 { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" },
1805 { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" },
1806 { 0x06E0, "IA32_TSC_DEADLINE"},
1807 { 0x0771, "IA32_HWP_CAPABILITIES"},
1808 { 0x0773, "IA32_HWP_INTERRUPT"},
1809 { 0x0774, "IA32_HWP_REQUEST"},
1810 { 0x0777, "IA32_HWP_STATUS"},
1811 { 0x0D90, "IA32_BNDCFGS"},
1812 { 0x0DA0, "IA32_XSS"},
1813 { 0x0DB1, "IA32_PM_CTL1"},
1814 { 0x0DB2, "IA32_THREAD_STALL"},
1815 { 0x0DC0, "IA32_LBR_INFO_0"},
1816 { 0x0DC1, "IA32_LBR_INFO_1"},
1817 { 0x0DC2, "IA32_LBR_INFO_2"},
1818 { 0x0DC3, "IA32_LBR_INFO_3"},
1819 { 0x0DC4, "IA32_LBR_INFO_4"},
1820 { 0x0DC5, "IA32_LBR_INFO_5"},
1821 { 0x0DC6, "IA32_LBR_INFO_6"},
1822 { 0x0DC7, "IA32_LBR_INFO_7"},
1823 { 0x0DC8, "IA32_LBR_INFO_8"},
1824 { 0x0DC9, "IA32_LBR_INFO_9"},
1825 { 0x0DCA, "IA32_LBR_INFO_10"},
1826 { 0x0DCB, "IA32_LBR_INFO_11"},
1827 { 0x0DCC, "IA32_LBR_INFO_12"},
1828 { 0x0DCD, "IA32_LBR_INFO_13"},
1829 { 0x0DCE, "IA32_LBR_INFO_14"},
1830 { 0x0DCF, "IA32_LBR_INFO_15"},
1831 { 0x0DD0, "IA32_LBR_INFO_16"},
1832 { 0x0DD1, "IA32_LBR_INFO_17"},
1833 { 0x0DD2, "IA32_LBR_INFO_18"},
1834 { 0x0DD3, "IA32_LBR_INFO_19"},
1835 { 0x0DD4, "IA32_LBR_INFO_20"},
1836 { 0x0DD5, "IA32_LBR_INFO_21"},
1837 { 0x0DD6, "IA32_LBR_INFO_22"},
1838 { 0x0DD7, "IA32_LBR_INFO_23"},
1839 { 0x0DD8, "IA32_LBR_INFO_24"},
1840 { 0x0DD9, "IA32_LBR_INFO_25"},
1841 { 0x0DDA, "IA32_LBR_INFO_26"},
1842 { 0x0DDB, "IA32_LBR_INFO_27"},
1843 { 0x0DDC, "IA32_LBR_INFO_28"},
1844 { 0x0DDD, "IA32_LBR_INFO_29"},
1845 { 0x0DDE, "IA32_LBR_INFO_30"},
1846 { 0x0DDF, "IA32_LBR_INFO_31"},
1847 };
1848
1849 typedef struct {
1850 unsigned int model;
1851 const msr_entry_t *global_msrs;
1852 unsigned int num_global_msrs;
1853 const msr_entry_t *per_core_msrs;
1854 unsigned int num_per_core_msrs;
1855 } cpu_t;
1856
1857 cpu_t cpulist[] = {
1858 { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
1859 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
1860 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
1861 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
1862 { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
1863 { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
1864 { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) },
1865 { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
1866 { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
1867 { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) },
1868
1869 { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
1870
1871 };
1872
1873 cpu_t *cpu = NULL;
1874
1875 /* Get CPU family and model, not the stepping
1876 * (TODO: extended family/model)
1877 */
1878 id = cpuid(1) & 0xfffff0;
1879 for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
1880 if(cpulist[i].model == id) {
1881 cpu = &cpulist[i];
1882 break;
1883 }
1884 }
1885
1886 if (!cpu) {
1887 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
1888 return -1;
1889 }
1890
1891 #ifndef __DARWIN__
1892 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
1893 if (fd_msr < 0) {
1894 perror("Error while opening /dev/cpu/0/msr");
1895 printf("Did you run 'modprobe msr'?\n");
1896 return -1;
1897 }
1898 #endif
1899
1900 printf("\n===================== SHARED MSRs (All Cores) =====================\n");
1901
1902 for (i = 0; i < cpu->num_global_msrs; i++) {
1903 msr = rdmsr(cpu->global_msrs[i].number);
1904 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
1905 cpu->global_msrs[i].number, msr.hi, msr.lo,
1906 cpu->global_msrs[i].name);
1907 }
1908
1909 close(fd_msr);
1910
1911 for (core = 0; core < 8; core++) {
1912 #ifndef __DARWIN__
1913 char msrfilename[64];
1914 memset(msrfilename, 0, 64);
1915 sprintf(msrfilename, "/dev/cpu/%u/msr", core);
1916
1917 fd_msr = open(msrfilename, O_RDWR);
1918
1919 /* If the file is not there, we're probably through. No error,
1920 * since we successfully opened /dev/cpu/0/msr before.
1921 */
1922 if (fd_msr < 0)
1923 break;
1924 #endif
1925 if (cpu->num_per_core_msrs)
1926 printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core);
1927
1928 for (i = 0; i < cpu->num_per_core_msrs; i++) {
1929 msr = rdmsr(cpu->per_core_msrs[i].number);
1930 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
1931 cpu->per_core_msrs[i].number, msr.hi, msr.lo,
1932 cpu->per_core_msrs[i].name);
1933 }
1934 #ifndef __DARWIN__
1935 close(fd_msr);
1936 #endif
1937 }
1938
1939 #ifndef __DARWIN__
1940 if (msr_readerror)
1941 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");
1942 #endif
1943 return 0;
1944 }
ast, secure and flexible OpenSource firmware