4 * Copyright (C) 2014 Google Inc.
5 * Copyright (C) 2015 Intel Corporation.
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8 * modification, are permitted provided that the following conditions are met:
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10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of Google Inc. nor the
15 * names of its contributors may be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #define PEI_VERSION 22
37 #define ABI_X86 __attribute__((regparm(0)))
39 typedef void ABI_X86(*tx_byte_func
)(unsigned char byte
);
46 /* Console output function */
50 * DIMM SPD data for memory down configurations
51 * [CHANNEL][SLOT][SPD]
53 uint8_t spd_data
[2][2][512];
57 * [CHANNEL][ITERATION][2]
59 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
60 * DQByteMap[0] - ClkDQByteMap:
61 * - If clock is per rank, program to [0xFF, 0xFF]
62 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
63 * - If clock is shared by 2 ranks but does not go to all bytes,
64 * Entry[i] defines which DQ bytes Group i services
65 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
66 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
67 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
68 * For DDR, DQByteMap[3:1] = [0xFF, 0]
69 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
70 * since we have 1 CTL / rank
71 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
72 * since we have 1 CA Vref
74 uint8_t dq_map
[2][12];
77 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
78 * [CHANNEL][MAX_BYTES]
80 uint8_t dqs_map
[2][8];
81 uint16_t RcompResistor
[3];
82 uint16_t RcompTarget
[5];
87 typedef struct pei_data PEI_DATA
;
89 #endif /* _PEI_DATA_H_ */