1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pci.h>
4 #include <device/pci_def.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_type.h>
9 void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge
)
12 reg16
= pci_s_read_config16(p2p_bridge
, PCI_BRIDGE_CONTROL
);
13 reg16
|= PCI_BRIDGE_CTL_BUS_RESET
;
14 pci_s_write_config16(p2p_bridge
, PCI_BRIDGE_CONTROL
, reg16
);
17 void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge
)
20 reg16
= pci_s_read_config16(p2p_bridge
, PCI_BRIDGE_CONTROL
);
21 reg16
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
22 pci_s_write_config16(p2p_bridge
, PCI_BRIDGE_CONTROL
, reg16
);
25 void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge
, u8 secondary
)
27 /* Disable config transaction forwarding. */
28 pci_s_write_config8(p2p_bridge
, PCI_SECONDARY_BUS
, 0x00);
29 pci_s_write_config8(p2p_bridge
, PCI_SUBORDINATE_BUS
, 0x00);
30 /* Enable config transaction forwarding. */
31 pci_s_write_config8(p2p_bridge
, PCI_SECONDARY_BUS
, secondary
);
32 pci_s_write_config8(p2p_bridge
, PCI_SUBORDINATE_BUS
, secondary
);
35 static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge
, u32 base
, u32 size
)
39 /* Disable MMIO window behind the bridge. */
40 reg16
= pci_s_read_config16(p2p_bridge
, PCI_COMMAND
);
41 reg16
&= ~PCI_COMMAND_MEMORY
;
42 pci_s_write_config16(p2p_bridge
, PCI_COMMAND
, reg16
);
43 pci_s_write_config32(p2p_bridge
, PCI_MEMORY_BASE
, 0x10);
48 /* Enable MMIO window behind the bridge. */
49 pci_s_write_config32(p2p_bridge
, PCI_MEMORY_BASE
,
50 ((base
+ size
- 1) & 0xfff00000) | ((base
>> 16) & 0xfff0));
52 reg16
= pci_s_read_config16(p2p_bridge
, PCI_COMMAND
);
53 reg16
|= PCI_COMMAND_MEMORY
;
54 pci_s_write_config16(p2p_bridge
, PCI_COMMAND
, reg16
);
57 static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge
, u32 mmio_base
, u32 mmio_size
)
59 int timeout
, ret
= -1;
61 /* Secondary bus number is mostly irrelevant as we disable
62 * configuration transactions right after the probe.
67 /* Enable configuration and MMIO over bridge. */
68 pci_s_assert_secondary_reset(p2p_bridge
);
69 pci_s_deassert_secondary_reset(p2p_bridge
);
70 pci_s_bridge_set_secondary(p2p_bridge
, secondary
);
71 pci_s_bridge_set_mmio(p2p_bridge
, mmio_base
, mmio_size
);
73 for (timeout
= 20000; timeout
; timeout
--) {
74 pci_devfn_t dbg_dev
= PCI_DEV(secondary
, dev
, 0);
75 u32 id
= pci_s_read_config32(dbg_dev
, PCI_VENDOR_ID
);
76 if (id
!= 0 && id
!= 0xffffffff && id
!= 0xffff0001)
82 ret
= pci_early_device_probe(secondary
, dev
, mmio_base
);
84 /* Disable MMIO window if we found no suitable device. */
86 pci_s_bridge_set_mmio(p2p_bridge
, 0, 0);
88 /* Resource allocator will reconfigure bridges and secondary bus
89 * number may change. Thus early device cannot reliably use config
90 * transactions from here on, so we may as well disable them.
92 pci_s_bridge_set_secondary(p2p_bridge
, 0);
95 void pci_early_bridge_init(void)
97 /* No PCI-to-PCI bridges are enabled yet, so the one we try to
98 * configure must have its primary on bus 0.
100 pci_devfn_t p2p_bridge
= PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE
,
101 CONFIG_EARLY_PCI_BRIDGE_FUNCTION
);
103 pci_s_early_mmio_window(p2p_bridge
, CONFIG_EARLY_PCI_MMIO_BASE
, 0x4000);
106 /* FIXME: A lot of issues using the following, please avoid.
107 * Assumes 256 PCI busses, scans them all even when PCI bridges are still
108 * disabled. Probes all functions even if 0 is not present.
110 pci_devfn_t
pci_locate_device(unsigned int pci_id
, pci_devfn_t dev
)
112 for (; dev
<= PCI_DEV(255, 31, 7); dev
+= PCI_DEV(0, 0, 1)) {
114 id
= pci_s_read_config32(dev
, 0);
118 return PCI_DEV_INVALID
;
121 pci_devfn_t
pci_locate_device_on_bus(unsigned int pci_id
, unsigned int bus
)
123 pci_devfn_t dev
, last
;
125 dev
= PCI_DEV(bus
, 0, 0);
126 last
= PCI_DEV(bus
, 31, 7);
128 for (; dev
<= last
; dev
+= PCI_DEV(0, 0, 1)) {
130 id
= pci_s_read_config32(dev
, 0);
134 return PCI_DEV_INVALID
;