2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 * Copyright (C) 2014 Sage Electronic Engineering, LLC
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <console/console.h>
19 #include <device/device.h>
20 #include <device/pci.h>
22 #include <cpu/x86/msr.h>
23 #include <cpu/amd/mtrr.h>
24 #include <device/pci_def.h>
25 #include <arch/acpi.h>
26 #include <southbridge/amd/agesa/hudson/pci_devs.h>
27 #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
28 #include <southbridge/amd/common/amd_pci_util.h>
29 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
30 #include <northbridge/amd/agesa/BiosCallOuts.h>
31 #include <northbridge/amd/agesa/state_machine.h>
33 /***********************************************************
34 * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
35 * This table is responsible for physically routing the PIC and
36 * IOAPIC IRQs to the different PCI devices on the system. It
37 * is read and written via registers 0xC00/0xC01 as an
38 * Index/Data pair. These values are chipset and mainboard
39 * dependent and should be updated accordingly.
41 * These values are used by the PCI configuration space,
42 * MP Tables. TODO: Make ACPI use these values too.
44 const u8 mainboard_picr_data
[FCH_INT_TABLE_SIZE
] = {
46 [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
47 /* Misc-nil,0,1,2, INT from Serial irq */
48 [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
49 /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
50 [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
52 [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
53 /* USB Devs 18/19/22 INTA-C */
54 [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
59 const u8 mainboard_intr_data
[FCH_INT_TABLE_SIZE
] = {
61 [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
62 /* Misc-nil,0,1,2, INT from Serial irq */
63 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
64 /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
65 [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
67 [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
68 /* USB Devs 18/19/20/22 INTA-C */
69 [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
75 * This table defines the index into the picr/intr_data
76 * tables for each device. Any enabled device and slot
77 * that uses hardware interrupts should have an entry
78 * in this table to define its index into the FCH
79 * PCI_INTR register 0xC00/0xC01. This index will define
80 * the interrupt that it should use. Putting PIRQ_A into
81 * the PIN A index for a device will tell that device to
82 * use PIC IRQ 10 if it uses PIN A for its hardware INT.
84 static const struct pirq_struct mainboard_pirq_data
[] = {
85 /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
86 {GFX_DEVFN
, {PIRQ_A
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* VGA: 01.0 */
87 {ACTL_DEVFN
,{PIRQ_NC
, PIRQ_B
, PIRQ_NC
, PIRQ_NC
}}, /* Audio: 01.1 */
88 {NB_PCIE_PORT1_DEVFN
, {PIRQ_A
, PIRQ_B
, PIRQ_C
, PIRQ_D
}}, /* x4 PCIe: 02.1 */
89 {NB_PCIE_PORT2_DEVFN
, {PIRQ_B
, PIRQ_C
, PIRQ_D
, PIRQ_A
}}, /* mPCIe: 02.2 */
90 {NB_PCIE_PORT3_DEVFN
, {PIRQ_C
, PIRQ_D
, PIRQ_A
, PIRQ_B
}}, /* NIC: 02.3 */
91 {NB_PCIE_PORT4_DEVFN
, {PIRQ_D
, PIRQ_A
, PIRQ_B
, PIRQ_C
}}, /* Edge: 02.4 */
92 {NB_PCIE_PORT5_DEVFN
, {PIRQ_E
, PIRQ_F
, PIRQ_G
, PIRQ_H
}}, /* Edge: 02.5 */
93 {XHCI_DEVFN
, {PIRQ_C
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* XHCI: 10.0 */
94 {SATA_DEVFN
, {PIRQ_SATA
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* SATA: 11.0 */
95 {OHCI1_DEVFN
, {PIRQ_OHCI1
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* OHCI1: 12.0 */
96 {EHCI1_DEVFN
, {PIRQ_NC
, PIRQ_EHCI1
, PIRQ_NC
, PIRQ_NC
}}, /* EHCI1: 12.2 */
97 {OHCI2_DEVFN
, {PIRQ_OHCI2
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* OHCI2: 13.0 */
98 {EHCI2_DEVFN
, {PIRQ_NC
, PIRQ_EHCI2
, PIRQ_NC
, PIRQ_NC
}}, /* EHCI2: 13.2 */
99 {SMBUS_DEVFN
, {PIRQ_SMBUS
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* SMBUS: 14.0 */
100 {HDA_DEVFN
, {PIRQ_HDA
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* HDA: 14.2 */
101 {SD_DEVFN
, {PIRQ_SD
, PIRQ_NC
, PIRQ_NC
, PIRQ_NC
}}, /* SD: 14.7 */
104 const u8
*picr_data
= mainboard_picr_data
;
105 const u8
*intr_data
= mainboard_intr_data
;
108 static void pirq_setup(void)
110 pirq_data_ptr
= mainboard_pirq_data
;
111 pirq_data_size
= sizeof(mainboard_pirq_data
) / sizeof(struct pirq_struct
);
112 intr_data_ptr
= mainboard_intr_data
;
113 picr_data_ptr
= mainboard_picr_data
;
116 /**********************************************
117 * enable the dedicated function in mainboard.
118 **********************************************/
119 static void mainboard_enable(device_t dev
)
121 printk(BIOS_INFO
, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER
" Enable.\n");
123 /* Initialize the PIRQ data structures for consumption */
127 struct chip_operations mainboard_ops
= {
128 .enable_dev
= mainboard_enable
,