src/mainboard/google/stout/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef STOUT_GPIO_H
  17 #define STOUT_GPIO_H
  18
  19 #include <southbridge/intel/common/gpio.h>
  20
  21 static const struct pch_gpio_set1 pch_gpio_set1_mode = {
  22         .gpio0  = GPIO_MODE_GPIO,       /* GPIO0 */
  23         .gpio1  = GPIO_MODE_GPIO,       /* SIO_EXT_SMI# */
  24         .gpio2  = GPIO_MODE_NONE,       /* NOT USED */
  25         .gpio3  = GPIO_MODE_NONE,       /* NOT USED */
  26         .gpio4  = GPIO_MODE_NONE,       /* NOT USED */
  27         .gpio5  = GPIO_MODE_GPIO,       /* INTH# */
  28         .gpio6  = GPIO_MODE_GPIO,       /* SIO_EXT_SCI# */
  29         .gpio7  = GPIO_MODE_GPIO,       /* GE_SCR_WP# */
  30         .gpio8  = GPIO_MODE_NONE,       /* NOT USED */
  31         .gpio9  = GPIO_MODE_NATIVE,     /* USB_OC5# */
  32         .gpio10 = GPIO_MODE_NATIVE,     /* USB_OC6# */
  33         .gpio11 = GPIO_MODE_NATIVE,     /* SMBALERT# */
  34         .gpio12 = GPIO_MODE_GPIO,       /* GPIO12 */
  35         .gpio13 = GPIO_MODE_GPIO,       /* GPIO13 */
  36         .gpio14 = GPIO_MODE_NATIVE,     /* USB_OC7# */
  37         .gpio15 = GPIO_MODE_GPIO,       /* GPIO15 */
  38         .gpio16 = GPIO_MODE_GPIO,       /* WWAN_LED_ON */
  39         .gpio17 = GPIO_MODE_GPIO,       /* WLAN_LED_ON */
  40         .gpio18 = GPIO_MODE_NATIVE,     /* PCIE_CLKREQ_WLAN# */
  41         .gpio19 = GPIO_MODE_GPIO,       /* BBS_BIT0 */
  42         .gpio20 = GPIO_MODE_NATIVE,     /* PCIE_CLKREQ_CARD# */
  43         .gpio21 = GPIO_MODE_GPIO,       /* BT_DET# / TP29 */
  44         .gpio22 = GPIO_MODE_GPIO,       /* MODEL_ID0 */
  45         .gpio23 = GPIO_MODE_GPIO,       /* LCD_BK_OFF */
  46         .gpio24 = GPIO_MODE_NATIVE,     /* GPIO24 */
  47         .gpio25 = GPIO_MODE_NATIVE,     /* PCIE_REQ_WWAN# / TP89 */
  48         .gpio26 = GPIO_MODE_NATIVE,     /* CLK_PCIE_REQ4# / TP59 */
  49         .gpio27 = GPIO_MODE_GPIO,       /* MSATA_DTCT# */
  50         .gpio28 = GPIO_MODE_GPIO,       /* PLL_ODVR_EN */
  51         .gpio29 = GPIO_MODE_GPIO,       /* WLAN_AOAC_ON */
  52         .gpio30 = GPIO_MODE_NATIVE,     /* SUS_PWR_ACK */
  53         .gpio31 = GPIO_MODE_NATIVE,     /* AC_PRESENT */
  54 };
  55
  56 static const struct pch_gpio_set1 pch_gpio_set1_direction = {
  57         /*
  58          * Note: Only gpio configured as "gpio" or "none" need to have the
  59          *       direction configured.
  60          */
  61         .gpio0  = GPIO_DIR_OUTPUT,
  62         .gpio1  = GPIO_DIR_INPUT,
  63         .gpio2  = GPIO_DIR_INPUT,
  64         .gpio3  = GPIO_DIR_INPUT,
  65         .gpio4  = GPIO_DIR_INPUT,
  66         .gpio5  = GPIO_DIR_OUTPUT,
  67         .gpio6  = GPIO_DIR_INPUT,
  68         .gpio7  = GPIO_DIR_INPUT,
  69         .gpio8  = GPIO_DIR_INPUT,
  70
  71         .gpio12 = GPIO_DIR_OUTPUT,
  72         .gpio13 = GPIO_DIR_OUTPUT,
  73
  74         .gpio15 = GPIO_DIR_INPUT,
  75         .gpio16 = GPIO_DIR_OUTPUT,
  76         .gpio17 = GPIO_DIR_OUTPUT,
  77
  78         .gpio19 = GPIO_DIR_OUTPUT,
  79
  80         .gpio21 = GPIO_DIR_OUTPUT,
  81         .gpio22 = GPIO_DIR_INPUT,
  82         .gpio23 = GPIO_DIR_OUTPUT,
  83
  84         .gpio27 = GPIO_DIR_INPUT,
  85         .gpio28 = GPIO_DIR_OUTPUT,
  86         .gpio29 = GPIO_DIR_OUTPUT,
  87 };
  88
  89 static const struct pch_gpio_set1 pch_gpio_set1_level = {
  90         /*
  91          * Note: Only gpio configured as "gpio" or "none" need to have the
  92          *       level set.
  93          */
  94         .gpio0  = GPIO_LEVEL_HIGH,
  95         .gpio1  = GPIO_LEVEL_LOW,
  96         .gpio2  = GPIO_LEVEL_LOW,
  97         .gpio3  = GPIO_LEVEL_LOW,
  98         .gpio4  = GPIO_LEVEL_LOW,
  99         .gpio5  = GPIO_LEVEL_HIGH,
 100         .gpio6  = GPIO_LEVEL_LOW,
 101         .gpio7  = GPIO_LEVEL_HIGH,
 102         .gpio8  = GPIO_LEVEL_LOW,
 103
 104         .gpio12 = GPIO_LEVEL_LOW,
 105         .gpio13 = GPIO_LEVEL_LOW,
 106
 107         .gpio15 = GPIO_LEVEL_LOW,
 108         .gpio16 = GPIO_LEVEL_HIGH,
 109         .gpio17 = GPIO_LEVEL_LOW,
 110
 111         .gpio19 = GPIO_LEVEL_LOW,
 112
 113         .gpio21 = GPIO_LEVEL_LOW,
 114         .gpio22 = GPIO_LEVEL_LOW,
 115         .gpio23 = GPIO_LEVEL_LOW,
 116
 117         .gpio27 = GPIO_LEVEL_LOW,
 118         .gpio28 = GPIO_LEVEL_HIGH,
 119         .gpio29 = GPIO_LEVEL_HIGH,
 120 };
 121
 122 static const struct pch_gpio_set1 pch_gpio_set1_invert = {
 123         .gpio1 = GPIO_INVERT,
 124         .gpio6 = GPIO_INVERT,
 125         .gpio8 = GPIO_INVERT,
 126 };
 127
 128 static const struct pch_gpio_set2 pch_gpio_set2_mode = {
 129         .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */
 130         .gpio33 = GPIO_MODE_GPIO,   /* GPIO33 */
 131         .gpio34 = GPIO_MODE_GPIO,   /* CCD_ON */
 132         .gpio35 = GPIO_MODE_GPIO,   /* BT_ON */
 133         .gpio36 = GPIO_MODE_NONE,   /* NOT USED */
 134         .gpio37 = GPIO_MODE_NONE,   /* NOT USED */
 135         .gpio38 = GPIO_MODE_NONE,   /* NOT USED */
 136         .gpio39 = GPIO_MODE_NONE,   /* NOT USED */
 137         .gpio40 = GPIO_MODE_GPIO,   /* USB_OC1# */
 138         .gpio41 = GPIO_MODE_GPIO,   /* USB_OC2# */
 139         .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */
 140         .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */
 141         .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */
 142         .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */
 143         .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */
 144         .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */
 145         .gpio48 = GPIO_MODE_GPIO,   /* DIS_BT_ON# */
 146         .gpio49 = GPIO_MODE_GPIO,   /* GPIO49 */
 147         .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */
 148         .gpio51 = GPIO_MODE_GPIO,   /* BBS_BIT1 */
 149         .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */
 150         .gpio53 = GPIO_MODE_GPIO,   /* PWM_SELECT# / TP44 */
 151         .gpio54 = GPIO_MODE_GPIO,   /* PCI_REQ3# */
 152         .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */
 153         .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */
 154         .gpio57 = GPIO_MODE_GPIO,   /* PCH_GPIO57 */
 155         .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */
 156         .gpio59 = GPIO_MODE_GPIO,   /* USB_OC0_1# */
 157         .gpio60 = GPIO_MODE_GPIO,   /* DRAMRST_CNTRL_PCH */
 158         .gpio61 = GPIO_MODE_GPIO,   /* LPCPD# */
 159         .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */
 160         .gpio63 = GPIO_MODE_NATIVE, /* TP51 */
 161 };
 162
 163 static const struct pch_gpio_set2 pch_gpio_set2_direction = {
 164         /*
 165          * Note: Only gpio configured as "gpio" or "none" need to have the
 166          *       direction configured.
 167          */
 168         .gpio33 = GPIO_DIR_OUTPUT,
 169         .gpio34 = GPIO_DIR_OUTPUT,
 170         .gpio35 = GPIO_DIR_OUTPUT,
 171         .gpio36 = GPIO_DIR_INPUT,
 172         .gpio37 = GPIO_DIR_INPUT,
 173         .gpio38 = GPIO_DIR_INPUT,
 174         .gpio39 = GPIO_DIR_INPUT,
 175         .gpio40 = GPIO_DIR_INPUT,
 176         .gpio41 = GPIO_DIR_INPUT,
 177
 178         .gpio48 = GPIO_DIR_OUTPUT,
 179         .gpio49 = GPIO_DIR_INPUT,
 180
 181         .gpio51 = GPIO_DIR_OUTPUT,
 182
 183         .gpio53 = GPIO_DIR_OUTPUT,
 184         .gpio54 = GPIO_DIR_INPUT,
 185
 186         .gpio57 = GPIO_DIR_INPUT,
 187
 188         .gpio59 = GPIO_DIR_INPUT,
 189         .gpio60 = GPIO_DIR_OUTPUT,
 190         .gpio61 = GPIO_DIR_OUTPUT,
 191 };
 192
 193 static const struct pch_gpio_set2 pch_gpio_set2_level = {
 194         /*
 195          * Note: Only gpio configured as "gpio" or "none" need to have the
 196          *       level set.
 197          */
 198         .gpio33 = GPIO_LEVEL_LOW,
 199         .gpio34 = GPIO_LEVEL_HIGH,
 200         .gpio35 = GPIO_LEVEL_HIGH,
 201         .gpio36 = GPIO_LEVEL_LOW,
 202         .gpio37 = GPIO_LEVEL_LOW,
 203         .gpio38 = GPIO_LEVEL_LOW,
 204         .gpio39 = GPIO_LEVEL_LOW,
 205         .gpio40 = GPIO_LEVEL_HIGH,
 206         .gpio41 = GPIO_LEVEL_LOW,
 207
 208         .gpio48 = GPIO_LEVEL_LOW,
 209         .gpio49 = GPIO_LEVEL_HIGH,
 210
 211         .gpio51 = GPIO_LEVEL_HIGH,
 212
 213         .gpio53 = GPIO_LEVEL_HIGH,
 214         .gpio54 = GPIO_LEVEL_LOW,
 215
 216         .gpio57 = GPIO_LEVEL_LOW,
 217
 218         .gpio59 = GPIO_LEVEL_HIGH,
 219         .gpio60 = GPIO_LEVEL_HIGH,
 220         .gpio61 = GPIO_LEVEL_LOW,
 221 };
 222
 223 static const struct pch_gpio_set3 pch_gpio_set3_mode = {
 224         .gpio64 = GPIO_MODE_GPIO,       /* CLK_FLEX0 / TP38 */
 225         .gpio65 = GPIO_MODE_GPIO,       /* CLK_FLEX1 / TP45 */
 226         .gpio66 = GPIO_MODE_GPIO,       /* CLK_FLEX2 / TP83 */
 227         .gpio67 = GPIO_MODE_GPIO,       /* CLK_FLEX3 / TP82 */
 228         .gpio68 = GPIO_MODE_GPIO,       /* WWAN_DTCT# */
 229         .gpio69 = GPIO_MODE_GPIO,       /* GPIO69 */
 230         .gpio70 = GPIO_MODE_GPIO,       /* WLAN_OFF# */
 231         .gpio71 = GPIO_MODE_GPIO,       /* WWAN_OFF# */
 232         .gpio72 = GPIO_MODE_GPIO,       /* PM_BATLOW# */
 233         .gpio73 = GPIO_MODE_NATIVE,     /* PCIECLKRQ0# / TP39 */
 234         .gpio74 = GPIO_MODE_NATIVE,     /* SML1ALERT#_R / TP56 */
 235         .gpio75 = GPIO_MODE_NATIVE,     /* SMB_ME1_DAT */
 236 };
 237
 238 static const struct pch_gpio_set3 pch_gpio_set3_direction = {
 239         /*
 240          * Note: Only gpio configured as "gpio" or "none" need to have the
 241          *       direction configured.
 242          */
 243         .gpio64 = GPIO_DIR_OUTPUT,
 244         .gpio65 = GPIO_DIR_OUTPUT,
 245         .gpio66 = GPIO_DIR_OUTPUT,
 246         .gpio67 = GPIO_DIR_INPUT,
 247         .gpio68 = GPIO_DIR_INPUT,
 248         .gpio69 = GPIO_DIR_OUTPUT,
 249         .gpio70 = GPIO_DIR_OUTPUT,
 250         .gpio71 = GPIO_DIR_OUTPUT,
 251         .gpio72 = GPIO_DIR_OUTPUT,
 252 };
 253
 254 static const struct pch_gpio_set3 pch_gpio_set3_level = {
 255         /*
 256          * Note: Only gpio configured as "gpio" or "none" need to have the
 257          *       level set.
 258          */
 259         .gpio64 = GPIO_LEVEL_HIGH,
 260         .gpio65 = GPIO_LEVEL_LOW,
 261         .gpio66 = GPIO_LEVEL_HIGH,
 262         .gpio67 = GPIO_LEVEL_LOW,
 263         .gpio68 = GPIO_LEVEL_HIGH,
 264         .gpio69 = GPIO_LEVEL_LOW,
 265         .gpio70 = GPIO_LEVEL_HIGH,
 266         .gpio71 = GPIO_LEVEL_HIGH,
 267         .gpio72 = GPIO_LEVEL_HIGH,
 268 };
 269
 270 const struct pch_gpio_map mainboard_gpio_map = {
 271         .set1 = {
 272                 .mode      = &pch_gpio_set1_mode,
 273                 .direction = &pch_gpio_set1_direction,
 274                 .level     = &pch_gpio_set1_level,
 275                 .invert    = &pch_gpio_set1_invert,
 276         },
 277         .set2 = {
 278                 .mode      = &pch_gpio_set2_mode,
 279                 .direction = &pch_gpio_set2_direction,
 280                 .level     = &pch_gpio_set2_level,
 281         },
 282         .set3 = {
 283                 .mode      = &pch_gpio_set3_mode,
 284                 .direction = &pch_gpio_set3_direction,
 285                 .level     = &pch_gpio_set3_level,
 286         },
 287 };
 288 #endif